WED2ZL361MV50BC

White Electronic Designs 1Mx36 Synchronous Pipeline Burst NBL SRAM FEATURES Fast clock speed: 166, 150, 133, and 100MHz Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Single +3.3V ± 5% power supply (VCC) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging: • 119-bump BGA package Low capacitive bus loading This product is subject to change without notice. WED2ZL361MV DESCRIPTION The WEDC SyncBurst — SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18 SRAMs into a single BGA package to provide 1M x 36 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The NBL or No Bus Latency Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied “High or Low.” Asynchronous inputs include the sleep mode enable (ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. FIGURE 1 – PIN CONFIGURATION (Top View) 1 VCC SA NC DQC DQC VCC DQC DQC VCC DQD DQD VCC DQD DQD NC NC VCC 2 SA CE2 SA DQPC DQC DQC DQC DQC VCC DQD DQD DQD DQD DQPD SA NC NC 3 SA SA SA VSS VSS VSS BWC# VSS NC VSS BWD# VSS VSS VSS LBO SA NC 4 SA ADV# VCC NC CE1# OE# SA WE# VCC CLK NC CKE# SA1 SA0 VCC SA NC 5 SA SA SA VSS VSS VSS BWB# VSS NC VSS BWA# VSS VSS VSS NC SA NC 6 SA CE2# SA DQPB DQB DQB DQB DQB VCC DQA DQA DQA DQA DQPA SA NC NC 7 VCC NC NC DQB DQB VCC DQB DQB VCC DQA DQA VCC DQA DQA NC ZZ VCC Block Diagram BWc# BWd# BWb# BWa# A B C D E F G H J K L M N P R T U 1M x 18 CLK CKE# ADV# LBO# CE1# CE2 CE2# OE# WE# ZZ CLK CKE# ADV# LBO# CS1# CS2 CS2# OE# WE# ZZ CLK CKE# ADV# LBO# CS1# CS2 CS2# OE# WE# ZZ 1M x 18 Address Bus (SA0 - SA19) DQc, DQd DQPc, DQPd DQa, DQb DQPa, DQPb DQa - DQd DQPa - DQPd June 2004 Rev. 3 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FUNCTION DESCRIPTION The WED2ZL361MV is an NBL SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE#, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV# input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV#). ADV# should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable (CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NBL SSRAM latches external address and initiates a cycle when CKE and ADV are driven low at the rising edge of the clock. Output Enable (OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, the write enable input signals WE# are driven high, and ADV# driven low. The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE# must be driven low for the device to drive out the requested data. WED2ZL361MV Write operation occurs when WE# is driven low at the rising edge of the clock. BW#[d:a] can be used for byte write operation. The pipe-lined NBL SSRAM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE# and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates after 2 cycles of wake up time. BURST SEQUENCE TABLE (Interleaved Burst, LBO = High) Case 1 LBO Pin First Address High A1 0 0 1 Fourth Address 1 A0 0 1 0 1 Case 2 A1 0 0 1 1 A0 1 0 1 0 Case 3 A1 1 1 0 0 A0 0 1 0 1 Case 4 A1 1 1 0 0 A0 1 0 1 0 Fourth Address LBO Pin First Address High (Linear Burst, LBO = Low) Case 1 A1 0 0 1 1 A0 0 1 0 1 Case 2 A1 0 1 1 0 A0 1 0 1 0 Case 3 A1 1 1 0 0 A0 0 1 0 1 Case 4 A1 1 0 0 1 A0 1 0 1 0 NOTE 1: LBO pin must be tied to High or Low, and Floating State must not be allowed. June 2004 Rev. 3 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs TRUTH TABLES Synchronous Truth Table CEx# H X L X L X L X L X X ADV# L H L H L H L H L H X WE# X X H X H X L X L X X BWx# X X X X X X L L H H X OE# X X L L H H X X X X X CKE# L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ Address Accessed N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address WED2ZL361MV Operation Deselect Continue Deselect Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock NOTES: 1. X means “Don’t Care.” 2. The rising edge of clock is symbolized by ( ↑ ) 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE# = L means Write operation in WRITE TRUTH TABLE. WRITE# = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins (ZZ and OE#). 6. CEx# refers to the combination of CE1#, CE2# and CE2#. Write Truth Table WE# H L L L L L L BWa# X L H H H L H BWb# X H L H H L H BWc# X H H L H L H BWd# X H H H L L H Operation Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write Abort/NOP NOTES: 1. X means “Don’t Care.” 2. All inputs in this table must meet setup and hold time around the rising edge of CLK ( ↑ ). June 2004 Rev. 3 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Absolute Maximum Ratings* Voltage on VCC Supply Relative to VSS VIN (DQx) VIN (Inputs) Storage Temperature (BGA) Short Circuit Output Current WED2ZL361MV -0.3V to +4.6V -0.3V to +4.6V -0.3V to +4.6V -65°C to +150°C 100mA * Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. Recommended DC Operating Conditions Voltage Referenced to: VSS = 0V, = 0°C ≤ TA ≤ +70°C; Commercial or -40°C ≤ TA ≤ +85°C; Industrial Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Symbol VIH VIL ILI ILO VOH VOL VCC Conditions Min 2.0 -0.3 -5 -5 2.4 – 3.135 Max VCC +0.5 0.8 5 5 – 0.4 3.465 Units V V µA µA V V V Notes 1 1 2 1 1 1 0V ≤ VIN ≤ VCC Output(s) Disabled, 0V ≤ VIN ≤ VCC IOH = -4.0mA IOL = 8.0mA NOTES: 1. All voltages referenced to VSS (GND) 2. ZZ pin has an internal pull-up, and input leakage = ± 10µA. DC Characteristics 166 Description Power Supply Current: Operating Power Supply Current: Standby Power Supply Current: Current Clock Running Standby Current Symbol Conditions Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle Time = IDD TCYC MIN; VCC = MAX; Output Open ISB2 Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2 or VCC - 0.2; All Inputs Static; CLK Frequency = 0; ZZ ≤ VIL ISB3 Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle Time = TCYC MIN; VCC = MAX; Output Open; ZZ ≥ VCC - 0.2V ISB4 Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2 or VCC - 0.2; Cycle Time = TCYC MIN; ZZ ≤ VIL Typ MHz 840 60 60 240 150 MHz 800 60 60 220 133 MHz 760 60 60 180 100 MHz 640 60 60 160 Units mA mA mA mA Notes 1, 2 2 2 2 30 30 NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. Typical values are measured at 3.3V, 25°C, and 10ns cycle time. BGA Capacitance Description Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance NOTES: 1. This parameter is sampled. June 2004 Rev. 3 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com Symbol CI CO CA CCK Conditions TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz Typ 5 6 5 3 Max 7 8 7 5 Units pF pF pF pF Notes 1 1 1 1 White Electronic Designs AC Characteristics Parameter Clock Time Clock Access Time Output enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High CKE Setup to Clock High Data Setup to Clock High Write Setup to Clock High Address Advance to Clock High Chip Select Setup to Clock High Address Hold to Clock high CKE Hold to Clock High Data Hold to Clock High Write Hold to Clock High Address Advance to Clock High Chip Select Hold to Clock High Symbol TCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tCES tDS tWS tADVS tCSS tAH tCEH tDH tWH tADVH tCSH 166MHz Min Max 6.0 — 3.5 — 3.5 1.5 — 1.5 — 0.0 — — 3.0 — 3.0 2.2 — 2.2 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 150MHz Min Max 6.7 — 3.8 — 3.8 1.5 — 1.5 — 0.0 — — 3.0 — 3.0 2.5 — 2.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — WED2ZL361MV 133MHz Min Max 7.5 — 4.2 — 4.2 1.5 — 1.5 — 0.0 — — 3.5 — 3.5 3.0 — 3.0 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 100MHz Min Max 10.0 — 5.0 — 5.0 1.5 — 1.5 — 0.0 — — 3.5 — 3.5 3.0 — 3.0 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV# is sampled low and CEx# is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CLK (when ADV# is Low) to remain enabled. 3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV# Low. Both cases must meet setup and hold times. AC Test Conditions VSS = 0V, = 0°C ≤ TA ≤ +70°C, VCC = 3.3V ± 5%; Commercial or -40°C ≤ TA ≤ +85°C, VCC = 3.3V ± 5%; Industrial Parameter Input Pulse Level Input Rise and Fall Time (Measured at 20% to 80%) Input and Output Timing Reference Levels Output Load Value 0 to 3.0V 1.0V/ns 1.5V See Output Load (A) Output Load (A) DOUT Zo=50Ω RL=50Ω 30pF* VL=1.5V Output Load (B) for a tLZC, tLZOE, tHZOE, and tHZC +3.3V DOUT 353 Ω 3.9 Ω 5pF* *Including Scope and Jig Capacitance June 2004 Rev. 3 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time Z is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. WED2ZL361MV When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current Conditions ZZ ≥ VIH SYMBOL ISB2Z tZZ tRZZ tZZI tRZZI Min Max 10 2(tKC) 2(tKC) Units mA ns ns ns ns Notes 1 1 1 1 2(tKC) FIGURE 2 – SNOOZE MODE TIMING DIAGRAM CLOCK t ZZ ZZ t RZZ t ZZI ISUPPLY t RZZI I ISB2Z ALL INPUTS (except ZZ) DESELECT or READ Only Output (Q) HIGH-Z DON'T CARE June 2004 Rev. 3 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 3 – TIMING WAVEFORM OF READ CYCLE tCH tCL WED2ZL361MV Clock tAS tAH A1 A2 A3 Address tWS tWH WRITE# tCSS tCSH CEx# tADVS tADVH ADV OE# tOE tLZOE tHZOE Q1-1 tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 tHZC Q3-4 Data Out NOTES: WRITE = L means WE = L, and BWx = L CEx# refers to the combination of CE1#, CE2 and CE2#. Don't Care Undefined June 2004 Rev. 3 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIGURE 4 – TIMING WAVEFORM OF WRITE CYCLE WED2ZL361MV tCH tCL Clock Address A1 A2 A3 WRITE# CEx# ADV OE# tDS tDH D3-2 D3-3 D3-4 Data In tHZOE D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 Data Out Q0-3 Q0-4 NOTES: WRITE# = L means WE# = L, and BWx = L CEx# refers to the combination of CE1#, CE2 and CE2#. Don't Care Undefined June 2004 Rev. 3 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED2ZL361MV FIGURE 5 – TIMING WAVEFORM OF SINGLE READ/WRITE tCH tCL Clock Address A1 A2 A3 A4 A5 A6 A7 A8 A9 WRITE# CEx# ADV OE# tOE tLZOE Data Out Q1 tDS tDH D2 Q3 Q4 Q6 Q7 Data In D5 Don't Care NOTES: WRITE = L means WE = L, and BWx = L CEx# refers to the combination of CE1#, CE2 and CE2#. Undefined June 2004 Rev. 3 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED2ZL361MV FIGURE 6 – TIMING WAVEFORM OF CKE# OPERATION tCH tCL Clock tCES tCEH tCYC CKE Address A1 A2 A3 A4 A5 A6 WRITE# CEx# ADV OE# tCD tLZC tHZC Q1 tDS tDH D2 Q3 Q4 Data Out Data In NOTES: WRITE# = L means WE = L, and BWx = L CEx# refers to the combination of CE1#, CE2 and CE2#. Don't Care Undefined June 2004 Rev. 3 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED2ZL361MV FIGURE 7 – TIMING WAVEFORM OF CE# OPERATION tCH tCL Clock tCYC Address A1 A2 A3 A4 A5 WRITE# CEx# ADV OE# tOE tLZOE tHZC Q1 Q2 tDS tDH tCD tLZC Q4 Data Out Data In D3 D5 NOTES: WRITE# = L means WE = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Don't Care Undefined June 2004 Rev. 3 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE DIMENSION: 119 BUMP PBGA 1.90 (0.075) MAX WED2ZL361MV 7.62 (0.300) TYP A B C D E F G 17.00 (0.669) TYP A1 CORNER 1.27 (0.050) TYP 23.00 (0.905) TYP 20.32 (0.800) TYP H J K L M N P R T U 1.27 (0.050) TYP 0.711 (0.028) MAX NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION Commercial Temp Range (0°C to 70°C) Part Number WED2ZL361MV35BC WED2ZL361MV38BC WED2ZL361MV42BC WED2ZL361MV50BC Configuration 1M x 36 1M x 36 1M x 36 1M x 36 tCD (ns) 3.5 3.8 4.2 5.0 Clock (MHz) 166 150 133 100 Industrial Temp Range (-40°C to +85°C) Part Number WED2ZL361MV35BI WED2ZL361MV38BI WED2ZL361MV42BI WED2ZL361MV50BI Configuration 1M x 36 1M x 36 1M x 36 1M x 36 tCD (ns) 3.5 3.8 4.2 5.0 Clock (MHz) 166 150 133 100 June 2004 Rev. 3 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com