WED2ZLRSP01S

White Electronic Designs 512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM FEATURES Fast clock speed: 166, 150, 133, and 100MHz Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Single +2.5V ± 5% power supply (VCC) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging: 209-bump BGA package Low capacitive bus loading WED2ZLRSP01S DESCRIPTION The WED2ZLRSP01S, Dual Independent Array, NBLSSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the first organized as a 512K x 32, and the second a 256K x 32. All Synchronous inputs pass through registers controlled by a positive edge triggered, single clock input per array. The NBL or No Bus Latency Memory provides 100% bus utilizaton, with no loss of cycles caused by change in modal operation (Write to Read/Read to Write). All inputs except for Asynchronous Output Enable and Burst Mode control are synchronized on the positive or rising edge of Clock. Burst order control must be tied either HIGH or LOW, Write cycles are internally self-timed, and writes are initiated on the rising edge of clock. This feature eliminates the need for complex off-chip write pulse generation and proved increased timing flexibility for incoming signals. PIN CONFIGURATION (TOP VIEW) 1 Vss NC A_ADR A_ADR A_ADR A_ADR A_ADR NC Vss Vss Vss NC B_ADR B_ADR B_ADR B_ADR B_ADR NC Vss 2 A_DATb0 A_DATb4 A_ADR Vss A_CK Vss A_ADR A_DATc0 A_DATc4 Vss B_DATb0 B_DATb4 B_ADR Vss B_CK Vss NC B_DATc4 B_DATc0 3 A_DATb1 A_DATb5 A_OE# A_CKE# A_GWE# A_CS2# A_CS1# A_DATc1 A_DATc5 Vss B_DATb1 B_DATb5 B_OE# B_CKE# B_GWE# B_CS2# B_CS1# B_DATc5 B_DATc1 4 A_DATb2 A_DATb6 A_ADV Vcc Vcc Vcc A_CS2 A_DATc2 A_DATc6 Vss B_DATb2 B_DATb6 B_ADV Vcc Vcc Vcc B_CS2 B_DATc6 B_DATc2 5 A_DATb3 A_DATb7 A_BWEb Vcc Vcc Vcc A_BWEc A_DATc3 A_DATc7 Vss B_DAT3 B_DAT7 B_BWEb Vcc Vcc Vcc B_BWEc B_DATc7 B_DATc3 6 Vss Vss Vss Vcc Vcc Vcc Vss Vss Vss Vss Vss Vss Vss Vcc Vcc Vcc Vss Vss Vss 7 A_DATa0 A_DATa4 A_BWEa Vcc Vcc Vcc A_BWEd A_DATd0 A_DATd4 Vss B_DATa0 B_DATa4 B_BWEa Vcc Vcc Vcc B_BWEd B_DATd4 B_DATd0 8 A_DATa1 A_DATa5 A_ZZ Vcc Vcc Vcc A_LBO# A_DATd1 A_DATd5 Vss B_DATa1 B_DATa5 B_ZZ Vcc Vcc Vcc B_LBO# B_DATd5 B_DATd1 9 A_DATa2 A_DATa6 A_ADR Vcc Vcc Vcc A_ADR A_DATd2 A_DATd6 Vss B_DATa2 B_DATa6 B_ADR Vcc Vcc Vcc B_ADR B_DATd6 B_DATd2 10 A_DATa3 A_DATa7 A_ADR A_ADR A_ADR1 A_ADR A_ADR A_DATd3 A_DATd7 Vss B_DATa3 B_DATa7 B_ADR B_ADR B_ADR1 B_ADR B_ADR B_DATd7 B_DATd3 11 Vss NC A_ADR A_ADR A_ADR0 A_ADR A_ADR NC Vss Vss Vss NC B_ADR B_ADR B_ADR0 B_ADR B_ADR NC Vss A B C D E F G H J K L M N P R T U V W White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 1 BLOCK DIAGRAM A_SA0-18 B_SA0-17 A_DQ0-31 B_DQ0-31 WED2ZLRSP01S A_LBO# A_ZZ A_ADV A_OE# A_CKE# A_WE# A_CK A_BWA# A_BWB# A_BWC# A_BWD# A_CS2# A_CS2 A_CS1# LBO# ZZ ADV OE# CKE# WE# CK BWa# BWb# BWc# BWd# CS2# CS2 CS1# U1 DQ0-31 512K x 32 B_LBO# B_ZZ B_ADV B_OE# B_CKE# B_WE# B_CK B_BWA# B_BWB# B_BWC# B_BWD# B_CS2# B_CS2 B_CS1# LBO# ZZ ADV OE# CKE# WE# CK BWa# BWb# BWc# BWd# CS2# CS2 CS1# U2 DQ0-31 256K x 32 White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FUNCTION DESCRIPTION The WED2ZLRSP01S is an NBL Dual Array SSRAM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE#, LBO# and ZZ) are synchronized to rising clock edges, and all features are available on each of the independent arrays. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable (CKE#) pin allows the operation of the chip to be suspended as long as necessary. When CKE# is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NBL SSRAM latches external address and initiates a cycle when CKE# and ADV are driven low at the rising edge of the clock. Output Enable (OE#) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE# is driven low, the write enable input signals WE# are driven high, and ADV driven low. The internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the output register. At the second clock edge the data is driven out of the SRAM. During read operation OE# must be driven low for the device to drive out the requested data. WED2ZLRSP01S Write operation occurs when WE# is driven low at the rising edge of the clock. BW#[d:a] can be used for byte write operation. The pipe-lined NBL SSRAM uses a late-late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required two cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO# pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates after 2 cycles of wake up time. BURST SEQUENCE TABLE (Interleaved Burst, LBO# = High) Case 1 LBO# Pin High First Address A1 0 0 1 1 A0 0 1 0 1 Case 2 A1 0 0 1 1 A0 1 0 1 0 Case 3 A1 1 1 0 0 A0 0 1 0 1 Case 4 A1 1 1 0 0 A0 1 0 1 0 LBO# Pin High First Address (Interleaved Burst, LBO = High) Case 1 A1 0 0 1 1 A0 0 1 0 1 Case 2 A1 0 1 1 0 A0 1 0 1 0 Case 3 A1 1 1 0 0 A0 0 1 0 1 Case 4 A1 1 0 0 1 A0 1 0 1 0 ↓ Fourth Address ↓ Fourth Address NOTE 1: LBO# pin must be tied to High or Low, and Floating State must not be allowed. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs TRUTH TABLES SYNCHRONOUS TRUTH TABLE CEx# H X L X L X L X L X X ADV L H L H L H L H L H X WE# X X H X H X L X L X X BWx# X X X X X X L L H H X OE# X X L L H H X X X X X CKE# L L L L L L L L L L H CK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ Address Accessed N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address WED2ZLRSP01S Operation Deselect Continue Deselect Begin Burst Read Cycle Continue Burst Read Cycle NOP/Dummy Read Dummy Read Begin Burst Write Cycle Continue Burst Write Cycle NOP/Write Abort Write Abort Ignore Clock NOTES: 1. X means “Don’t Care.” 2. The rising edge of clock is symbolized by ( ↑ ) 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WRITE# = L means Write operation in WRITE TRUTH TABLE. WRITE# = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins (ZZ and OE#). 6. CEx# refers to the combination of CE1#, CE2 and CE2#. 7. Applies to each of the independent arrays. WRITE TRUTH TABLE WE# H L L L L L L BWa# BWb# BWc# BWd# X X X X L H H H H L H H H H L H H H H L L L L L H H H H Operation Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write Abort/NOP NOTES: 1. X means “Don’t Care.” 2. All inputs in this table must meet setup and hold time around the rising edge of CK ( ↑ ). 3. Applies to each of the independent arrays. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS* Voltage on Vdd Supply Relative to VSS VIN (DQx) VIN (Inputs) Storage Temperature (BGA) Short Circuit Output Current WED2ZLRSP01S -0.3V to +3.6V -0.3V to +3.6V -0.3V to +3.6V -55°C to +125°C 100mA *Stress greater than those listed under “Absolute Maximum Ratings”: may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS (0°C ≤ TA ≤ 70°C) Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Symbol VIH VIL ILI ILO VOH VOL VCC Conditions Min 1.7 -0.3 -5 -5 2.0 --2.375 Max VCC +0.3 0.7 5 5 --0.4 2.625 Units V V µA µA V V V Notes 1 1 2 1 1 1 0V ≤ VIN ≤ VCC Output(s) Disabled, 0V ≤ VIN ≤ VCC IOH = -1.0mA IOL = 1.0mA NOTES: 1. All voltages referenced to VSS (GND) 2. ZZ pin has an internal pull-up, and input leakage is higher. DC CHARACTERISTICS Description Power Supply Current: Operating Power Supply Current: Standby Power Supply Current: Current Clock Running Standby Current Symbol IDD ISB2 Conditions Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle Time = tCYC MIN; VCC = MAX; Output Open Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2 or VCC - 0.2; All Inputs Static; CK Frequency = 0; ZZ ≤ VIL Device Selected; All Inputs ≤ VIL or ≥ VIH; Cycle Time =tCYC MIN; VCC = MAX; Output Open; ZZ ≥ VCC - 0.2V Device Deselected; VCC = MAX; All Inputs ≤ VSS + 0.2 or VCC - 0.2; Cycle Time = tCYC MIN; ZZ ≤ VIL Typ 166 MHz 650 30 60 150 MHz 600 60 133 MHz 560 60 100 MHz 500 60 Units mA mA Notes 1, 2 2 ISB3 20 40 40 40 40 mA 2 ISB4 140 120 100 80 mA 2 NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time. BGA CAPACITANCE Description Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance Symbol CI CO CA CCK Conditions TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ TA = 25°C; f = 1MHZ Typ 5 6 5 3 Max 7 8 7 5 Units pF pF pF pF Notes 1 1 1 1 NOTES: 1. This parameter is sampled. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC CHARACTERISTICS Parameter Clock Time Clock Access Time Output enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width Clock Low Pulse Width Address Setup to Clock High CKE# Setup to Clock High Data Setup to Clock High Write Setup to Clock High Address Advance to Clock High Chip Select Setup to Clock High Address Hold to Clock high CKE# Hold to Clock High Data Hold to Clock High Write Hold to Clock High Address Advance to Clock High Chip Select Hold to Clock High Symbol tCYC tCD tOE tLZC tOH tLZOE tHZOE tHZC tCH tCL tAS tCES tDS tWS tADVS tCSS tAH tCEH tDH tWH tADVH tCSH 166MHz Min 6.0 — — 1.5 1.5 0.0 — — 2.2 2.2 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 — — — — — — 3.5 3.5 — — — 3.0 3.0 — — — — — — Max 150MHz Min 6.7 — — 1.5 1.5 0.0 — — 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 — — — — — — 3.8 3.8 — — — 3.0 3.0 — — — — — — Max 133MHz Min 7.5 — — 1.5 1.5 0.0 — — 3.0 3.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 — — — — — — 4.2 4.2 — — — 3.5 3.5 — — — — — — Max WED2ZLRSP01S 100MHz Min 10.0 — — 1.5 1.5 0.0 — — 3.0 3.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 — — — — — — 5.0 5.0 — — — 3.5 3.5 — — — — — — Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. All Address inputs must meet the specified setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled. 3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low. Both cases must meet setup and hold times. 4. Applies to each of the independent arrays. AC TEST CONDITIONS (0 ≤ TA ≤ 70°C, VCC = 2.5V ± 5%, Unless Otherwise Specified) Parameter Input Pulse Level Input Rise and Fall Time (Measured at 20% to 80%) Input and Output Timing Reference Levels Output Load Value 0 to 2.5V 1.0V/ns 1.25V See Output Load (A) OUTPUT LOAD (A) Dout Zo=50Ω RL=50Ω 30pF* VL=1.25V OUTPUT LOAD (B) (for tLZC, tLZOE, tHZOE, and tHZC) +2.5V Dout 1538Ω 1667 Ω 5pF* *Including Scope and Jig Capacitance White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time Z is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. WED2ZLRSP01S When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current Conditions ZZ ≥ VIH Symbol ISB2Z tZZ tRZZ tZZI tRZZI Min Max 10 2(tKC) 2(tKC) Units mA ns ns ns ns Notes 1 1 1 1 2(tKC) FIG. 2 SNOOZE MODE TIMING DIAGRAM CLOCK t ZZ ZZ t RZZ t ZZI ISUPPLY t RZZI I ISB2Z ALL INPUTS (except ZZ) DESELECT or READ Only Output (Q) HIGH-Z DON'T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 3 TIMING WAVEFORM OF READ CYCLE tCH tCL Clock WED2ZLRSP01S tCYC tCES CKE# tCEH tAS Address A1 tAH A2 A3 tWS WRITE# tWH tCSS CEx# tCSH tADVS ADV tADVH OE# tOE tLZOE Data Out Q1-1 tHZOE tCD tOH Q2-1 Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 tHZC Q3-4 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Dont Care Undefined Note: Applies to both independent arrays. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 4 TIMING WAVEFORM OF WRITE CYCLE tCH tCL Clock WED2ZLRSP01S tCSS tCSH CKE# tCYC Address A1 A2 A3 WRITE# CEx# ADV OE# tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 D3-2 tDH D3-3 D3-4 tHZOE Data Out Q0-3 Q0-4 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Dont Care Undefined Note: Applies to both independent arrays. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 5 TIMING WAVEFORM OF SINGLE READ/WRITE WED2ZLRSP01S tCH tCL Clock tCES tCEH CKE# tCYC Address A1 A2 A3 A4 A5 A6 A7 A8 A9 WRITE# CEx# ADV OE# tOE tLZOE Data In Q1 Q2 Q4 Q6 Q7 tDS Data Out D2 tDH D5 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Dont Care Undefined Note: Applies to both independent arrays. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 6 TIMING WAVEFORM OF CKE# OPERATION WED2ZLRSP01S tCH tCL Clock tCES tCEH CKE# tCYC Address A1 A2 A3 A4 A5 A6 WRITE# CEx# ADV OE# tCD tLZC Data Out Q1 tHZC Q3 Q4 tDS Data In D2 tDH NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Dont Care Undefined Note: Applies to both independent arrays. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 7 TIMING WAVEFORM OF CE# OPERATION WED2ZLRSP01S tCH tCL Clock tCSS tCSH CKE# tCYC Address A1 A2 A3 A4 A5 WRITE# CEx# ADV OE# tOE tLZOE Data Out Q1 tHZC Q2 tCD tLZC Q4 tDS tDH Data In D3 D5 NOTES: WRITE# = L means WE# = L, and BWx# = L CEx# refers to the combination of CE1#, CE2 and CE2#. Dont Care Undefined Note: Applies to both independent arrays. White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE DIMENSION: 153 BUMP PBGA 17.00 2.33 Max WED2ZLRSP01S 23.00 0.50 ± 10 10.00 3.50 18.00 1.00 2.5 .60 ± .050 ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTE: Ball attach pad for above BGA package is 620 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION Commercial Temp Range (0°C to 70°C) Part Number WED2ZLRSP01S35BC WED2ZLRSP01S38BC WED2ZLRSP01S42BC WED2ZLRSP01S50BC WED2ZLRSP01S38BI WED2ZLRSP01S42BI WED2ZLRSP01S50BI Configuration 512K x 32/256K x 32 512K x 32/256K x 32 512K x 32/256K x 32 512K x 32/256K x 32 512K x 32/256K x 32 512K x 32/256K x 32 512K x 32/256K x 32 tCD (ns) 3.5 3.8 4.2 5.0 3.8 4.2 5.0 Clock (MHz) 166 150 133 100 150 133 100 Operating Range Commercial Commercial Commercial Commercial Industrial Industrial Industrial Temperature Range 0° - 70° C 0° - 70°C 0° - 70°C 0° - 70°C -40° - 85°C -40° - 85°C -40° - 85°C White Electronic Designs Corp. reserves the right to change products or specifications without notice. April, 2002 Rev. 0 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com