WED3C7410E16M400BHM

White Electronic Designs WED3C7410E16M-XBHX PRELIMINARY* 7410E RISC Microprocessor HiTCE™ Multichip Package OVERVIEW The WEDC 7410E/SSRAM multichip package is targeted for high performance, space sensitive, low power systems and supports the following power management features: doze, nap, sleep and dynamic power management. The WED3C7410E16M-XBHX multichip package consists of: 7410E AltiVec™ RISC processor Dedicated 2MB SSRAM L2 cache, configured as 256Kx72 21mmx25mm, 255 HiTCE™ Ball Grid Array (CBGA) Core frequency = 450 or 400MHz @ 1.8V Maximum L2 Cache frequency = 200MHz Maximum 60x Bus frequency = 100MHz * This product is under development, is not qualified or characterized and is subject to change without notice. The WED3C7410E16M-XBHX is offered in Commercial (0°C to +70°C), industrial (-40°C to +85°C) and military (-55°C to +125°C) temperature ranges and is well suited for embedded applications such as missiles, aerospace, flight computers, fire control systems and rugged critical systems. FEATURES Footprint compatible with WED3C7410E16M-XBX, WED3C7558M-XBX and WED3C750A8M-200BX Implementation of Altivec™ technology instruction set Optional, high-bandwidth MPX bus interface HiTCE™ interposer for TCE compatibility to laminate substrates for increased Board level reliability Available with eutectic or high lead solder balls FIGURE 1 – MULTI-CHIP PACKAGE DIAGRAM AltiVec™ is a trademark of Motorola Inc. HiTCE™ is a trademark of Kyocera Corp. July 2004 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com July 2004 Rev. 0 Instruction MMU SRs (Shadow) 128-Entry DTLB Tags Data MMU EA Fetcher BTIC (64 Entry) LR SRs (Original) 128-Entry DTLB DBAT Array Tags CTR BHT (512 Entry) IBAT Array 32-Kbyte I Cache Branch Processing Unit 128-Bit (4 Instructions) Additional Features Time Base Counter/Decrementer Clock Muliplier JTAG/COP Interface Thermal/Power Management Performance Monitor Instruction Queue (6 Word) Dispatch Unit PA 32-Kbyte I Cache Reservation Station Reservation Station Reservation Station GPR File 6 Rename Buffers + Load/Store Unit Interger Unit 1 System Register Unit Interger Unit 2 VR File 6 Rename Buffers Reservation Station Reservation Station Reservation Station (2 Entry) FPR File 6 Rename Buffers Reservation Station Floating-Point Unit Vector ALU White Electronic Designs FIGURE 2 – BLOCK DIAGRAM 2 32-Bit Vector Permute Unit VSIU VCIU VFPU . . +x 32-Bit 128-Bit 32-Bit Vector Touch Queue . . . . + (EA Calculation) Load Fold Finished Queue Stores . . 64-Bit 64-Bit +x L1 Complete Stores Operations . . FPSCR VSCR 128-Bit Completion Unit L2 Data Transaction Queue L2 Tags L2CR L2PMCR L2 Miss L2 Controller Bus Interface Unit Data Transaction Queue Memory Subsystem Data Reload Data Reload Table Buffer Completion Queue (8 Entry) L2 Castout Ability to complete up to two instructions per clock Instruction Reload Buffer 19-Bit L2 Address Bus 64- 32-Bit L2 Data Bus 32-Bit Address Bus 64-Bit Data Bus Instruction Reload Table WED3C7410E16M-XBHX PRELIMINARY White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com SSRAM SSRAM White Electronic Designs WED3C7410E16M-XBHX PRELIMINARY FIGURE 3 – BLOCK DIAGRAM, L2 INTERCONNECT SSRAM 1 L2pin_DATA L2pin_DATA L2pin_DATA L2pin_DATA L2Vdd DQa DQb DQc DQd DP0-3 K SGW# SE1# U1 FT# SBd# SBc# SBb# SBa# SW# ADSP# ADV# SE2 L2DP0-3 L2 CLK_OUT A L2WE# L2CE# ADSC# SE3# SA0-17 ZZ LBO# G# mP 7410E A0-17 SSRAM 2 SA0-17 U2 FT# SBd# SBc# SBb# SBa# SW# ADSP# ADV# SE2 L2Vdd L2CLK_OUT B L2pin_DATA L2pin_DATA L2pin_DATA L2pin_DATA L2DP4-7 SGW# SE1# K DQa DQb ADSC# DQc DQd DP0-3 ZZ L2ZZ SE3# LBO# G# July 2004 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3C7410E16M-XBHX PRELIMINARY FIGURE 5 – PIN ASSIGNMENTS Ball assignments of the 255 CBGA package as viewed from the top surface. Side profile of the CBGA package to indicate the direction of the top surface view. July 2004 Rev. 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3C7410E16M-XBHX PRELIMINARY PACKAGE PINOUT LISTING SIGNAL NAME A[0-31] AACK# ABB#/AMONO# (8) AP[0-3] ARTRY# AVCC BG# BR# BVSEL (4, 6) CHK# (5, 6, 13) CI# CKSTP_IN# CKSTP_OUT# CLK_OUT DBB#/DMONO (8) DBG# DBWO#/DTI[0] DH[0-31] DL[0-31] DP[0-7] DRDY# (5, 9, 12) DTI 1-2 (9, 11) EMODE# (10, 11) GBL# GND HIT# (5) (12) HRESET# INT# L1_TSTCLK (1) L2_TSTCLK (1) L2AVCC L2VCC (5) (7) L2OVCC L2VSEL (3, 6) LSSD_MODE# (1) MCP# NC (No-connect) OVCC (2) PLL_CFG[0-3] QACK# QREQ# RSRV# SHD0-1# (5) (14) SMI# SRESET# PIN NUMBER C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1 L2 K4 C1, B4, B3, B2 J4 A10 L1 B6 B1 C6 E1 D8 A6 D7 J14 N1 G4 P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4 M2, L3, N2, L4, R1, P2, M4, R2 D5 G16, H15 C4 F1 C5, C12, E3, E6, E8, E9, E11, E14, F3, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12 A3 A7 B15 D11 D12 L11 A2, B8, C3, D6, J16 E10, E12, M12, G12, G14, K12, K14 B5 B10 C13 B7, C8 C7, E5, G3, G5, K3, K5, P7, P10, E7, M5, M7, M10 A8, B9, A9, D9 D3 J3 D1 A4, A5 A16 B14 ACTIVE High Low Low High Low — Low Low High Low Low Low Low High Low Low Low High High High Low High Low Low — Low Low Low High High — — — High Low Low — — High Low Low Low Low Low Low I/O I/O Input Output I/O I/O Input Input Output Input Input I/O Input Ouput Output Output Input Input I/O I/O I/O Output Input Input I/O — Output Input Input Input Input Input Input Input Input Input Input — Input Input Input Output Output I/O Input Input 1.8V 2.5V 3.3V *— 1.8V 3.3V 1.8V 3.3V 2.5V HRESET# 3.3V 1.8V 3.3V N/A N/A GND GND GND GND HRESET# OVCC 1.8V 1.8V 1.8V 1.8V (7) 2.5V (7) 3.3V (7) July 2004 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3C7410E16M-XBHX PRELIMINARY PACKAGE PINOUT LISTING (continued) SIGNAL NAME SYSCLK TA# TBEN TBST# TCK TDI (6) TDO TEA# TMS (6) TRST# (6) TS# TSIZ[0-2] TT[0-4] VCC (2) WT# PIN NUMBER C9 H14 C2 A14 C11 A11 A12 H13 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 F6, F8, F9, F11, G7, G10, H4, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9 D2 ACTIVE — Low High Low High High High Low High Low Low High High — Low I/O Input Input Input Output Input Input Output Input Input Input I/O Output I/O Input I/O 1.8V 1.8V 1.8V 1.8V (7) 2.5V (7) 3.3V (7) NOTES: 1. These are test signals for factory use only and must be pulled up to OVCC for normal machine operation. 2. OVCC inputs supply power to the I/O drivers and VCC inputs supply power to the processor core. 3. To allow future L2 cache I/O interface voltage changes. 4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL to HRESET# (Selects 2.5V Interface) or to GND (Selects 1.8V Interface) or to OVCC (Selects 3.3V Interface). 5. Uses one of 9 existing no-connects in WEDC’s WED3C755A8M-300BX. 6. Internal pull up on die. 7. OVCC supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVCC supplies power to the L2 cache I/O interface (L2ADDR (0-18], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT) and the L2 control signals; L2AVCC supplies power to the SSRAM core memory; and VCC supplies power to the processor core and the PLL and DLL (after filtering to become AVCC and L2AVCC respectively). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL pin configuration and the voltage supplied. For actual recommended value of Vin or supply voltages see Recommended Operating Conditions. 8. 9. 10. 11. Output only for 7410, was I/O for 750/755. Enhanced mode only. Deasserted (pulled high) at HRESET# for 60x bus mode. Reuses 750/755 DRTRY#, DBIS#, and TLBISYNC pins (DTI1, DTI2, and EMODE# respectively). 12. Unused output in 60x bus mode. 13. Connect to HRESET# to trigger post power-on-reset (por) internal memory test. 14. Ignored in 60x bus mode. July 2004 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3C7410E16M-XBHX PRELIMINARY ABSOLUTE MAXIMUM RATINGS Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage 60x bus supply voltage L2 bus supply voltage L2 supply voltage Input supply Symbol VCC AVCC L2AVCC OVCC L2OVCC L2VCC VIN VIN VIN TSTG Value -0.3 to 2.1 -0.3 to 2.1 -0.3 to 2.1 -0.3 to 3.465 -0.3 to 2.6 -0.3 to 4.6 -0.3 to 0VCC +0.2 -0.3 to L20VCC +0.2 -0.3 to OVCC +0.2 -55 to 150 Unit V V V V V V V V V °C Notes (4) (4) (4) (3) (3) (5) (2) (2) (2) Processor Bus L2 bus JTAG Signals Storage temperature range NOTES: 1. Functional and tested operating conditions are given in Operating Conditions table. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Vin must not exceed OVCC by more than 0.2V at any time including during power-on reset. 3. Caution: OVCC/L2OVCC must not exceed VCC/AVCC/L2AVCC by more than 2.0 V at any time including during power-on reset. 4. Caution: VCC/AVCC/L2AVCC must not exceed L2OVCC/OVCC by more than 0.4 V at any time including during power-on reset. 5. L2OVCC should never exceed L2VCC RECOMMENDED OPERATING CONDITIONS CHARACTERISTIC Core supply voltage PLL supply voltage L2 DLL supply voltage Memory core supply voltage BVSEL = 0 Processor bus supply voltage BVSEL = HRESET# BVSEL = HRESET or BVSEL = 1 L2 bus supply voltage Input Voltage L2VSEL = HRESET# or 1 Processor bus and JTAG Signals SYMBOL VCC AVCC L2AVCC L2VCC OVCC OVCC OVCC L20VCC Vin RECOMMENDED VALUE 1.8v ± 100mV 1.8v ± 100mV 1.8v ± 100mV 3.3v ± 165mV 1.8± 100mV 2.5v ± 100mV 3.3v ± 165 mV 2.5v ± 100 mV GND to OVCC UNIT V V V V V V V V V NOTE: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed July 2004 Rev. 0 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs POWER CONSUMPTION WED3C7410E16M-XBHX PRELIMINARY VCC = AVCC = 1.8 ±0.1V VDC, L2VCC = 3.3V ±5% VDC, GND = 0 VDC, 0 ≤ TJ < 105°C Processor (CPU) Frequency/L2 Frequency 400MHz/200MHz Full-on Mode Typical Maximum Doze Mode Nap Mode Sleep Mode Sleep Mode–PLL and DLL Disabled Maximum Maximum Maximum Maximum 5.7 13.1 5.3 2.25 2.20 2.0 450MHz/200MHz 6.2 14.3 5.8 2.4 2.35 2.0 Unit W W W W W W Notes 1, 3 1, 2 1, 2 1, 2 1, 2 1, 2 NOTES: 1. These values apply for all valid system bus and L2 bus ratios. The values do not include OVCC; AVCC and L2AVCC suppling power. OVCC power is system dependent, but is typically