WED3C755E8M300BI

White Electronic Designs WED3C755E8M-XBX RISC MICROPROCESSOR MULTI-CHIP PACKAGE OVERVIEW The WEDC 755E/SSRAM multichip package is targeted for high performance, space sensitive, low power systems and supports the following power management features: doze, nap, sleep and dynamic power management. The WED3C755E8M-XBX multichip package consists of: 755 RISC processor (E die revision) Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) Core Frequency/L2 Cache Frequency (300MHz/ 150MHz, 350MHz/175MHz) Maximum 60x Bus frequency = 66MHz FEATURES The WED3C755E8M-XBX is offered in Commercial (0°C to +70°C), industrial (-40°C to +85°C) and military (-55°C to +125°C) temperature ranges and is well suited for embedded applications such as missiles, aerospace, flight computers, fire control systems and rugged critical systems. Footprint compatible with WED3C7558M-XBX and WED3C750A8M-200BX Footprint compatible with Motorola MPC 745 This product is subject to change without notice. FIG. 1 - MULTI-CHIP PACKAGE DIAGRAM SSRAM µP 755E SSRAM White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 2 - BLOCK DIAGRAM WED3C755E8M-XBX Completion Instruction Fetch Branch Unit Control Unit 32K ICache System Unit Dispatch BHT/BTIC GPRs FXU1 FXU2 Rename Buffers FPRs LSU Rename Buffers FPU 32K DCache L2Tags L2 Cache BIU 60x BIU L2 Cache Bus 60x Bus SSRAM SSRAM White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3C755E8M-XBX FIG. 3 - BLOCK DIAGRAM, L2 INTERCONNECT SSRAM 1 L2pin_DATA L2pin_DATA L2pin_DATA L2pin_DATA L2DP0-3 L2 CLK_OUT A L2WE# L2CE# L20Vdd U1 FT# SBd# SBc# SBb# SBa# SW# ADSP# ADV# SE2 DQa DQb DQc DQd DP0-3 K SGW# SE1# ADSC# SE3# SA0-16 ZZ A0-16 mP 755 E SSRAM 2 U2 SA0-16 FT# SBd# SBc# SBb# SBa# SW# ADSP# ADV# SE2 L2pin_DATA L2pin_DATA L2pin_ DATA L2DP4-7 DQb ADSC# DQc DQd DP0-3 ZZ L2ZZ SE3# LBO# G# LBO# G# L20Vdd L2CLK_OUT B L2pin_DATA SGW# SE1# K DQa FIG. 4. - BLOCK DIAGRAM, L2 INTERCONNECT TDI 755 E TDO STDI L2 Cache SSRAM U2 L2 Cache SSRAM U1 STDO TMS TCK TRST STMS STCK White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FIG. 5 - PIN ASSIGNMENTS WED3C755E8M-XBX Ball assignments of the 255 CBGA package as viewed from the top surface. 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Side profile of the CBGA package to indicate the direction of the top surface view. View Substrate Assembly Underfill Encapsulant Die White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PACKAGE PINOUT LISTING Signal Name A[0-31] AACK# ABB# AP[0-3] ARTRY# AVCC BG# BR# BVSEL (4, 5, 6) CI# CKSTP_IN# CKSTP_OUT# CLK_OUT DBB# DBG# DBDIS# DBWO# DH[0-31] DL[0-31] DP[0-7] DRTRY# GBL# GND WED3C755E8M-XBX HRESET# INT# L1_TSTCLK (1) L2_TSTCLK (1) L2AVCC (8) L2OVCC L2VSEL (4, 5, 6, 7) LSSD_MODE# (1) MCP# NC (No-connect) OVCC (2) PLL_CFG[0-3] QACK# QREQ# RSRV# SMI# SRESET# STCK (9) STDI STDO Pin Number C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1 L2 K4 C1, B4, B3, B2 J4 A10 L1 B6 B1 E1 D8 A6 D7 J14 N1 H15 G4 P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4 M2, L3, N2, L4, R1, P2, M4, R2 G16 F1 C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12 A7 B15 D11 D12 L11 E10, E12, M12, G12, G14, K12, K14 B5 B10 C13 C3, C6, D5, D6, H4, A4, A5, A2, A3 C7, E5, G3, G5, K3, K5, P7, P10, E7, M5, M7, M10 A8, B9, A9, D9 D3 J3 D1 A16 B14 B7 C8 J16 Active High Low Low High Low — Low Low High Low Low Low — Low Low Low Low High High High Low Low — I/O I/O Input I/O I/O I/O — Input Output Input Output Input Ouput Output I/O Input Input Input I/O I/O I/O Input I/O — I/F Voltage OVCC OVCC OVCC OVCC OVCC 2.0V OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC GND Low Low High High — — High Low Low — — High Low Low Low Low Low — — — Input Input Input Input — — Input Input Input — — Input Input Output Output Input Input Input Input Output OVCC OVCC — — 2.0V L20VCC L20VCC — OVCC — OVCC OVCC OVCC OVCC OVCC OVCC OVCC L20VCC L20VCC L20VCC White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3C755E8M-XBX PACKAGE PINOUT LISTING (continued) Signal Name STMS (10) SYSCLK TA# TBEN TBST# TCK TDI (6) TDO TEA# TLBISYNC# TMS (6) TRST# (6) TS# TSIZ[0-2] TT[0-4] WT VCC (2) Pin Number B8 C9 H14 C2 A14 C11 A11 A12 H13 C4 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D2 F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9 8. Active — — Low High Low High High High Low Low High Low Low High High Low — I/O Input Input Input Input I/O Input Input Output Input Input Input Input I/O Output I/O Output — I/F Voltage (7) L2OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC OVCC 2.0V VOLDET (3) F3 NOTES: 1. These are test signals for factory use only and must be pulled up to OVCC for normal machine operation. 2. OVCC inputs supply power to the I/O drivers and VCC inputs supply power to the processor core. 3. Internally tied to GND in the BGA package to indicate to the power supply that a low-voltage processor is present. This signal is not a power supply pin. 4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVCC or to GND . 5. Uses one of 15 existing no-connects in WEDC’s WED3C750A8M-200BX. 6. Internal pull up on die. 7. OVCC supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVCC supplies power to the L2 cache I/O interface (L2ADDR (0-16], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT) and the L2 control signals and the SSRAM power supplies; and VCC supplies power to the processor core and the PLL and DLL (after filtering to become AVCC and L2AVCC respectively). This column serves as a reference for the nominal voltage supported on a given signal as selected by the BVSEL/ L2VSEL pin configurations and the voltage supplied. For actual recommended value of VIN or supply voltages see Recommended Operating Conditions Table. 9. 10. — Output — Uses one of 20 existing VCC pins in WEDC's WED3C750A8M-200BX, no board level design changes are necessary. For new designs of WED3C755E8M-XBX refer to PLL power supply filtering. To disable SSRAM TAP controllers without interfering with the normal operation of the devices, STCK should be tied low (GND) to prevent clocking the devices. STDI and STMS are internally pulled up and may be left unconnected. Upon power-up the SSRAM devices will come up in a reset state which will not interfere with the operation of the device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage 60x bus supply voltage L2 bus supply voltage Input supply Processor Bus L2 bus JTAG Signals Storage temperature range NOTES: 1. Functional and tested operating conditions are given in Operating Conditions table. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VIN must not exceed OVCC by more than 0.3V at any time including during power-on reset. Symbol VCC AVCC L2AVCC OVCC L2OVCC VIN VIN VIN Tstg 3. 4. Value -0.3 to 2.5 -0.3 to 2.5 -0.3 to 2.5 -0.3 to 3.6 -0.3 to 3.6 WED3C755E8M-XBX Unit V V V V V V V V °C Notes (4) (4) (4) (3) (3) (2) (2) (2) -0.3 to 0VCC +0.3 -0.3 to L20VCC +0.3 -0.3 to 3.6 -55 to 150 Caution: OVCC/L2OVCC must not exceed VCC/AVCC/L2AVCC by more than 1.6 V at any time including during power-on reset. Caution: VCC/AVCC/L2AVCC must not exceed L2OVCC/OVCC by more than 0.4 V at any time including during power-on reset. RECOMMENDED OPERATING CONDITIONS (1) Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage Processor bus supply BVSEL = 1 voltage (2) L2 bus supply voltage (3) Input Voltage L2VSEL = 1 Processor bus JTAG Signals Symbol VCC AVCC L2AVCC OVCC L20VCC VIN VIN Recommended Value 2.0 ± 100mV 2.0 ± 100mV 2.0 ± 100mV 2.5± 125mV 3.3 ± 165mV 3.3 ± 165mV GND to OVCC GND to OVCC Unit V V V V V V V V NOTE: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed 2. BVSEL = 0 is not available 3. L2VSEL = 0 is not available White Electronic Designs Corp. reserves the right to change products or specifications without notice. May, 2003 Rev 2 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs POWER CONSUMTION WED3C755E8M-XBX VCC=AVCC=2.0±0.1V, OVCC=3.3V ±5% VDC, GND=0 VDC, 0≤Tj