WED3DG6466V75D1

White Electronic Designs 512MB – 64Mx64 SDRAM UNBUFFERED FEATURES PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V ± 0.3V Power Supply 144 Pin SO-DIMM JEDEC • Package height option: JD1: 31.75 mm (1.25”) WED3DG6466V-D1 -JD1 DESCRIPTION The WED3DG6466V is a 64Mx64 synchronous DRAM module which consists of eight 64Mx8 SDRAM components in TSOP II package, and one 2K EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 144 pin SO-DIMM multilayer FR4 Substrate. * This product is subject to change without notice. PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) PINOUT PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 FRONT VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 PIN 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 FRONT DQ13 DQ14 DQ15 VSS NC NC CKL0 VCC RAS# WE# CS0# NC NC VSS NC NC VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 PIN 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 BACK DQ45 DQ46 DQ47 VSS NC NC CKE0 VCC CAS# NC A12 NC CK1 VSS NC NC VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 PIN 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 BACK DQ22 DQ23 VCC A6 A8 VSS A9 A10 VCC DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC PIN 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 BACK DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 VCC DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC PIN NAMES A0 – A12 BA0-1 DQ0-63 CK0, CK1 CKE0 CS0 RAS# CAS# WE# DQMB0-7 VCC VSS SDA SCL DNU NC Address Input (Multiplexed) Select Bank Data Input/Output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Serial Data I/O Serial Clock Do Not Use No Connect July 2005 Rev. 3 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM WE# S0# DQMB0 DQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WE DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WED3DG6466V-D1 -JD1 WE D0 D4 DQMB1 DQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WE DQMB5 DQM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WE D1 D5 DQMB2 DQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WE DQMB6 DQM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WE D2 D6 DQMB3 DQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WE DQMB7 DQM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S WE D3 D7 NOTE: DQ writing may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown. *CLOCK WIRING CLOCK INPUT *CK0 *CK1 SDRAMS 4 - SDRAMS 4 - SDRAMS RAS# CAS# CKE0 RAS#: SDRAM D0-D7 CAS#: SDRAM D0-D7 CKE: SDRAM D0-D7 *Wire per Clock Loading Table/Wiring Diagrams BA0-BA1 A0-A12 BA0-BA1: SDRAM D0-D7 A0-A12: SDRAM D0-D7 SERIAL PD SCL VDD D0-D7 A0 A1 A2 SDA VSS D0-D7 July 2005 Rev. 3 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS WED3DG6466V-D1 -JD1 Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 9 50 Units V V °C W mA Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ +70°C Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 — -10 Typ 3.3 3.0 — — — — Max 3.6 VCCQ + 0.3 0.8 — 0.4 10 Unit V V V V V µA 1 2 IOH = -2mA IOL= -2mA 3 Note Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE TA = 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V ± 200mV Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CK0) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data Input/Output Capacitance (DQ0-DQ63) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 35 35 35 16 35 7 35 10 Unit pF pF pF pF pF pF pF pF July 2005 Rev. 3 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs OPERATING CURRENT CHARACTERISTICS VCC = 3.3V, TA = 0°C to +70°C WED3DG6466V-D1 -JD1 Version Parameter Operating Current (One bank active) Precharge Standby Current in Power Down Mode Active Standby Current in Non-Power Down Mode Symbol ICC1 Conditions Burst Length = 1 tRC ≤ tRC(min) IOL = 0mA CKE ≤ VIL(max), tCC = 10ns CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns Input signals are changed one time during 20ns Io = mA Page burst 4 Banks activated tCCD = 2CK tRC ≥ tRC(min) CKE ≤ 0.2V 100/133 1080 Units mA Note 1 ICC2P ICC3N ICC4 16 360 mA mA Operating Current (Burst mode) 1,200 mA 1 Refresh Current Self Refresh Current Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. ICC5 ICC6 2,280 24 mA mA 2 July 2005 Rev. 3 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC TIMING PARAMETERS Speed Grade 100MHz Symbol tCK tCH tCL tIS tIH tAC Parameter Clock Period Clock High Time Rated @1.5V Clock Low Time Input Setup Times Min 10 3 3 2 2 1 1 Max WED3DG6466V-D1 -JD1 Speed Grade 133MHz Min 7.5 2.5 2.5 1.5 1.5 0.8 0.8 Max Units ns ns ns ns ns ns ns ns Notes tOH tOHZ tCCD tCBD tCKE tRP tRAS tRCD tRRD tRC tDQD tDWD tMRD tROH tDQZ tDQM tDPL tDAL tSB tSRX tPDE tCKSTP tREF tRFC 1. 2. 3. 4. 5. 6. Address/ Command & CKE Data Input Hold Times Address/Command & CKE Data Output Valid From Clock CAS# Latency = 2 or 3, LVTTL levels, Rated @ 50 pF all outputs switching Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf) Output Valid to Z CAS to CAS Delay CAS Bank Delay CKE to Clock Disable RAS Precharge Time RAS Active Time Activate to Command Delay (RAS to CAS Delay) RAS to RAS Bank Activate Delay RAS Cycle Time DQM to Input Data Delay Write Cmd. to Input Data Delay Mode Register set to Active delay Precharge to O/P in High Z DQM to Data in High Z for read DQM to Data mask for write Data-in to PRE Command Period Data-in to ACT (PRE) Command period (Auto precharge) Power Down Mode Entry Self Refresh Exit Time Power Down Exit Set up Time Clock Stop During Self Refresh or Power Down Refresh Period Row Refresh Cycle Time 6.0 (tco = 5.2) 3 3 1 1 1 20 50 20 20 70 0 0 3 2 0 20 5 1 10 1 200 64 80.0 75.0 10 1 200 2.7 2.7 1 1 1 20 45 20 15 67.5 0 0 3 2 0 15 5 5.4 (tco = 4.6) 1 9 7 CL CL 1 64 ns ns tCK tCK tCK ns ns ns ns ns tCK tCK tCK tCK tCK tCK ns tCK tCK ns tCK tCK ms ns 2 3 4 5 6 Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load. CL = CAS Latency Data Masked on the same clock Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC. Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle. If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high. July 2005 Rev. 3 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ORDERING INFORMATION FOR D1 Ordering Information WED3DG6466V10D1 WED3DG6466V7D1 WED3DG6466V75D1 Speed 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3 WED3DG6466V-D1 -JD1 Height* 31.75 (1.250”) 31.75 (1.250”) 31.75 (1.250”) Note: For industrial temperature range product, add an "I" to the end of the part number. ORDERING INFORMATION FOR JD1 Ordering Information WED3DG6466V10JD1 WED3DG6466V7JD1 WED3DG6466V75JD1 Speed 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3 Height* 31.75 (1.250”) 31.75 (1.250”) 31.75 (1.250”) Note: For industrial temperature range product, add an "I" to the end of the part number. PACKAGE DIMENSIONS FOR D1 AND JD1 67.72 (2.661 Max) 2.01 (0.079 Min) 3.81 (0.150) MAX. 3.99 (0.157) 31.75 (1.250) Max 19.99 (0.787) 23.14 (0.913) 28.2 (1.112) 32.79 (1.291) 4.60 (0.181) 1.50 (0.059) 9.91 (0.039) (± 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). July 2005 Rev. 3 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Document Title 512MB – 64Mx64 SDRAM UNBUFFERED WED3DG6466V-D1 -JD1 Revision History Rev # Rev 0 Rev 1 History Created Datasheet 1.1 Updated Datasheet 1.2 Added AD1 package option Release Date 6-4-03 4-04 Status Advanced Preliminary Rev 2 2.1 Removed AD1 package option 2.2 Added Timing Parameters 2.3 Added D1 package option “Not Recommended for New Designs” 2.4 Moved from Preliminary to Final 9-04 Final Rev 3 3.1 Added “ED” to part number 7-05 Final July 2005 Rev. 3 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com