WED9LAPC2B16P8BC

White Electronic Designs 4M x 32 SDRAM / 2M x 8 SDRAM WED9LAPC2B16P8BC EXTERNAL MEMORY SOLUTION FOR AGERE’S TAPC640 ATM PORT CONTROLLER FEATURES Clock speeds: • SDRAM: 100 MHz 100% tested to timing requirements of TAPC640’s memory interface Packaging: • 153 pin BGA, 14mm x 22mm 3.3V Operating supply voltage Direct control interface to both the BRAM and PRAM ports on the TAPC640 62% space savings vs. monolithic solution Reduced system inductance and capacitance DESCRIPTION The WED9LAPC2B16P8BC is a 3.3V, 4M x 32 Synchronous DRAM and a 2M x 8 Synchronous DRAM array packaged in a 14mm x 22mm 153 lead BGA. The WED9LAPC2B16P8BC provides the memory required for the BRAM (Buffer Memory) and PRAM (Pointer Memory) memory ports for Agere’s TAPC640 ATM port controller. When used in conjunction with the WED9LAPC2C16V4BC, which provides memory for the CRAM (Control Memory) and VCRAM (Virtual Control Memory) memory ports, the entire memory requirement of the LUCTAPC640 can be met using these 2 BGA devices. The WED9LAPC2B16P8BC is 100% tested to the timing requirements of the TAPC640’s memory interface timing for both Commercial and Industrial temperature ranges. FIGURE 1 – PIN CONFIGURATION Pinout BRAM and PRAM MCM — Top View 1 A B C D E F G H J K L M N P R T U 2 VCC BDATA_A BDATA_A VSS BDATA_A BDATA_A VCC BDATA_B BDATA_B VSS BDATA_B BDATA_B VCC PDATA PDATA PDATA PDATA 3 BDATA_A BDATA_A BDATA_A BDATA_A BDATA_A BDATA_A BDATA_B BDATA_B BDATA_B BDATA_B BDATA_B BDATA_B VCC PDATA VCC VCC PDATA 4 BDATA_A BDATA_A BDATA_A BDATA_A BDATA_A BDATA_A BDATA_B BDATA_B BDATA_B BDATA_B BDATA_B BDATA_B VSS VSS VSS PDATA PDATA 5 VSS VSS VCC VCC VCC VSS VSS VSS VCC VCC VCC VSS VSS VSS VSS VCC VCC 6 GCLK VSS NC VCC VCC VCC VCC VCC NC NC NC NC NC NC NC VCC PCASN 7 VSS NC NC VSS VSS VSS VSS NC NC NC NC NC NC NC NC VCC PRASN 8 BWEN VCC VSS VSS VSS VSS VCC VSS VSS VSS VCC VSS VSS VSS VSS PDQM PWEN 9 BCASN VCC BADDR9 BADDR7 BADDR5 BADDR3 VCC BADDR1 BADDR10 BADDR12 VCC PADDR8 PADDR6 PADDR4 PADDR2 PADDR0 PBS BRASN BDQM BADDR11 BADDR8 BADDR6 BADDR4 VCC BADDR2 BADDR0 BADDR13 VCC PADDR9 PADD7 PADDR5 PADDR3 PADDR1 PADDR10 White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 1 – PIN CONFIGURATION (continued) Pin Description Symbol BADDR BDATA BADDR12, BADDR13 BDQM BRAS BCAS BWE PADDR PDATA PBS PDQM PRAS PCASN PWE GCLK VCC VSS Pin Name BRAM Address BRAM Data BRAM Bank Select BRAM DQM BRAM Row Address Strobe BRAM Column Address Strobe BRAM Write Enable PRAM Address PRAM Data PRAM Bank Select PRAM DQM PRAM Row Address Strobe PRAM Column Address Strobe PRAM Write Enable Global Clock Power Supply Ground Description Address Pins For The SDRAM Memory That Serves As The Buffer Memory (BRAM) Data I/o Pins For The SDRAM Buffer Memory (BRAM) Bank Address Pin For The SDRAM Buffer Memory (BRAM) DQM (Data Mask) Pin For The SDRAM Buffer Memory (BRAM) RAS Pin For The SDRAM Buffer Memory (BRAM) CAS Pin For The SDRAM Buffer Memory (BRAM) Write Enable Pin For The SDRAM Buffer Memory (BRAM) Address Pins For The SDRAM Memory That Serves As The Pointer Memory (PRAM) Data I/o Pins For The SDRAM Pointer Memory (PRAM) Bank Address Pin For The SDRAM Pointer Memory (PRAM) DQM (Data Mask) Pin For The SDRAM Pointer Memory (PRAM) RAS Pin For The SDRAM Pointer Memory (PRAM) CAS Pin For The SDRAM Pointer Memory (PRAM) Write Enable Pin For The SDRAM Pointer Memory (PRAM) Common Clock Pin For Both The BRAM And PRAM Memory Arrays Power Supply Pins Ground Pins FIGURE 2 – BLOCK DIAGRAM 4M X 32 SDRAM / 2M X 8 SDRAM BADDR0-11 BADDR12 BADDR13 BDQM ADDR BA0 BA1 LDQM# UDQM# RAS# CAS# WE# CLK CKE CS# ADDR BA0 BA1 LDQM# UDQM# RAS# CAS# WE# CLK 1M x 16 x 4 SDRAM DQ0-7 Bdata 0-15 DQ8-15 BRASN BCASN BWEN GCLK VCC VSS 1M x 16 x 4 SDRAM DQ0-7 Bdata 16-31 DQ8-15 PADDR0-10 ADDR0-10 1M x 8 x 2 SDRAM PBS PDQM BA1 DQM# DQ0-7 Pdata 0-7 PRASN PCASN PWEN RAS# CAS# WE# CLK White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Voltage on VCC Relative to VSS VIN (DQX) Storage Temperature (BGA) Junction Temperature Short Circuit Output Current -0.5V to +4.6V -0.5V to VCC +0.5V -55°C to +125°C +125°C 50 mA WED9LAPC2B16P8BC RECOMMENDED DC OPERATING CONDITIONS 0°C ≤ TA ≤ 70°C; VCC = 3.3V ± 5% unless otherwise noted Parameter Supply Voltage (1) Input High Voltage (1,2) Input Low Voltage (1,2) Input Leakage Current 0 ≤ VIN ≤ VCC Output Leakage (Output Disabled) 0 ≤ VIN ≤ VCC Output High (IOH = -2mA) (1) Output Low (IOL = 2mA) (1) NOTES: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH ≤ +6.0V for t ≤ tKC/2 Undershoot: VIL ≥ -2.0V for t ≤ tKC/2 *Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Min Max Units 3.135 3.465 V VCC VIH 2.0 VCC +0.3 V -0.3 0.8 V VIL ILI -10 10 µA ILO VOH VOL -10 2.4 — 10 — 0.4 µA V V DC ELECTRICAL CHARACTERISTICS Description Operating Current Operating Current Operating Current Operating Current Conditions BRAM and PRAM active BRAM active/PRAM inactive BRAM inactive/PRAM active BRAM inactive/PRAM inactive Symbol ICC1 ICC2 ICC3 ICC4 Typ 170 140 90 40 Max 210 160 110 60 Units mA mA mA mA BGA CAPACITANCE Description Address Input Capacitance1 Input/Output Capacitance (DQ)1 Control Input Capacitance1 Clock Input Capacitance1 NOTE: 1. This parameter is sampled. Conditions TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz TA = 25°C; f = 1MHz Symbol CI CO CA CCK Typ 5 8 5 4 Max 8 10 8 6 Units pF pF pF pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs SDRAM AC CHARACTERISTICS Parameter Clock Cycle Time (1) Clock To Valid Output Delay (1,2) Output Data Hold Time (2) Clock High Pulse Width (3) Clock Low Pulse Width (3) Input Setup Time (3) Input Hold Time (3) Clk To Output Low-Z (2) Clk To Output High-Z Row Active To Row Active Delay (4) RAS# To CAS# Delay (4) Row Precharge Time (4) Row Active Time (4) Row Cycle Time – Operation (4) Row Cycle Time – Auto Refresh (4,8) Last Data In To New Column Address Delay (5) Last Data In To Row Precharge (5) Last Data In To Burst Stop (5) Column Address To Column Address Delay (6) Number Of Valid Output Data (7) CL = 3 CL = 2 Symbol tCC tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ tRRD tRCD tRP tRAS tRC tRFC tCDL tRDL tBDL tCCD WED9LAPC2B16P8BC Min 8 10 2.5 3 3 2 1 1 Max 1000 1000 6 6 16 20 20 48 70 70 1 2 1 1 10,000 2 1 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK EA EA NOTES: 1. Parameters depend on programmed CAS latency. 2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter. 3. Assumed input rise and fall time = 1ns. If trise of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter. 4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer. 5. Minimum delay is required to complete write. 6. Al devices allow every cycle column address changes. 7. In case of row precharge interrupt, auto precharge and read burst stop. 8. A new command may be given tRFC after self-refresh exit. CLOCK FREQUENCY AND LATENCY PARAMETERS (Unit = number of clock) Cycle Time 8.0ns 10.0ns CAS Latency 3 2 tRC 70ns 9 7 tRAS 48ns 6 5 tRP 20ns 3 2 tRRD 16ns 2 2 tRCD 20ns 3 2 tCCD 10ns 1 1 tCDL 10ns 1 1 tRDL 10ns 2 2 REFRESH CYCLE PARAMETERS Parameter Refresh Period1,2 Symbol tREF Min — Max 64 Units ms NOTES: 1. 1024 cycles 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC SDRAM COMMAND TRUTH TABLE FUNCTION BRAS or PRAS L L L L L H H H H H H X X BCAS or PCAS L L H H H L L L L H H X X BWE or PWE BDQM or PDQM X X X X X X X X X X X L H BADDR12, BADDR or BADDR13 or PADDR PBS OP CODE X X BA L X H BA Row Address BA L BA H BA L BA H X X X X X X X X NOTES Mode Register Set Auto Refresh (CBR) Precharge Single Bank Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge Burst Termination No Operation Data Write/Output Disable Data Mask/Output Disable L H L L H L L L H L H X X 2 2 2 2 2 2 3 4 4 NOTES: 1. All of the SDRAM operations are defined by states of BWE or PWE, BRAS or PRAS, BCAS or PCAS, and BDQM or PDQM at the positive rising edge of the clock. 2. Bank Select (BADDR12, BADDR13, or PBS), if BADDR12, BADDR13, or PBS = 0 then bank A is selected, if BADDR12, BADDR13, or PBS = 1 then bank B is selected. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. The BDQM or PDQM has two functions for the data DQ Read and Write operations. During a Read cycle, when BDQM or PDQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. BDQM or PDQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC SDRAM CURRENT STATE TRUTH TABLE Command Current State BRAS or BCAS or BWE or BADDR12, BADDR or PRAS PCAS PWE BADDR13 PADDR or PBS L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X L L L OP Code L L H X X L H L X X L H H BA Row Address H L L BA Column H L H BA Column H H L X X H H H X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Action Notes Idle Row Active Read Write Read with Auto Precharge Set the Mode Register Start Auto No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst 1 1 2 1 1 3 1 4,5 4,5 2 5,6 5,6 2 5,6 5,6 2 2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC SDRAM CURRENT STATE TRUTH TABLE (continued) Command Current State BRAS or PRAS L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H L L L L H H H H BCAS or PCAS L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H L L H H BWE or BADDR12, BADDR or PWE BADDR13 PADDR or PBS L OP Code H X X L X X H BA Row Address L BA Column H BA Column L X X H X X L OP Code H X X L X X H BA Row Address L BA Column H BA Column L X X H X X L OP Code H X X L X X H BA Row Address L BA Column H BA Column L X X H X X L OP Code H X X L X X H BA Row Address L BA Column H BA Column L X X H X X L OP Code H X X L X X H BA Row Address L BA Column H BA Column L X X H X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write w/o Precharge Read w/o Precharge Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto orSelf Refresh Precharge Bank Activate Write Read Burst Termination No Operation Action Notes Write with Auto Precharge Precharging Row Activating Write Recovering Write Recovering with Auto Precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row active after tRCD No Operation; Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row active after tDPL No Operation; Row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL 2 2 2 2 20 2 2 2 2 2 2 6 6 2 2 2,6 2,6 White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC SDRAM CURRENT STATE TRUTH TABLE (continued) Command Current State BRAS or PRAS L L L L H H H H L L L L H H H H BCAS or PCAS L L H H L L H H L L H H L L H H BWE or PWE L H L H L H L H L H L H L H L H BADDR12, BADDR or BADDR13 PADDR or PBS OP Code X X X X BA Row Address BA Column BA Column X X X X OP Code X X X X BA Row Address BA Column BA Column X X X X Description Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Mode Register Set Auto or Self Refresh Precharge Bank Activate Write Read Burst Termination No Operation Action Notes Refreshing Mode Register Accessing ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles Notes: 1. Both Banks must be idle otherwise it is an illegal action. 2. The Current State refers only refers to one of the banks, if VCBS selects this bank then the action is illegal. If VCBS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 3. The minimum and maximum Active time (tRAS) must be satisfied. 4. The VCRAS# to VCCAS# Delay (tRCD) must occur before the command is given. 5. Address VCADDR9/AP is used to determine if the Auto Precharge function is activated. 6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank-to-bank delay time (tRRD) is not satisfied. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 3 – SDRAM POWER UP SEQUENCE 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRP VCRAS# tRFC tRFC VCCAS# VCADDR Key RAa VCBS VCADDR9/AP RAa VCDATA HIGH-Z VCWE# VCDQM# High level is necessary Precharge (All Banks) Auto Refresh Auto Refresh Mode Register Set Row Active (A-Bank) DON’T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 4 – SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @CAS LATENCY = 3, BURST LENGTH = 1 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tCC tCH tCL tRCD tRAS tRCD tSS VCRAS# tSH tRP tSS VCCAS# tSH tCCD tSS VCADDR Ra tSH Ca tSS Cb tSH Cc Rb VCBS BS BS BS BS BS BS VCADDR9/AP Ra Rb tRAC tSAC VCDATA Qa tSS Db tSH Qc tSLZ VCWE# tOH tSS tSH tSS VCDQM# tSH Row Active Read Write Read Precharge Row Active DON’ T CARE White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 5 – SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 0 GCK Note 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRC tRCD VCRAS# VCCAS# VCADDR Ra Ca0 Rb Cb0 VCBS VCADDR9/AP Ra Rb tRAC Note 3 tSHZ tSAC Qa0 tOH Qa1 Qa2 Qa3 Note 4 tRDL Db0 Db1 Db2 Db3 CL = 2 VCDATA CL = 3 tRAC Note 3 tSAC Qa0 tOH Qa1 Qa2 tSHZ Qa3 Note 4 Db0 Db1 Db2 Db3 tRDL VCWE# VCDQM# Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) DON’T CARE Notes: 1. Minimum row cycle times are required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ) after the clock. 3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC. 4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst) White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 6 – SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRCD VCRAS# Note 2 VCCAS# VCADDR Ra Ca0 Cb0 Cc0 Cd0 VCBS VCADDR9/AP Ra tRDL CL = 2 VCDATA CL = 3 Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Qa0 Qa1 Qb2 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 tCDL Dd0 Dd1 VCWE# Note 1 Note 3 VCDQM# Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) DON’T CARE Notes: 1. To write data before burst read ends. VCDQM# should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written. 3. VCDQM# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 7 – SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VCRAS# Note 1 VCCAS# VCADDR RAa CAa RBb CBb CAc CBd CAe VCBS VCADDR9/AP RAa RBb CL = 2 VCDATA CL = 3 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 VCWE# VCDQM# Row Active (A-Bank) Row Active (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Precharge (A-Bank) DON’T CARE Note: 1. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 8 – SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VCRAS# Note 2 VCCAS# VCADDR RAa CAa RBb CBb CAc CBd VCBS VCADDR9/AP RAa RBb tCDL VCDATA DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 tRDL DBd1 VCWE# Note 1 VCDQM# Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Write (B-Bank) Write (A-Bank) Write (B-Bank) Precharge (Both Banks) DON’T CARE NOTES: 1. To interrupt burst write by Row precharge, VCDQM# should be asserted to mask invalid input data. 2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 14 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 9 – SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VCRAS# VCCAS# VCADDR RAa CAa RBb CBb RAc CAc VCBS VCADDR9/AP RAa RBb RAc tCDL CL = 2 VCDATA CL = 3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 Note 1 QAc0 QAc1 QAc2 QAc0 QAc1 VCWE# VCDQM# Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (B-Bank) Write (B-Bank) Row Active (A-Bank) Read (A-Bank) DON’T CARE Note: 1. tCDL should be met to complete write. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 15 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 10 – SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @BURST LENGTH = 4 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VCRAS# VCCAS# VCADDR Ra Rb Ca Cb VCBS VCADDR9/AP Ra Rb CL = 2 VCDATA CL = 3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 VCWE# VCDQM# Row Active (A-Bank) Read with Auto Precharge (A-Bank) Row Active (B-Bank) Auto Precharge Start Point (A-Bank) Write with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) DON’T CARE Note: 1. tCDL should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length = 1 & 2 and BRSW mode) White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 16 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 11 – SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST STOP @ BURST LENGTH = FULL PAGE 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VCRAS# VCCAS# VCADDR RAa CAa CAb VCBS VCADDR9/AP RAa Note 2 1 QAb0 QAb1 QAb2 QAb3 QAb4 1 QAb5 CL = 2 VCDATA QAa0 QAa1 QAa2 QAa3 QAa4 2 2 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 CL = 3 QAa0 QAa1 QAa2 QAa3 QAa4 VCWE# VCDQM# Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) DON’T CARE Notes: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. About the valid VCDATAs after burst stop, it is the same as the case of VCRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each of them. But at burst write, burst stop and VCRAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle.” 3. Burst stop is valid at every burst length. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 17 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 12 – SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST STOP @ BURST LENGTH = FULL PAGE 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VCRAS# VCCAS# VCADDR RAa CAa CAb VCBS VCADDR9/AP RAa tBDL VCDATA DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 tRDL Note 2 DAb5 VCWE# VCDQM# Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) DON’T CARE Notes: 1. At full page mode, burst is end at the end of burst. So auto precharge is possible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. VCDQM# at write interrupt by precharge command is needed to prevent invalid write. VCDQM# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 18 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 13 – SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2 0 GCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VCRAS# Note 2 VCCAS# VCADDR RAa CAa RBb CAb RAc CBc CAd VCBS VCADDR9/AP RAa RBb RAc CL = 2 VCDATA CL = 3 DAa0 QAb0 QAb1 DBc0 QAd0 QAd1 DAa0 QAb0 QAb1 DBc0 QAd0 QAd1 VCWE# VCDQM# Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank) Row Active (A-Bank) Write with Auto Precharge (B-Bank) Read (A-Bank) Precharge (Both Banks) DON’T CARE Notes: 1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set). At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 19 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC FIGURE 14 – SDRAM MODE REGISTER SET CYCLE 0 GCK 1 2 3 4 5 6 Note 2 VCRAS# Note 1 VCCAS# Note 3 VCADDR Key Ra VCDATA HI-Z VCWE# VCDQM# MRS New Command DON’T CARE *Both banks precharge should be completed before Mode Register Set cycle. NOTES: MODE REGISTER SET CYCLE 1. VCRAS#, VCCAS# & VCWE# activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new VCRAS# activation. 3. Please refer to Mode Register Set table. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 20 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED9LAPC2B16P8BC PACKAGE DESCRIPTION: 153 LEAD BGA 14MM X 22MM Note: Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION WED9LAPC2C16P8BC WED9LAPC2C16P8BI Commercial Temperature: Industrial Temperature: 0ºC to +70ºC -40ºC to +85ºC White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2001 Rev. 1 21 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com