White Electronic Designs
WV3EG128M72EFSR-D3
ADVANCED*
1GB – 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA
FEATURES
Double-data-rate architecture DDR266 and DDR333 • JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power Supply: • VCC = VCCQ = +2.5V ±0.2V (100, 133 and 166MHz) 184 pin DIMM package PCB height: • D3: 29.97mm (1.18")
NOTE: Consult factory for availability of: • Lead-Free Products • Vendor source control options • Industrial temperature options * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice.
DESCRIPTION
The WV3EG128M72EFSR is a 128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of eighteen 64Mx8 DDR components in FBGA packages mounted on a 184 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3
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WV3EG128M72EFSR-D3
ADVANCED
PIN CONFIGURATION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VCCQ NC NC VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 CB0 CB1 VCC PIN 47 48 49 50 51 52 53 54 55 56 57 56 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL DQS8 A0 CB2 VSS CB3 BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS NC NC VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCCQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DM1/DQS10 VCC DQ14 DQ15 CKE1 VCCQ NC DQ20 A12 VSS DQ21 A11 DM2/DQS11 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VCCQ CK0 CK0# PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 SYMBOL VSS DM8/DQS17 A10 CB6 VCCQ CB7 VSS DQ36 DQ37 VCC DM4/DQS13 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# CS1# DM5/DQS14 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53 NC VCC DM6/DQS15 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD
PIN NAMES
A0-A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0 CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# DM0-DM8 WE# VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC RESET# Address input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Data-in Mask Write Enable Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect Reset Enable
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WV3EG128M72EFSR-D3
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
RCS0#
DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS
RCS1#
DQS5 DM5/DQS14
DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS
DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS
DQS6 DM6/DQS15
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS
DQS7 DM6/DQS16
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS
DQS8 DM7/DQS17
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS
DQS4 DM4/DQS13
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O7 I/O6 I/O1 I/O0 I/O5 I/O4 I/O3 I/O2 CS# DQS DM I/O0 I/O1 I/O6 I/O7 I/O2 I/O3 I/O4 I/O5 CS# DQS 120 CK0 CK0# PLL
SERIAL PD CS0# CS1# BA0-BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE# PCK PCK# R E G I S T E R RCS0# RCS1# RBA0-RBA1 RA0-RA12 RRAS# RCAS# RCKE0 RCKE1 RWE# RESET# SCL WP BA0-BA1: SDRAMs A0-A12: SDRAMs RAS#: SDRAMs CAS#: SDRAMs CKE: SDRAMs CKE: SDRAMs WE#: DQRAMs SDA A0 A1 A2 SA0 SA1 SA2
DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM REGISTER X 2
V CCSPD VCCQ V CC VREF VSS
SPD DDR SDRAMS DDR SDRAMS DDR SDRAMS DDR SDRAMS
Note: All resistor values are 22Ω unless otherwise indicated.
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Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current
Note:
WV3EG128M72EFSR-D3
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 18 50 Units V V °C W mA
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) IL IOZ IOH IOL IOH IOL
4.
Parameter Supply Voltage (for device with nominal VCC of 2.5V) I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (systems) Input Logic High Voltage Input Logic Low Voltage Input Voltage Level, CK and CK# inputs Input Differential Voltage, CK and CK# inputs Input Crossing Point Voltage, CK and CK# inputs Input Leakage Current Output Leakage Current Output High Current (Normal strength driver); VOUT = VTT + 0.84V Output High Current (Normal strength driver); VOUT = VTT - 0.84V Output High Current (Half strength driver); VOUT = VTT + 0.45V Output High Current (Half strength driver); VOUT = VTT - 0.45V
Notes: 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
Min 2.3 2.3 VCCQ/2-50mV VREF -0.04 VREF +0.15 -0.3 -0.3 0.3 1.15 -2 -5 -16.8 16.8 -9 9
Max 2.3 2.3 VCCQ/2+50mV VREF +0.04 VCCQ +0.3 VREF -0.15 VCCQ +0.3 VCCQ +0.6 1.35 2 5
Unit V V V V V V V V V uA uA mA mA mA mA
5. 6.
These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must track variations in the dc level of the same. These charactericteristics obey the SSTL-2 class II standards.
CAPACITANCE
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT
4
TA = 25°C. f = 1MHz, VCC = 2.5V Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0, CKE1) Input Capacitance (CK0#, CK0) Input Capacitance (CS0#, CS1#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Data input/output capacitance (CB0-CB7)
March 2005 Rev. 0
Max 11 11 11 12 11 15 11 15 15
Unit pF pF pF pF pF pF pF pF pF
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White Electronic Designs
WV3EG128M72EFSR-D3
ADVANCED
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only DDR333@ CL=2.5 Max 4140 DDR266@ CL=2 Max 4140 DDR266@ CL=2.5 Max 4140
IDD SPECIFICATIONS AND TEST CONDITIONS
Parameter Operating Current
Symbol IDD0
Conditions One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-Down mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; ActivePrecharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE ≤ 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands.
Units mA
Operating Current
IDD1
4680
4680
4680
mA
Precharge PowerDown Standby Current Idle Standby Current
IDD2P IDD2F
180 1620
180 1620
180 1620
rnA mA
Active Power-Down Standby Current Active Standby Current
IDD3P IDD3N
1260 1800
1260 1800
1260 1800
mA mA
Operating Current
IDD4R
4770
4770
4770
mA
Operating Current
IDD4W
4590
4590
4590
rnA
Auto Refresh Current Self Refresh Current Operating Current
IDD5 IDD6 IDD7A
7020 180 9090
7020 180 9000
7020 180 9000
mA mA mA
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WV3EG128M72EFSR-D3
ADVANCED
Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes PLL and register power DDR333@ CL=2.5 Max 4725 DDR266@ CL=2 Max 4725 DDR266@ CL=2.5 Max 4725
IDD SPECIFICATIONS AND TEST CONDITIONS
Parameter Operating Current
Symbol IDD0
Conditions One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-Read-Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-Down mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; ActivePrecharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE ≤ 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands.
Units mA
Operating Current
IDD1
5265
5265
5265
mA
Precharge PowerDown Standby Current Idle Standby Current
IDD2P IDD2F
180 1930
180 1930
180 1930
rnA mA
Active Power-Down Standby Current Active Standby Current
IDD3P IDD3N
1260 2110
1260 2110
1260 2110
mA mA
Operating Current
IDD4R
5355
5355
5355
mA
Operating Current
IDD4W
5535
5175
5175
rnA
Auto Refresh Current Self Refresh Current Operating Current
IDD5 IDD6 IDD7A
7640 455 9675
7605 455 9585
7605 455 9585
mA mA mA
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WV3EG128M72EFSR-D3
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
1. 2. 3. Typical Case : VCC=2.5V, T=25°C Worst Case : VCC=2.7V, T=10°C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst •
IDD7A : OPERATING CURRENT : FOUR BANKS
1. 2. 3. Typical Case : VCC=2.5V, T=25°C Worst Case : VCC=2.7V, T=10°C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
4.
4.
•
•
•
•
•
Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3
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WV3EG128M72EFSR-D3
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V AC Characteristics Parameter Access window of DQs from CK, CK# CK high-level width CK low-level width Clock cycle time CL=3 CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK, CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK, CK# Data-out low-impedance window from CK, CK# Address and control input hold time (fast slew rate) Address and control input set-up time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period Symbol tAC tCH tCL tCK (3) tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHf tISf tIHs tISs tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC 42 18 60 72 -0.7 0.75 0.75 0.8 0.8 2.2 12 tHP-tQHS 0.55 70,000 45 15 60 75 0.75 0.2 0.2 tCH, tCL +0.7 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 45 20 65 75 Min -0.7 0.45 0.45 6 6 7.5 0.45 0.45 1.75 -0.6 0.35 0.35 0.4 1.25 0.75 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 +0.6 335 Max +0.7 0.55 0.55 13 12 12 Min -0.75 0.45 0.45 7.5 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 0.75 0.2 0.2 tCH, tCL +0.75 +0.75 262 Max +0.75 0.55 0.55 13 12 12 Min -0.75 0.45 0.45 7.5 7.5 10 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 +0.75 265 Max +0.75 0.55 0.55 13 12 12 Units ns tCK tCK ns ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 15 13,14 18 8,19 8,20 6 6 6 6 13,14 16 16 22 22 22 14,17 14,17 17 Notes
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WV3EG128M72EFSR-D3
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued)
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Average periodic refresh interval Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command Symbol tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR tREFI tXSNR tXSRD 75 200 Min 18 18 0.9 0.4 12 0.25 0 0.4 15 1 7.8 75 200 0.6 1.1 0.6 335 Max Min 20 20 0.9 0.4 15 0.25 0 0.4 15 1 7.8 75 200 0.6 1.1 0.6 262 Max Min 20 20 0.9 0.4 15 0.25 0 0.4 15 1 7.8 0.6 1.1 0.6 265 Max Units ns ns tCK tCK ns tCK ns tCK ns tCK μs ns tCK 12 10,11 9 19 Notes
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Notes
1. 2. All voltages referenced to VSS Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifications and device operations are guaranteed for the full voltage range specified. Outputs are measured with equivalent load: 13. 12.
WV3EG128M72EFSR-D3
ADVANCED
The refresh period is 64ms. This equates to an average refresh rate of 15.625µs (256Mb component) or 7.8125µs (512 Mb component). However, an AUTO REFRESH command must be asserted at least once every 140.6µs (256 Mb component) or 70.3µs (512Mb component); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. Referenced to each output group: x4 = DQS with DQ0-DQ4. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. JEDEC specifies CK and CK# input slew rate must be > 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain. tHP min is the lesser of tCL min and tCH min actually applied to the device CK and CK# inputs, collectively during bank active. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ (MAX) and last DVW. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. CKE must be active (High) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands).
3.
VTT Output (VOUT) 50Ω Reference Reference Point Point 30pF
14. 15. 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are defined in the SSTL_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level). Command/Address input slew rate = 0.5V/ns. For -75 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ). The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS.
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March 2005 Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3EG128M72EFSR-D3
ADVANCED
ORDERING INFORMATION FOR D3
Part Number WV3EG128M72EFSR335D3 WV3EG128M72EFSR262D3 WV3EG128M72EFSR265D3
NOTES: • Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option
Speed 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s
CAS Latency 2.5 2 2.5
tRCD 3 2 3
tRP 3 2 3
Height* 29.97 (1.18") 29.97 (1.18") 29.97 (1.18")
PACKAGE DIMENSIONS FOR D3
133.35 (5.25) 128.95 (5.076) 2x 3.00 (2x 0.118) 4x 4.00+/-0.1 (4x 0.157+/-0.004) 19.80 (0.779) 29.97 ±0.15 (1.18 ±0.006) March 2005 Rev. 0 1.27 +/-0.1 (0.05+/-0.004)
12.00 (0.472)
2x DIA. 2.50 +0.1/-0.00 (2x DIA 0.098 + 0.004/-0.00) 1 6.35 (0.25)
2.175 (0.085) 3.80 (0.149)
6.35 (0.25) 4.175 (0.164) 1.80 (0.070)
1.0 ±0.05 (0.039 ±0.002)
10.00 (0.393)
92
1.27 (0.05) 49.53 (1.95)
0.20 ±0.15 (0.008 ±0.006) 2.50 (0.098)
3.99 MAX (0.157 MAX)
64.77 (2.55)
120.65 (4.75)
93
184
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3EG128M72EFSR-D3
ADVANCED
PART NUMBERING GUIDE
WV 3 E G 128M 72 E F S R xxx D3 x F/G
WEDC MEMORY DDR GOLD DEPTH BUS WIDTH x8 FBGA 2.5V REGISTERED SPEED (MHz) PACKAGE 184 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) F = LEAD-FREE, G = ROHS COMPLIANT
March 2005 Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
Document Title
1GB - 128Mx72 DDR SDRAM REGISTERED w/PLL, FBGA
WV3EG128M72EFSR-D3
ADVANCED
Revision History Rev #
Rev 0
History
Created
Release Date
3-05
Status
Advanced
March 2005 Rev. 0
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com