WV3EG216M64STSU335D4MG

White Electronic Designs WV3EG216M64STSU-D4 PRELIMINARY* 256MB – 2x16Mx64 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture PC2700@CL=2.5 Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh, (8K/64ms refresh) Serial presence detect with EEPROM Power Supply: VCC/VCCQ: 2.5V ± 0.20V Dual Rank Standard 200 pin SO-DIMM package • Package height options: D4: 31.75mm (1.25") NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change without notice. DESCRIPTION The WV3EG216M64STSU is a 2x16Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of eight 16Mx16 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. OPERATING FREQUENCIES DDR333@CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VREF VSS VSS DQ0 DQ4 DQ1 DQ5 VCC VCC DQS0 DM0 DQ2 DQ6 VSS VSS DQ3 DQ7 DQ8 DQ12 VCC VCC DQ9 DQ13 DQS1 DM1 VSS VSS DQ10 DQ14 DQ11 DQ15 VCC VCC CK0 VCC CK0# VSS VSS VSS DQ16 DQ20 DQ17 DQ21 VCC VCC DQS2 DM2 DQ18 DQ22 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VSS VSS DQ19 DQ23 DQ24 DQ28 VCC VCC DQ25 DQ29 DQS3 DM3 VSS VSS DQ26 DQ30 DQ27 DQ31 VCC VCC NC NC NC NC VSS VSS NC NC NC NC VCC VCC NC NC NC NC VSS VSS NC VSS NC VCC VCC VCC CKE1 CKE0 NC NC A12 A11 Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol A9 A8 VSS VSS A7 A6 A5 A4 A3 A2 A1 A0 VCC VCC A10 BA1 BA0 RAS# WE# CAS# CS0# CS1# NC NC VSS VSS DQ32 DQ36 DQ33 DQ37 VCC VCC DQS4 DM4 DQ34 DQ38 VSS VSS DQ35 DQ39 DQ40 DQ44 VCC VCC DQ41 DQ45 DQS5 DM5 VSS VSS Pin 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol DQ42 DQ46 DQ43 DQ47 VCC VCC VCC CK1# VSS CK1 VSS VSS DQ48 DQ52 DQ49 DQ53 VCC VCC DQS6 DM6 DQ50 DQ54 VSS VSS DQ51 DQ55 DQ56 DQ60 VCC VCC DQ57 DQ61 DQS7 DM7 VSS VSS DQ58 DQ62 DQ59 DQ63 VCC VCC SDA SA0 SCL SA1 VCCSPD SA2 NC NC WV3EG216M64STSU-D4 PRELIMINARY* PIN NAMES A0 – A12 BA0-BA1 DQ0-DQ63 DQS0-DQS7 CK0, CK1 CK0#, CK1# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DM0-DM7 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock Input Clock Input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM No Connect White Electronic Designs Corp. reserves the right to change products or specifications without notice. August 2005 Rev. 0 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG216M64STSU-D4 PRELIMINARY* FUNCTIONAL BLOCK DIAGRAM CS1# CS0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 CS# LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 CS# DQS4 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 CS# LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 CS# DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQS5 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQS2 DM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 CS# LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 CS# DQS6 DM6 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 CS# LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 CS# DQS3 DM3 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQS7 DM7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 BA0, BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE# BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs CKE1: DDR SDRAMs WE#: DDR SDRAMs Clock Wiring Clock Input CK0/CK0# CK1/CK1# CK2/CK2# SDRAMs 4 SDRAMs 4 SDRAMs NC *Clock Net Wiring DDR SDRAMs DDR SDRAMs R = 120 Ohm VCCSPD VCC/VCCQ VREF VSS SPD CK0/1/2 CK0/1/2# Card Edge DDR SDRAM DDR SDRAM DDR SDRAM SERIAL PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA DDR SDRAMs DDR SDRAMs NOTE: All resistor values are 22 ohms unless otherwise specified. NOTES: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown. White Electronic Designs Corp. reserves the right to change products or specifications without notice. August 2005 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Parameter Voltage on any pin relative to VSS Voltage on VCC and VCCQ supply relative to VSS Storage temperature Operating temperature Power Dissipation Short circuit output current WV3EG216M64STSU-D4 PRELIMINARY* ABSOLUTE MAXIMUM RATINGS Symbol VIN, VOUT VCC, VCCQ TSTG TA PD IOS Value -0.5 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 0 ~ 70 8 50 Units V V °C °C W mA NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) Addr, CAS#, RAS#, WE# CS#, CKE CK, CK# DM Parameter Supply voltage DDR266/DDR333 (nominal VCC of 2.5V) I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V) I/O Reference voltage I/O Termination voltage Input logic high voltage Input logic low voltage Input voltage level, CK and CK# Input differential voltage, CK and CK# Input crossing point voltage, CK and CK# Min 2.3 2.3 0.49*VCCQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.3 0.3 -16 -8 -8 -4 -10 -16.8 16.8 -9 9 Max 2.7 2.7 0.51*VCCQ VREF+0.04 VCCQ+0.30 VREF-0.15 VCCQ+0.30 VCCQ+0.60 VCCQ+0.60 16 8 8 4 10 — — — — Unit V V V V V V V V uA uA uA uA uA mA mA mA mA Note 1 2 3 Input leakage current II Output leakage current Output high current (normal strengh); VOUT = V +0.84V Output high current (normal strengh); VOUT = VTT -0.84V Output high current (half strengh); VOUT = VTT +0.45V Output high current (half strengh); VOUT = VTT -0.45V IOZ IOH IOL IOH IOL NOTES: 1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed ±2% of the DC value 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors,is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#. CAPACITANCE VCC = 2.5V, VCCQ =2.5V, TA = 25°C, f = 1MHz Parameter Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#) Input Capacitance (CKE0, CKE1) Input Capacitance (CS0#, CS1#) Input Capacitance (CK0,CK0#, CK1, CK1#) Input Capacitance (DM0-DM7) Data and DQS input/output capacitance (DQ0-DQ63), CB0-7 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT Min 20 12 12 12 12 12 Max 28 16 16 16 14 14 Unit pF pF pF pF pF pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. August 2005 Rev. 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Parameter/Condition Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Differential Voltage, CK and CK# inputs Input Crossing Point Voltage, CK and CK# inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF +0.31 WV3EG216M64STSU-D4 PRELIMINARY* AC OPERATING TEST CONDITIONS Max VREF -0.31 VCCQ+0.6 0.5*VCCQ+0.2 Unit V V V V Note 1 1 0.7 0.5*VCCQ-0.2 NOTES: 1. VIH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate. White Electronic Designs Corp. reserves the right to change products or specifications without notice. August 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG216M64STSU-D4 PRELIMINARY* IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V Parameter Operating current - One bank ActivePrecharge Operating current - One bank operation Percharge powerdown standby current Precharge Floating standby current Active power - down standby current Active standby current Symbol IDD0* Conditions tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One bank open, BL=4, Reads - Refer to the following page for detailed test condition All banks idle; power - down mode; CKE = = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ,DQS and DM one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC = tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0mA Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B Four bank interleaving with BL=4 -Refer to the following page for detailed test condition DDR333 @ CL = 2.5 Max 372 Unit mA IDD1* IDD2P** IDD2F** 512 24 240 mA mA mA IDD3P** 280 mA IDD3N** 440 mA Operating current - burst read IDD4R* 812 mA Operating current - burst write IDD4W* 772 mA Auto refresh current Self refresh current; CKE =< 0.2V Orerating current - Four bank operation IDD5** IDD6** IDD7A* 1440 24 1412 mA mA mA NOTE: IDD specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different. * Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode. ** Value calculated as all module ranks in this operation condition. White Electronic Designs Corp. reserves the right to change products or specifications without notice. August 2005 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG216M64STSU-D4 PRELIMINARY* IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V Parameter Operating current - One bank ActivePrecharge Operating current - One bank operation Percharge powerdown standby current Precharge Floating standby current Active power - down standby current Active standby current Symbol IDD0* Conditions tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One bank open, BL=4, Reads - Refer to the following page for detailed test condition All banks idle; power - down mode; CKE = = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs changing once per clock cycle; VIN = VREF for DQ,DQS and DM one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and DM CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC = tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle Burst length = 2; reads; continguous burst; One bank active; address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0mA Burst length = 2; writes; continuous burst; One bank active address and control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of input data changing at every burst tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B Four bank interleaving with BL=4 -Refer to the following page for detailed test condition DDR333 @ CL = 2.5 Max 288 Unit mA IDD1* IDD2P** IDD2F** 304 32 200 mA mA mA IDD3P** 80 mA IDD3N** 312 mA Operating current - burst read IDD4R* 364 mA Operating current - burst write IDD4W* 408 mA Auto refresh current Self refresh current; CKE =< 0.2V Orerating current - Four bank operation IDD5** IDD6** IDD7A* 944 16 844 mA mA mA NOTE: IDD specification is based on Nanya components. Other DRAM Manufacturers specification may be different. * Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode. ** Value calculated as all module ranks in this operation condition. White Electronic Designs Corp. reserves the right to change products or specifications without notice. August 2005 Rev. 0 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG216M64STSU-D4 PRELIMINARY* DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V Parameter Row Cycle Time Refresh row cycle time Row active RAS# to CAS# delay Row precharge time Row active to row active delay Write recovery time Last data into Read command Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK# Output data access time from CK/CK# Data strobe edge to output data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge to CK rising-hold time DQS-in high level width DQS-in low level width Address and control input setup time (fast) Address and control input hold time (fast) Address and control input setup (slow) Address and control input hold time (slow) Data-out high impedence time from CK/CK# Data-out low impedence time from CK/CK# Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & address input pulse width DQ & DM input pulse width Exit self refresh o non-Read command Exit self refresh to Read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble Active Read with Auto precharge command Auto precharge Write recovery + Precharge time Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tIS tIH tIS tIH tHZ tLZ tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tRAL 335 Min 60 72 42 18 18 12 15 1 6 0.45 0.55 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.75 0.75 0.7 0.7 -0.7 -0.7 10 0.4 0.4 2.2 1.75 75 200 tHP - tQHS tCLmin or tCHmin 0.4 18 (tWR/tCK) + (tRP/tCK) Max Unit ns ns ns ns ns ns ns tCK ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK us ns ns ns ns ns tCK 120K CL=2.5 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 +0.7 +0.7 7.8 — — 0.55 0.6 White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG216M64STSU-D4 PRELIMINARY* ORDERING INFORMATION FOR D4 Part Number WV3EG216M64STSU335D4xG Speed 166MHz/333Mbps, CL=2.5 Height* 31.75mm (1.25") NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung, N = Nanya & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR D4 67.60 (2.661) 63.60 (2.504) Full R 2x 3.80 (0.150) MAX. 4.00 ±0.10 (0.158 ±0.039) 31.75 (1.25) 20 (0.787) 1 39 41 199 6.0 0.236 11.40 (0.449) 2.15 (0.085) 2.45 (0.098) 1.8 (0.071) 1.00 ±0.1 (0.04 ±0.0039) 4.20 (0.165) 2.40 (0.094) 47.40 (1.866) 2- 1.80 (0.071) 1.0 ± 0.1 (0.04 ± 0.0039) 0.60 (0.024) 0.45 ±0.03 (0.018 ±0.001) 0.25 (0.01) 2.55 Min (0.102 Min) 4.00 (0.158) MIN. 4.00 ±0.10 (0.158 ±0.039) Tolerances: ±0.15 (0.006) unless otherwise specified * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3EG216M64STSU-D4 PRELIMINARY* PART NUMBERING GUIDE WV 3 E G 216M 64 S T S U xxx D4 x G WEDC MEMORY DDR GOLD DEPTH (Daul Rank) BUS WIDTH x16 TSOP 2.5V UNBUFFERED SPEED (MHz) PACKAGE 200 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) (N = Nanya) G = RoHS COMPLIANT White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs Document Title 256MB – 2x16Mx64, DDR SDRAM UNBUFFERED WV3EG216M64STSU-D4 PRELIMINARY* Revision History Rev # Rev 0 Rev 1 History Created 1.1 Added Samsung IDD specs Release Date 8-05 12-05 Status Preliminary Preliminary White Electronic Designs Corp. reserves the right to change products or specifications without notice. December 2005 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com