WT6014

WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 GENERAL DESCRIPTION The WT6014 is a member of WT60XX microcontroller family. It is specially designed for digital controlled multi-sync monitor. It contains 8-bit CPU, 4K bytes ROM, 128 bytes RAM, 14 PWMs, parallel I/O, SYNC processor, timer, DDC interface (slave mode I2C interface with DDC1), and watch-dog timer. FEATURES * 8-bit 6502 compatible CPU, 4MHz operating frequency * 4096 bytes ROM, 128 bytes SRAM * 8MHz crystal oscillator * 14 channels 8-bit/62.5kHz PWM outputs (8 open drain outputs & 6 CMOS outputs) * Sync signal processor with sync separation, frequency calculation, H/V polarity detection control * DDC interface supports VESA DDC1/DDC2B standard * Watch-dog timer (0.524 second) * Maximum 22 programmable I/O pins * One 8-bit programmable timer * One external interrupt request * Built-in low VDD voltage reset * Single +5V power supply PIN ASSIGNMENT 40-Pin PDIP DA2 DA1 DA0 RESET VDD GND OSCO OSCI PB5 PB4 PB3 PB2 PB1 PB0 IRQ PC7 PC6 PC5 PC4 PC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSYNC HSYNC DA3 DA4 DA5 DA6 DA7 PA7/HSO PA6/VSO PA5/DA13 PA4/DA12 PA3/DA11 PA2/DA10 PA1/DA9 PA0/DA8 SCL SDA PC0 PC1 PC2 GND OSCO OSCI PB5 PB4 PB3 PB2 PB1 PB0 IRQ PC7 PC6 PC5 PC4 PC3 DA2 DA1 DA0 RESET VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42-Pin SDIP 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 DA6 DA7 PA7/HSO PA6/VSO PA5/DA13 PA4/DA12 PA3/DA11 PA2/DA10 PA1/DA9 PA0/DA8 SCL SDA PC0 PC1 PC2 VSYNC HSYNC DA3 DA4 DA5 * I2C is a trademark of Philips Corporation. * DDC is a trademark of Video Electronics Standard Association (VESA). Weltrend Semiconductor, Inc. 1 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 PIN DESCRIPTION Pin No. 40 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 38 39 40 41 42 Pin Name DA2 DA1 DA0 /RESET VDD GND OSCO OSCI PB5 PB4 PB3 PB2 PB1 PB0 /IRQ PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SDA SCL PA0/DA8 PA1/DA9 PA2/DA10 PA3/DA11 PA4/DA12 PA5/DA13 PA6/VSO PA7/HSO DA7 DA6 DA5 DA4 DA3 HSYNC VSYNC I/O O O O I Descriptions D/A converter 2. Open-drain output. External applied voltage can up to 10V. D/A converter 1. Open-drain output. External applied voltage can up to 10V. D/A converter 0. Open-drain output. External applied voltage can up to 10V. Reset. Active low. Schmitt trigger input, Internal pull high. Power supply (+5V). Ground (0V). Oscillator Output. Connects a 8MHz crystal. Oscillator Input. Connects a 8MHz crystal. I/O Port B5. When it is an input pin, it has an internal pull-up resistor. When it is an output pin, the sink current is 5mA and the source current is 5mA. I/O Port B4. Same as PB5. I/O Port B3. Same as PB5. I/O Port B2. Same as PB5. I/O Port B1. Same as PB5. I/O Port B0. Same as PB5. Interrupt Request . It has an internal pull high resistor. I/O Port C7. When it is an input pin, it has an internal pull-up resistor. When it is an output pin, the sink current is 10mA and the source current is 5mA. I/O Port C6. Same as PC7. I/O Port C5. Same as PC7. I/O Port C4. Same as PC7. I/O Port C3. Same as PC7. I/O Port C2. Same as PC7. I/O Port C1. Same as PC7. I/O Port C0. Same as PC7. DDC serial data. DDC serial clock. I/O Port A0 or D/A converter 8. This pin can be the output of D/A converter 8 (source/sink = 5mA) or an I/O pin (source = -100uA, sink = 5mA). I/O Port A1 or D/A converter 9. Same as PA0/DA8. I/O Port A2 or D/A converter 10. Same as PA0/DA8. I/O Port A3 or D/A converter 11. Same as PA0/DA8. I/O Port A4 or D/A converter 12. Same as PA0/DA8. I/O Port A5 or D/A converter 13. Same as PA0/DA8. I/O Port A6 / VSYNC OUT. This pin can be the output of VSYNC or an I/O pin. When as an I/O pin, it is same as PA0. I/O Port A7 / HSYNC OUT. This pin can be the output of HSYNC or an I/O pin. When as an I/O pin, it is same as PA0. D/A converter 7. Open-drain output. External applied voltage can up to 10V. D/A converter 6. Open-drain output. External applied voltage can up to 10V. D/A converter 5. Open-drain output. External applied voltage can up to 10V. D/A converter 4. Open-drain output. External applied voltage can up to 10V. D/A converter 3. Open-drain output. External applied voltage can up to 10V. HSYNC input. Schmitt trigger input. VSYNC input. Schmitt trigger input. O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O I I Weltrend Semiconductor, Inc. 2 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 FUNCTIONAL DESCRIPTION CPU The CPU core is 6502 compatible, operating frequency is 4MHz. Address bus is 16-bit and data bus is 8-bit. the non-maskable interrupt (/NMI) of 6502 is changed to maskable interrupt and is defined as the INT0. The interrupt request (/IRQ) of 6502 is defined as the INT1. The initial stack pointer is 00FFH, because page 1 and page 0 are mapped to same area. Please refer the 6502 reference menu for more detail. ROM 4096 bytes maskable ROM is provided for program codes. Address is located from F000H to FFFFH. The following addresses are reserved for special purpose : FFFAH (low byte) and FFFBH (high byte) : INT0 interrupt vector. FFFCH (low byte) and FFFDH (high byte) : program reset vector. FFFEH (low byte) and FFFFH (high byte) : INT1 interrupt vector. RAM Built-in 128 bytes SRAM, address is located from 0080H to 00FFH 0000H : REGISTERS 001CH 001DH : Reserved 007FH 0080H : RAM 00FFH 0100H : Page 1 mapped to Page 0 01FFH 0200H : EFFFH F000H : : : FFFFH Reserved ROM Low VDD Voltage Reset A VDD voltage detector is built inside the chip. When VDD is below 4.0 volts, the whole chip will be reset just like power-on-reset. Note that the 4.0 volts varies with temperature and process. Please refer the electrical characteristics. Weltrend Semiconductor, Inc. 3 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 PWM D/A Converter The WT6014 provides 14 PWM D/A converters. DA0 to DA7 are open-drain outputs and external applied voltage on these pins can be up to 10 volts. DA8 to DA13 are 5 volts push-pull CMOS outputs and are shared with I/O Port PA0 to PA5. All D/A converters are 62.5kHz frequency with 8-bit resolution. Each D/A converter is controlled by the corresponding register (REG#00H to REG#0DH), the duty cycle can be programmed from 1/256 (data = 01H) to 255/256 (data = FFH). Duty cycle = 1/256 62.5ns Duty cycle = 2/256 125ns 62.5ns Duty cycle = 255/256 1/62.5kHz=16us To program the PWM D/A converters, write the corresponding registers ( REG#00H to REG#0DH). Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H Bit7 DA07 DA17 DA27 DA37 DA47 DA57 DA67 DA77 DA87 DA97 DA107 DA117 DA127 DA137 Bit6 DA06 DA16 DA26 DA36 DA46 DA56 DA66 DA76 DA86 DA96 DA106 DA116 DA126 DA136 Bit5 DA05 DA15 DA25 DA35 DA45 DA55 DA65 DA75 DA85 DA95 DA105 DA115 DA125 DA135 Bit4 DA04 DA14 DA24 DA34 DA44 DA54 DA64 DA74 DA84 DA94 DA104 DA114 DA124 DA134 Bit3 DA03 DA13 DA23 DA33 DA43 DA53 DA63 DA73 DA83 DA93 DA103 DA113 DA123 DA133 Bit2 DA02 DA12 DA22 DA32 DA42 DA52 DA62 DA72 DA82 DA92 DA102 DA112 DA122 DA132 Bit1 DA01 DA11 DA21 DA31 DA41 DA51 DA61 DA71 DA81 DA91 DA101 DA111 DA121 DA131 Bit0 DA00 DA10 DA20 DA30 DA40 DA50 DA60 DA70 DA80 DA90 DA100 DA110 DA120 DA130 Bit Name DAx7-DAx0 Bit value 01H : 1/256 duty cycle 02H : 2/256 duty cycle 03H : 3/256 duty cycle : FFH : 255/256 duty cycle ** Do not write 00H to the PWM registers. This will cause unstable output on the corresponding pin. Weltrend Semiconductor, Inc. 4 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 I/O Ports Port_A : Pin PA0/DA8 Pin PA1/DA9 Pin PA2/DA10 Pin PA3/DA11 Pin PA4/DA12 Pin PA5/DA13 Pin PA6/VSO Pin PA7/HSO - general purpose I/O shared with DA8 output. - general purpose I/O shared with DA9 output. - general purpose I/O shared with DA10 output. - general purpose I/O shared with DA11 output. - general purpose I/O shared with DA12 output. - general purpose I/O shared with DA13 output. - general purpose I/O shared with VSYNC output. - general purpose I/O shared with HSYNC output. Port_A is controlled by REG#10H & REG#11H. In REG#10H, each corresponding bit enables HSYNC output, VSYNC output or D/A converter output when it is "1". If the corresponding bit is "0", the output level is decided by REG#11H. In REG#11H, if the I/O corresponding bit (PAn) is "0", the output is low level (IOL=5mA). If PAn bit is "1", the output is high level (IOH= -100uA) and can be used as an input. Address 0010H 0011H 0011H R/W W W R Initial 00H FFH -Bit7 EHO PA7W PA7R Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 EVO EDA13 EDA12 EDA11 EDA10 EDA9 PA6W PA5W PA4W PA3W PA2W PA1W PA6R PA5R PA4R PA3R PA2R PA1R Bit value = “0” PA7 as general purpose I/O. PA6 as general purpose I/O. PA5 as general purpose I/O. PA4 as general purpose I/O. PA3 as general purpose I/O. PA2 as general purpose I/O. PA1 as general purpose I/O. PA0 as general purpose I/O. Outputs low level (IOL= 5mA). Pin is low level. Bit0 EDA8 PA0W PA0R Bit Name EHO EVO EDA13 EDA12 EDA11 EDA10 EDA9 EDA8 PA7W - PA0W PA7R- PA0R Bit value = “1” Enable PA7 as HSYNC output. Enable PA6 as VSYNC output. Enable PA5 as DA13 output. Enable PA4 as DA12 output. Enable PA3 as DA11 output. Enable PA2 as DA10 output. Enable PA1 as DA9 output. Enable PA0 as DA8 output. Outputs high level (IOH= -100uA). Pin is high level. * If the program wants to force VSYNC output (VSO pin) in low state, write "0" to PA6 bit first, then write "0" to EVO bit. This is used to prevent high frequency output on VSO pin when the VSYNC frequency is increased to read EDID data in DDC1 mode. EDAx DAx 5mA PAnW 5mA 100uA Pin PAn PAnR Weltrend Semiconductor, Inc. 5 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 Port_B : Pin PB0 to PB5 - general purpose I/O pins. The source/sink current of port_B is 5mA when as an output. When it is input, an internal pull high resistor is connected. Address 0012H 0013H 0013H R/W W W R Initial 00H FFH -Bit7 0 1 -Bit6 0 1 -Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PB5OE PB4OE PB3OE PB2OE PB1OE PB0OE PB5W PB4W PB3W PB2W PB1W PB0W PB5R PB4R PB3R PB2R PB1R PB0R Bit value = “0” Output disable (internal pull-up). Outputs low level (IOL= 5mA). Pin is low level. Bit Name PB5OE - PB0OE PB5W - PB0W PB5R- PB0R Bit value = “1” Output enable. Outputs high level (IOH= -5mA). Pin is high level. PBnOE 5mA Pin PB0 to PB5 5mA PBnW 100uA PBnR Structure of I/O Port B Weltrend Semiconductor, Inc. 6 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 Port_C : Pin PC0 to PC7 - general purpose I/O pins. The REG#14H defines the I/O direction and the REG#15H controls the output level. The structure of Port_C is same as the Port_B except the sink current is 10mA. Address 0014H 0015H 0015H R/W W W R Initial 00H FFH -Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PC7OE PC6OE PC5OE PC4OE PC3OE PC2OE PC1OE PC0OE PC7W PC6W PC5W PC4W PC3W PC2W PC1W PC0W PC7R PC6R PC5R PC4R PC3R PC2R PC1R PC0R Bit value = “0” Output disable (internal pull-up). Outputs low level (IOL= 10mA). Pin is low level. Bit Name PC7OE - PC0OE PC7W - PC0W PC7R - PC0R Bit value = “1” Output enable. Outputs high level (IOH= -5mA). Pin is high level. * If program wants to read current status on the I/O pins (any I/O port), do not set output enable bit to “0”. Because the registers for reading I/O are always indicating the current state on the I/O pins, set output enable bit to “0” will change the level on the I/O pin. Please reference the I/O pin structure. PCnOE 5mA Pin PC0 to PC7 10mA PCnW 100uA PCnR Structure of I/O Port C Weltrend Semiconductor, Inc. 7 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 SYNC Processor The SYNC processor can : (1) calculate HSYNC and VSYNC frequencies; (2) detect polarities of HSYNC and VSYNC inputs; (3) control the output polarities of HSO and VSO pins. Frequency Calculation Horizontal frequency and vertical frequencies calculation are done by using one 10-bit up counter. After power is on, the SYNC processor calculates the vertical frequency first (H/V bit ="0"). A 31.25KHz clock counts the time interval between two VSYNC pulses, then sets the FRDY bit and generates an INT1 interrupt (if IEN_S bit is "1"). The software can either use interrupt or polling the FRDY bit to read the correct vertical frequency. After reading the REG#16H, the FRDY bit is cleared to "0", counter is reset and H/V bit is set. The SYNC processor starts to count horizontal frequency. The horizontal frequency calculation is done by counting the HSYNC pulses in 8.192 ms. Like the vertical frequency, the horizontal frequency can be read when the FRDY bit is set or INT1 occurs. After reading the REG#16H, the FRDY, INT_S and H/V bits are cleared. The SYNC processor starts to calculate the vertical frequency again, and so on. The relationships between counter value and frequency are : Hfreq = (counter value x 122.07) Hz Vfreq = ( 31250 / counter value ) Hz The frequency range : Hfreq range : 122.07 Hz to 124.8 kHz ; Resolution : 122.07Hz Vfreq range : 30.5 Hz to 31.25 kHz If counter overflowed, the OVF1 bit will be set to "1". The counter keeps on counting until it overflowed again. The OVF2 bit and FRDY bit will be set when counter overflowed twice. This is designed for finding the vertical frequency bellows 15.25Hz. The program should check REG#17H before reading REG#16H. Polarity Detect/Control The polarities of HSYNC and VSYNC are automatically detected and are shown in the H_POL and V_POL bits. The polarities of HSO and VSO are controlled by the HOP and VOP bits. For example, set HOP bit to “1”, the HSO pin always outputs positive horizontal sync signal, whatever the HSYNC input’s polarity is. Address 0016H 0017H 0017H R/W R W R Initial --00H Bit7 F9 0 H/V Bit6 F8 0 -Bit5 Bit4 Bit3 F7 F6 F5 0 0 0 H_POL V_POL OVF2 Bit2 F4 0 OVF1 Bit1 F3 HOP F1 Bit0 F2 VOP F0 Bit Name HOP VOP H/V H_POL V_POL OVF2, OVF1 F9-F0 Bit value = “1” Bit value = “0” HSO pin is always positive polarity. HSO pin is always negative polarity. VSO pin is always positive polarity. VSO pin is always negative polarity. Counter stores horizontal frequency. Counter stores vertical frequency. HSYNC input is positive polarity. HSYNC input is negative polarity. VSYNC input is positive polarity. VSYNC input is negative polarity. OVF2=“1”,OVF1=“0” : Counter overflowed twice. OVF2=“0”,OVF1=“1” : Counter overflowed once. OVF2=“0”,OVF1=“0” : No overflow. OVF2=“1”,OVF1=“1” : No such condition. Frequency counter value. (F9 is MSB) Weltrend Semiconductor, Inc. 8 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 DDC Interface The DDC interface is a slave mode I2C interface with DDC1 function. It is fully compatible with VEAS DDC1/2B standard. The functional block diagram is shown in the below. Internal Data ENACK Data Buffer SDA I/O VSYNC MUX Shift Register R/W Address Compare MSB ADDR START STOP DDC2B SCL 1010000 Address Register START/STOP Detect Handshake Control After power on or reset the DDC interface, it is in DDC1 state. The shift register shifts out data to SDA pin on the rising edge of VSYNC clock. Data format is an 8-bit byte followed by a null bit. Most significant bit (MSB) is transmitted first. Every time when the ninth bit has been transmitted, the shift register will load a data byte from data buffer (REG#18H). After loading data to the shift register, the data buffer becomes empty and generates an INT0 interrupt. So the program must write one data byte into REG#18 every nine VSYNC clocks. Since the default values of data buffer(REG#22) and shift register are FFH, the SDA pin outputs high level if no data had been written into data buffer after power on reset. When program finished initialization and set the IEN_D bit to "1", the INT0 will occur because the data buffer is empty. The INT0 service routine should check the DDC2B bit is "0" and then writes the first EDID data byte into data buffer. When the second INT0 occurs, the INT0 service routine writes the second EDID data byte into data buffer and so on. SDA VSYNC Load data to shift register INT0 IEN_D Bit7 1 2 3 9 10 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 18 Bit7 19 Weltrend Semiconductor, Inc. 9 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 If a low level occurs on the SCL pin in DDC1 state, the DDC interface will switch to DDC2B state immediately and set the DDC2B bit to "1". No interrupt will be generated. But, if there is no valid device address and it receives 128 VSYNC pulses while the SCL is high level, it will go back to DDC1 state automatically. If it receives a valid device address, it will lock into DDC2B state and disregard VSYNC. In some case, program wants to go back DDC1 state, set RDDC bit in REG#1AH and reset it again. This operation resets the DDC interface to the initial condition. When it is in DDC2B state, the VSYNC clock is disregarded and the communication protocol follows the DDC standard. The data format on SDA pin is: S Address R/W A D7,D6,...., D0 A D7,D6,...., D0 A P S : Start condition. A falling edge occurs when SCL is high level. P : Stop condition. A rising edge occurs when SCL is high level. A : Acknowledge bit. “0” means acknowledge and “1” means non-acknowledge. Address : 7-bit device address. R/W : Read/Write control bit, "1" is read and "0" is write. D7,D6,...., D0 : data byte. The hardware operations in DDC2B state are : (1) START/STOP detection When the START condition is detected, the DDC interface is enabled and set START bit to "1". When the STOP condition is detected, the DDC interface is disabled, set STOP bit to "1" and generate INT0 interrupt. The START bit is cleared when the following data byte received. The STOP bit is cleared after writing REG#19H. (2) Address Recognition It contains two device addresses in WT6014. One fixed address (‘1010000’) is for EDID reading and one programmable address (REG#19H) is for external control, such as auto alignment. If the address is equal to "1010000", set ADDR bit to "0". If the address is equal to the bit A6 to bit A0 (REG#19H), set ADDR bit to "1". If the address is not equal to anyone above, the DDC interface will not response acknowledge. The ADDR bit is updated when a new device address is received. (3) Store R/W bit and decide the direction of SDA pin The R/W bit on the SDA pin will be stored in the RW bit. (4) Acknowledge bit control/detection Acknowledge bit control in receive direction : If ENACK=1 and address compare is true, response acknowledge (Acknowledge bit ="0"). If ENACK=0 or address compare is false, response non-acknowledge (Acknowledge bit ="1"). Acknowledge bit detect in transmit direction : If the acknowledge bit is "1" , the DDC interface will be disabled and release the SDA pin. If the acknowledge bit is "0" , the DDC interface keeps on communicating. Weltrend Semiconductor, Inc. 10 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 (5) Data bytes transmit/receive If the RW bit is "1", the shift register will load data from the data buffer (REG#18H) before the data byte is transmitted and shift out data to the SDA pin before the rising edge of the SCL clock. If the RW bit is "0", the shift register will shift in data on the rising edge of the SCL clock and the whole data byte is latched to the data buffer(REG#18H). (6) Handshaking procedure The handshaking is done on the byte level. The DDC interface will hold the SCL pin low after the acknowledge bit automatically. The bus master will be forced to wait until the WT6014 is ready for the next byte transfer. To release the SCL pin, write REG#19H will release clear the wait state. (7) Interrupt INT0 The DDC interface interrupt is enabled by setting the IEN_D bit in the REG#1AH. Interrupt INT0 occurs when: - Transmit buffer empty in DDC1 state. The INT0 occurs when the shift register load data from data buffer. Write REG#18H will clear the transmit buffer empty condition. - Acknowledge is detected in DDC2B state. The INT0 occurs on the falling edge of the SCL clock after the acknowledge had been detected. The SCL pin will be pulled low to force the bus master to wait until the REG#19H is written. - STOP condition occurs in DDC2B state Address 0018H 0019H 0019H R/W R/W R W Initial Bit7 Bit6 FFH D7 D6 40H DDC2B ADDR A0H A6 A5 Bit5 D5 RW A4 Bit4 Bit3 D4 D3 START STOP A3 A2 Bit2 D2 -A1 Bit1 D1 -A0 Bit0 D0 -ENACK Bit Name DDC2B ADDR RW START STOP ENACK A6,A5, … A0 ., D7,D6, … D0 ., Bit value = “1” Bit value = “0” DDC2B state. DDC1 state. received address equals to the address received address equals to ‘1010000’. in REG#19H(W). received R/W bit is ‘1’. received R/W bit is ‘0’. START condition is detected. No START condition is detected. STOP condition is detected. No STOP condition is detected. Enable acknowledge. Disable acknowledge. 7-bit slave address Data to be transmitted or received data. Weltrend Semiconductor, Inc. 11 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 Pull low SCL SCL SDA In SDA Out Write REG#19H to release SCL Shift register to data buffer INT0 1 01 0 0000 A Data Byte Pull low SCL Pull low SCL Data Byte A A DDC2B=1 ADDR=0 R/W=0 START=1 STOP=0 DDC2B=1 ADDR=0 R/W=0 START=0 STOP=0 DDC2B=1 ADDR=0 R/W=0 START=0 STOP=0 DDC2B=1 ADDR=0 R/W=0 START=0 STOP=1 DDC2B state write timing Pull low SCL SCL SDA In SDA Out Write REG#19H to release SCL Data buffer to shift reg INT0 1 01 0 0001 A Data Byte Pull low SCL A Data Byte N DDC2B=1 ADDR=0 R/W=1 START=1 STOP=0 DDC2B=1 ADDR=0 R/W=1 START=0 STOP=0 DDC2B=1 ADDR=0 R/W=1 START=0 STOP=1 DDC2B state read timing Weltrend Semiconductor, Inc. 12 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 Interrupt Control There are two interrupt sources : INT0 and INT1. INT0 has the higher priority. Interrupt vector : INT0 : FFFAH (low byte) and FFFBH (high byte). INT1 : FFFEH (low byte) and FFFFH (high byte). INT0 occurs when : (1) data buffer empty in the DDC1 mode (DDC="1" and DDC2B="0"). (2) acknowledge or STOP condition is detected in the DDC2B mode (DDC="1" and DDC2B="0"). INT1 occurs when : (1) a falling edge or a low level occurs on the /IRQ pin (EXT="1"). (2) the timer is time out (TIM="1"). (3) SYNC processor has a valid frequency (SYNC="1"). If H/V ="0" , it is vertical frequency ready. If H/V ="1" , it is horizontal frequency ready. INT0 is cleared when : (1) writing the REG#18H in DDC1 state. (2) writing the REG#19H in DDC2B state. INT1 is cleared when : (1) reading the REG#1AH if EXT="1". (2) reading the REG#1BH if TIM="1". (3) reading the REG#16H if SYNC="1". IEN_D DDC D Q 4MHz IEN_X IRQ IEN_T TOUT IEN_S FRDY CK Q INT0 INT1 Weltrend Semiconductor, Inc. 13 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 Address 001AH 001AH R/W W R Initial 00H 00H Bit7 Bit6 IEN_X IEN_T EXT TIM Bit5 Bit4 Bit3 IEN_S IEN_D EDGE SYNC DDC IRQ Bit2 RDDC TOUT Bit1 0 FRDY Bit0 0 -- Bit Name IEN_X IEN_T IEN_S IEN_D EDGE RDDC EXT TIM SYNC DDC IRQ TOUT FRDY Bit value = “1” Bit value = “0” Enable /IRQ pin interrupt. Disable /IRQ pin interrupt. Enable timer interrupt. Disable timer interrupt. Enable SYNC processor interrupt. Disable SYNC processor interrupt. Enable DDC interface interrupt. Disable DDC interface interrupt. /IRQ pin interrupt is edge trigger. /IRQ pin interrupt is level trigger. Reset DDC interface. Clear the reset of DDC interface. DDC interface will always under reset condition if this bit keeps “1”. /IRQ pin interrupt occurs. No /IRQ pin interrupt. Timer interrupt occurs. No timer interrupt. SYNC processor interrupt occurs. No SYNC processor interrupt. DDC interface interrupt occurs. No DDC interface interrupt. /IRQ pin is low level /IRQ pin is high level Timer is time-out. Timer is not time-out. H/V frequency counter is ready. H/V frequency counter is not ready. The counter value is valid. The counter value is invalid. Weltrend Semiconductor, Inc. 14 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 Timer It is a 8-bit down counter and clock frequency is 976.5625Hz (period=1.024ms). The timer is started by writing a value into REG#1BH. When the timer counts down to zero, the timer stops, sets the TOUT bit and generates an INT1 interrupt (if the IEN_T bit is "1"). The TOUT bit will be cleared after REG#1BH is read. Watch-Dog Timer The watch-dog timer is always enable after power is on. Software must clear the watch-dog timer within every 524ms. If the watch-dog timer expired, It will cause the whole chip reset just like external reset. To clear the watch-dog timer, write any data to REG#1CH. Address 001BH 001CH R/W R/W W Initial --Bit7 TM7 WDT Bit6 TM6 WDT Bit5 TM5 WDT Bit4 TM4 WDT Bit3 TM3 WDT Bit2 TM2 WDT Bit1 TM1 WDT Bit0 TM0 WDT Bit Name TM7 to TM0 WDT Bit value Timer value (0 - 255) Write any value to this register will reset the watchdog timer. Weltrend Semiconductor, Inc. 15 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 REGISTER MAP Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH Initial R/W value R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H R/W 80H Bit7 DA07 DA17 DA27 DA37 DA47 DA57 DA67 DA77 DA87 DA97 DA107 DA117 DA127 DA137 Bit6 DA06 DA16 DA26 DA36 DA46 DA56 DA66 DA76 DA86 DA96 DA106 DA116 DA126 DA136 Bit4 Bit2 Bit1 Bit5 Bit3 Bit0 DA05 DA04 DA03 DA02 DA01 DA00 DA15 DA14 DA13 DA12 DA11 DA10 DA25 DA24 DA23 DA22 DA21 DA20 DA35 DA34 DA33 DA32 DA31 DA30 DA45 DA44 DA43 DA42 DA41 DA40 DA55 DA54 DA53 DA52 DA51 DA50 DA65 DA64 DA63 DA62 DA61 DA60 DA75 DA74 DA73 DA72 DA71 DA70 DA85 DA84 DA83 DA82 DA81 DA80 DA95 DA94 DA93 DA92 DA91 DA90 DA105 DA104 DA103 DA102 DA101 DA100 DA115 DA114 DA113 DA112 DA111 DA110 DA125 DA124 DA123 DA122 DA121 DA120 DA135 DA134 DA133 DA132 DA131 DA130 Reserved Reserved EDA13 EDA12 EDA11 EDA10 EDA9 EDA8 PA5R PA4R PA3R PA2R PA1R PA0R PA5W PA4W PA3W PA2W PA1W PA0W PB5OE PB4OE PB3OE PB2OE PB1OE PB0OE PB5R PB4R PB3R PB2R PB1R PB0R PB5W PB4W PB3W PB2W PB1W PB0W PC5OE PC4OE PC3OE PC2OE PC1OE PC0OE PC5R PC4R PC3R PC2R PC1R PC0R PC5W PC4W PC3W PC2W PC1W PC0W F7 F6 F5 F4 F3 F2 H_POL V_POL OVF2 OVF1 F1 F0 0 0 0 0 HOP VOP D5 D4 D3 D2 D1 D0 RW START STOP ---A4 A3 A2 A1 A0 ENACK SYNC DDC IRQ TOUT FRDY -IEN_S IEN_D EDGE RDDC 0 0 TM5 TM4 TM3 TM2 TM1 TM0 CWDT CWDT CWDT CWDT CWDT CWDT W R W W R W W R W R R W R/W R W R W R/W W 00H X FFH 00H X FFH 00H FFH X X 00H X FFH 40H A0H 00H 00H X X EHO EVO PA7R PA6R PA7W PA6W 0 0 --1 1 PC7OE PC6OE PC7R PC6R PC7W PC6W F9 F8 H/V -0 0 D7 D6 DDC2B ADDR A6 A5 EXT TIM IEN_X IEN_T TM7 TM6 CWDT CWDT X -0 : No default value. : No function. : Must write 0.. Weltrend Semiconductor, Inc. 16 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter DC Supply Voltage (VDD) Input and output voltage with respect to Ground All pins except DA0 to DA7 DA0 to DA7 Storage temperature Ambient temperature with power applied Min. -0.3 -0.3 -0.3 -65 -10 Max 7.0 VDD+0.3 11.5V 150 70 Units V V V oC oC * Note : Stresses above those listed may cause permanent damage to the device. D.C. Characteristics ( VDD=5.0V + 5% , Ta=0 - 70 OC) Symbol VDD VIH VIL VSIH VSIL VOH Parameter Supply Voltage Input High Voltage Input Low Voltage Sync Input High Voltage Sync Input Low Voltage Output High Voltage Condition All input pins (except HSYNC and VSYNC) All input pins (except HSYNC and VSYNC) HSYNC and VSYNC pin Min. Typ. Max. Units 4.0 3.0 -0.3 2.0 5 5.5 VDD+ 0.3 1.5 VDD+ 0.3 0.8 V V V V V V V HSYNC and VSYNC pin -0.3 IOH= -100uA 3.5 PA0-PA7 pins IOH= -6mA 3.5 PB0-PB5, PC0-PC7, DA8-DA13, HSO, VSO and HSO pins DA0-DA7 pins (external voltage) SCL and SDA pins (open drain) VOL Output Low Voltage IOL= 5mA PA0-PA7, PB0-PB5, DA0-DA13, SCL, SDA, VSO and HSO pins IOL= 10mA PC0-PC7 pins IIL Input Leakage Current SDA, SCL, HSYNC and VSYNC pins ( VIN = -10 0 to 5V) RPH Pull High Resistance VIN=0.8V 16 PA0-PA7, PB0-PB5, PC0-PC7, /RESET and /IRQ pins IDD Operating Current No load VRESET Reset Voltage /RESET pin 3.8 - 10.5 5.5 0.4 V V V 22 0.4 10 28 V uA Kohm 3 4.0 10 4.2 mA V Weltrend Semiconductor, Inc. 17 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 A.C. Characteristics ( VDD=5.0V + 5%, fosc=8MHz, Ta=0 - 70 C) RESET and IRQ Timing Symbol Parameter tLOW,RES /RESET pin low pulse tLOW,IRQ /IRQ low pulse (level trigger) O Min. 250 250 Typ. - Max. - Units ns ns RESET IRQ tLOW,RES tHIGH,IRQ SYNC Processor Timing Symbol Parameter tHIGH,SYNC HSYNC and VSYNC high time tLOW,SYNC HSYNC and VSYNC low time Min. 250 250 Typ. Max. Units ns ns HSYNC VSYNC tHIGH,SYNC tLOW,SYNC DDC1 Timing Symbol tVAA,DDC1 tMT Parameter SDA output valid from VSYNC rising edge Mode transition time (DDC1 to DDC2B) Min. 125 Typ. Max. 500 500 Units ns ns SCL tMT tVAA,DDC1 SDA Bit 0 (LSB) Null Bit Bit 7 (MSB) VSYNC tHIGH,SYNC tLOW,SYNC Weltrend Semiconductor, Inc. 18 WT6014 Digital Monitor Controller Ver. 1.21 Jul-31-1998 DDC2B Timing Symbol f SCL tBF tHD,START tSU,START tHIGH,SCL tLOW,SCL tHD,DATA tSU,DATA tRISE tFALL tSU,STOP Parameter SCL input clock frequency Bus free time Hold time for START condition Set-up time for START condition SCL clock high time SCL clock low time Hold time for DATA input Hold time for DATA output Set-up time for DATA input Set-up time for DATA output SCL and SDA rise time SCL and SDA fall time Set-up time for STOP condition Min. 0 2 1 1 1 1 0 250 250 500 4 Typ. Max. 100 1 300 Units kHz us us us us us ns ns ns ns us ns us tBF SDA tHD,START SCL tRISE tFALL tSU,STOP tLOW,SCL tHD,DATA tHIGH,SCL tSU,DATA tSU,START Weltrend Semiconductor, Inc. 19