W24258S-70LI

W24258 32K × 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24258 is a normal speed, very low power CMOS static RAM organized as 32768 × 8 bits that operates on a wide voltage range from 2.7V to 5.5V power supply. The W24258 family, W2425870LE and W24258-70LI, can meet requirement of various operating temperature. This device is manufactured using Winbond's high performance CMOS technology. FEATURES • • • • Low power consumption: − Active: 350 mW (max.) − Standby: 6 µW (max.)/3V 25 µW (max.)/5V Access time: 70 nS (max.)/5V 100 nS (max.)/3V Single 3V/5V power supply Fully static operation • • • • • All inputs and outputs directly TTL compatible Three-state outputs Battery back-up operation capability Data retention voltage: 2V (min.) Packaged in 28-pin 600 mil DIP, 330 mil SOP and standard type one TSOP (8 mm × 13.4 mm) PIN CONFIGURATIONS BLOCK DIAGRAM CLK GEN. A12 A14 A2 R O W D E C O D E R PRECHARGE CKT. A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin DIP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 A3 A4 A5 A6 A7 A13 I/O1 I/O8 CORE CELL ARRAY 512 ROWS 64 X 8 COLUMNS DATA CNTRL. CLK GEN. I/O CKT. COLUMN DECODER WE CS OE A11 A10 A1 A0 A8 A9 PIN DESCRIPTION OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 28-pin TSOP SYMBOL A0−A14 I/O1−I/O8 CS WE OE VDD VSS DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground -1- Publication Release Date: November 1998 Revision A8 W24258 TRUTH TABLE CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1− I/O8 High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 IDD IDD IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature LE LI RATING -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 -20 to 85 -40 to 85 UNIT V V W °C °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V ±10%; VDD = 3V ±10%; VSS = 0V; TA (°C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current SYM. VIL VIH ILI ILO TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, CS = VIH (min.) or OE = VIH (min.) or WE = VIL (max.) IOL = +2.1 mA IOH = -1.0 mA 5V ± 10% MIN. -0.5 +2.2 -1 -1 MAX. +0.8 VDD +0.5 +1 +1 3V ± 10% MIN. -0.5 +2.0 -1 -1 MAX. +0.6 VDD +0.5 +1 +1 UNIT V V µA µA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 - 2.2 0.4 - V V -2- W24258 Operating Characteristics, continued PARAMETER SYM. TEST CONDITIONS MIN. 5V ± 10% TYP. 3V ± 10% UNIT MAX. MIN. TYP. MAX. Operating Power Supply Current Standby Power Supply Current IDD CS = VIL (max.), I/O = 0 mA, Cycle = min., Duty = 100% CS = VIH (min.), Cycle = min., Duty = 100% CS ≥ VDD -0.2V - - 70 - - 30 mA ISB - - 3 - - 1 mA ISB1 - 0.7 5 - 0.5 2 µA Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V / 3V. CAPACITANCE (VDD = 5V, TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Input/Output Capacitance SYM. CIN CI/O CONDITIONS VIN = 0V VOUT = 0V MAX. 6 8 UNIT pF pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load CONDITIONS 3V ±10%, 0V to 2.4V 5V ±10%, 0V to 3.0V 5 nS 1.5V See the drawing below AC Test Loads and Waveform 1 TTL OUTPUT 100 pF Including Jig and Scope OUTPUT 5 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW ) 2.4V/3.0V 0V 5 nS 90% 10% 90% 10% 5 nS 1 TTL -3- Publication Release Date: November 1998 Revision A8 W24258 AC Characteristics, continued (VDD = 5V ±10%; VDD = 3V ±10%; VSS = 0V; TA (°C) = -20 to 85 for LE; -40 to 85 for LI) Read Cycle PARAMETER SYM. MIN. Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change ∗ These parameters are sampled but not 100% tested 5V MAX. 70 70 35 30 30 MIN. 100 15 5 15 3V MAX. 100 100 50 35 35 - UNIT TRC TAA TACS TAOE TCLZ* TOLZ* TCHZ* TOHZ* TOH 70 10 5 10 nS nS nS nS nS nS nS nS nS Write Cycle PARAMETER SYM. MIN. Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write ∗ These parameters are sampled but not 100% tested CS , WE TWC TCW TAW TAS TWP TWR TDW TDH TWHZ* TOHZ* TOW 70 50 50 0 50 0 30 0 5 5V MAX. 25 25 MIN. 100 70 70 0 70 0 50 0 10 3V MAX. 30 30 nS nS nS nS nS nS nS nS nS nS nS UNIT -4- W24258 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH DOUT TAA TOH Read Cycle 2 (Chip Select Controlled) CS TACS TCLZ DOUT TCHZ Read Cycle 3 (Output Enable Controlled) T RC Address T AA OE T AOE T OLZ CS T ACS D OUT TCLZ T CHZ T OHZ T OH -5- Publication Release Date: November 1998 Revision A8 W24258 Timing Waveforms, continued Write Cycle 1 TWC Address T WR OE TCW CS T AW WE TAS TOHZ D OUT T DW D IN TDH (1, 4) T WP Write Cycle 2 ( OE = VIL Fixed) T WC Address TCW CS TAW WE TAS T WP TWHZ (1, 4) TOH (2) TOW (3) TWR D OUT TDW DIN TDH Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24258 DATA RETENTION CHARACTERISTICS (TA (°C) =-20 to 85 for LE; -40 to 85 for LI) PARAMETER VDD for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time * Read Cycle Time SYM. VDR IDDDR TCDR TR TEST CONDITIONS CS ≥ VDD -0.2V CS ≥ VDD -0.2V, VDD = 3V See data retention waveform MIN. 2.0 0 TRC* TYP. MAX. UNIT 2 V µA nS nS DATA RETENTION WAVEFORM VDD 0.9 VDD TCDR CS VIH > CS = V DD - 0.2V VDR > 2V = 0.9 V DD TR VIH ORDERING INFORMATION PART NO. W24258H W24258-70LE W24258S-70LE W24258Q-70LE W24258-70LI W24258S-70LI W24258Q-70LI ACCESS TIME (nS) 100 70/100 70/100 70/100 70/100 70/100 70/100 OPERATING VOLTAGE (V) 3V 5V/3V 5V/3V 5V/3V 5V/3V 5V/3V 5V/3V OPERATING TEMPERATURE (° C) 0 to 70 -20 to 85 -20 to 85 -20 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE Die form 600 mil DIP 330 mil SOP Standard type one TSOP 600 mil DIP 330 mil SOP Standard type one TSOP Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -7- Publication Release Date: November 1998 Revision A8 W24258 BONDING PAD DIAGRAM 6 5 4 3 2 1 28 28 27 S-2 S-1 26 25 24 23 A4 7 A 3 A5 A6 A7 A1 2 A1 4 VDD VDD WE A13 A8 A9 A11 22 OE Y X 21 8 A2 9 A1 10 11 12 13 14 14 S-1 S-2 15 16 17 18 19 A10 20 A0 I/O1 I/O2 I/O3 VSS VSS I/O4 I/O3 I/O6 I/O7 I/O8 CS PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14S-1 14S-2 15 16 17 18 19 20 21 22 23 24 25 26 27 28S-1 28S-2 X -276.73 -421.97 -568.93 -714.17 -861.13 -1006.37 -1190.70 -1190.70 -1023.69 -878.45 -730.05 -584.79 -438.69 -293.69 -152.23 -9.22 437.42 582.68 730.42 875.68 1025.65 1189.20 1188.70 1025.68 878.72 733.48 586.52 441.28 18.40 -131.73 Y 2047.90 2047.90 2047.90 2047.90 2047.90 2047.90 1796.55 -1797.65 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -2049.00 -1797.65 1796.55 2047.90 2047.90 2047.90 2047.90 2047.90 2047.90 2047.90 Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout. -8- W24258 PACKAGE DIMENSIONS 28-pin P-DIP Dimension in Inches Dimension in mm Symbol Min. Nom. Max. 0.210 0.010 0.150 0.016 0.058 0.008 0.155 0.018 0.060 0.010 1.460 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.064 0.014 1.470 0.610 0.550 0.110 0.140 15 0.670 0.090 Min. Nom. Max. 5.33 0.25 3.81 0.41 1.47 0.20 3.94 0.46 1.52 0.25 37.08 14.99 13.72 2.29 3.05 0 16.00 16.51 15.24 13.84 2.54 3.30 4.06 0.56 1.63 0.36 37.34 15.49 13.97 2.79 3.56 15 17.02 2.29 D 28 15 A A1 A2 B B1 c D E E1 e1 L a E1 eA S Notes: 1 14 S E c A A2 A1 Base Plane Seating Plane L B B1 e1 a eA 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 28-pin SOP Wide Body Dimension in Inches Dimension in mm Symbol Min. Nom. Max. 0.112 0.004 0.093 0.014 0.008 0.098 0.016 0.010 0.713 0.326 0.044 0.453 0.028 0.059 0.331 0.050 0.465 0.036 0.067 0.103 0.020 0.014 0.733 0.336 0.056 0.477 0.044 0.075 0.047 0.004 0 10 Min. Nom. Max. 2.85 0.10 2.36 0.36 0.20 2.49 0.41 0.25 18.11 8.28 1.12 11.51 0.71 1.50 8.41 1.27 11.81 0.91 1.70 2.62 0.51 0.36 18.62 8.53 1.42 12.12 1.12 1.91 1.19 0.10 0 10 28 15 e1 E HE θ L Detail F 1 b 14 A A1 A2 b c D E e HE L LE S y θ Notes: D e1 c A2 A 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. S e y A1 LE See Detail F Seating Plane -9- Publication Release Date: November 1998 Revision A8 W24258 Package Dimensions, continued 28-pin Standard Type One TSOP HD Symbol Dimension In Inches Min. Nom. Max. 0.047 0.002 0.035 0.007 0.004 0.461 0.311 0.520 0.040 0.008 0.006 0.465 0.315 0.528 0.022 0.020 0.024 0.010 0.000 0 3 0.004 5 0.028 0.006 0.041 0.011 0.008 0.469 0.319 0.536 Dimension In mm Min. Nom. Max. 1.20 0.05 0.95 0.17 0.10 11.70 7.90 13.20 1.00 0.20 0.15 11.80 8.00 13.40 0.55 0.50 0.60 0.25 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.21 11.90 8.10 13.60 D c 1 e E b A2 A θ A A1 A2 b c D E HD e L L1 Y θ Y L L1 A1 Controlling dimension: Millimeters - 10 - W24258 VERSION HISTORY VERSION A4 A5 A6 A7 A8 DATE Mar. 1997 Jan. 1998 Feb. 1998 Apr. 1998 Nov. 1998 PAGE 8 8 1, 2, 4, 7 3 1, 3, 7, 10 DESCRIPTION Add bonding PAD diagram Modify bonding PAD diagram Delete operating temperature (SL = 0 to 70 °C) Add standby power supply current (ISB1) typical parameter when operation temperature TA = 25° C Deduct reverse type one TSOP package Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 11 - Publication Release Date: November 1998 Revision A8