W24512AJ-25

W24512A 64K × 8 HIGH SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W24512A is a high speed, low power CMOS static RAM organized as 65536 × 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology. FEATURES • • High speed access time: 25 nS (max.) Low power consumption: − Active: 800 mW (max.) Single +5V power supply Fully static operation • • • All inputs and outputs directly TTL compatible Three-state outputs Available packages: 32-pin 300 mil SOJ, 450 mil SOP, and standard type one TSOP (8 mm × 20 mm) • • PIN CONFIGURATIONS BLOCK DIAGRAM V DD NC NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 1 I/O 2 I/O 3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD A15 CS2 WE A13 A8 A9 A11 OE A1 0 CS1 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 V SS A0 . . A15 DECODER CORE ARRAY CS2 CS1 OE WE CONTROL DATA I/O I/O1 . . I/O8 PIN DESCRIPTION SYMBOL A0−A15 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection A11 A9 A8 A13 WE CS2 A15 VDD NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O1−I/O8 CS1 , CS2 WE OE VDD VSS NC 32-pin TSOP -1- Publication Release Date: April 1997 Revision A3 W24512A TRUTH TABLE CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L MODE Not Selected Not Selected Output Disable Read Write I/O1−I/O8 High Z High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 ISB, ISB1 IDD IDD IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 0 to +70 UNIT V V W °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current SYM. VIL VIH ILI ILO TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD CS1 = VIH (min.) or CS2 = VIL (max.) or OE = VIH (min.) or WE = VIL (max.) IOL = +8.0 mA IOH = -4.0 mA CS1 = VIL (max.), CS2 = VIH (min.) I/O = 0mA, Cycle = min Duty = 100% CS1 = VIH (min.) or CS2 = VIL (max.) Cycle = min, Duty = 100% CS1 ≥ VDD -0.2V or CS2 ≤ 0.2V MIN. -0.5 +2.2 -10 -10 TYP. - MAX. +0.8 VDD +0.5 +10 +10 UNIT V V µA µA Output Low Voltage Output High Voltage Operating Power Supply Current VOL VOH IDD 2.4 - - 0.4 160 V V mA Standby Power Supply Current ISB - - 30 mA ISB1 - - 10 mA Note: Typical characteristics are at VDD = 5V, TA = 25° C. -2- W24512A CAPACITANCE (VDD = 5V, TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Input/Output Capacitance SYM. CIN CI/O CONDITIONS VIN = 0V VOUT = 0V MAX. 8 10 UNIT pF pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 5 nS 1.5V CL = 30 pF, IOH/IOL = -4 mA/8 mA CONDITIONS AC Test Loads and Waveform R1 480 ohm R1 480 ohm 5V OUTPUT OUTPUT 30 pF Including Jig and Scope 5V 5 pF R2 255 ohm Including Jig and Scope R2 255 ohm (For TCLZ1, TCLZ2, TOLZ, TCHZ1,TCHZ2, TOHZ, TWHZ, TOW ) 3.0V 90% 10% 5 nS 10% 90% 0V 5 nS -3- Publication Release Date: April 1997 Revision A3 W24512A AC Characteristics,continued (VDD = 5V ±10%, VSS = 0V, TA = 0 to 70° C) Read Cycle PARAMETER Read Cycle Time Address Access Time Chip Select Access Time CS1 CS2 Output Enable to Output Valid Chip Selection to Output in Low Z CS1 CS2 Output Enable to Output in Low Z Chip Deselection to Output in High Z CS1 CS2 Output Disable to Output in High Z Output Hold from Address Change * These parameters are sampled but not 100% tested. SYM. TRC TAA TACS1 TACS2 TAOE TCLZ1* TCLZ2* TOLZ* TCHZ1* TCHZ2* TOHZ* TOH W24512A-25 MIN. 25 3 3 0 3 MAX. 25 25 25 12 12 12 12 nS nS nS nS nS nS nS nS nS nS nS nS UNIT Write Cycle PARAMETER Write Cycle Time Chip Selection to End of Write CS1 CS2 Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time CS1 , WE CS2 Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write * These parameters are sampled but not 100% tested. -4SYM. TWC TCW1 TCW2 TAW TAS TWP TWR1 TWR2 TDW TDH TWHZ* TOHZ* TOW W24512A-25 MIN. 25 18 18 18 0 15 0 0 12 0 0 MAX. 12 12 nS nS nS nS nS nS nS nS nS nS nS nS nS UNIT W24512A TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TAA TOH TOH D OUT Read Cycle 2 (Chip Select Controlled) CS1 TACS1 CS2 TACS2 TCHZ2 TCHZ1 TCLZ1 D OU TCLZ2 Read Cycle 3 (Output Enable Controlled) TRC Address TAA OE TAOE TOLZ CS1 TACS1 TCLZ1 CS2 T ACS2 TCLZ2 D OUT TCHZ2 TOHZ TCHZ1 TOH -5- Publication Release Date: April 1997 Revision A3 W24512A Timing Waveforms, continued Write Cycle 1 (OE Clock) T WC Address TWR1 OE TCW1 CS1 CS2 TAW WE TAS TOHZ D OUT (1, 4) TCW2 TWR2 TWP TDW D IN TDH Write Cycle 2 (OE = VIL Fixed) TWC Address TCW1 CS1 TWR1 CS2 TAW WE TAS TCW2 TWR2 T WP TWHZ (1, 4) TOH TOW TDH (2) (3) D OUT TDW D IN Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24512A ORDERING INFORMATION PART NO. ACCESS TIME (nS) 25 25 25 OPERATING CURRENT MAX. (mA) 160 160 160 STANDBY CURRENT MAX. (mA) 10 10 10 PACKAGE W24512AS-25 W24512AT-25 W24512AJ-25 Notes: 450 mil SOP Standard type one TSOP 300 mil SOJ 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -7- Publication Release Date: April 1997 Revision A3 W24512A PACKAGE DIMENSIONS 32-pin SO Wide Body Symbol 32 17 Dimension in Inches Dimension in mm Min. 0.004 0.101 0.014 0.006 Nom. Max. 0.118 Min. 0.10 Nom. Max. 3.00 e1 EH E L Detail F 1 16 b A A1 A2 b c D E e HE L LE S y θ Notes: 0.106 0.016 0.008 0.805 0.111 0.020 0.012 0.817 0.450 0.056 0.556 0.039 0.063 0.036 0.004 2.57 0.36 0.15 2.69 0.41 0.20 20.45 2.82 0.51 0.31 20.75 11.43 1.42 14.38 0.99 1.60 0.91 0.10 0.440 0.044 0.546 0.023 0.047 0.445 0.050 0.556 0.031 0.055 11.18 1.12 13.87 0.58 1.19 11.30 1.27 14.12 0.79 1.40 0 10 0 10 D e1 c A 2 A 1 S y e A LE 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch and are determined .at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. Seating Plane See Detail F 32-pin SOJ Dimension in Inches Dimension in mm Min. __ 0.020 0.095 0.026 0.016 0.008 0.815 0.295 0.044 0.247 0.325 0.080 __ __ 0 32 17 Symbol A A1 A2 E He Nom. Max. __ __ 0.100 0.028 0.018 0.010 0.825 0.300 0.050 0.267 0.335 __ __ __ __ 0.140 __ 0.105 0.032 0.022 0.014 0.835 0.305 0.056 0.287 0.345 __ 0.045 0.004 10 Min. __ 0.508 2.413 0.660 0.406 0.203 20.701 7.493 1.118 6.274 8.255 2.032 __ __ 0° Nom. Max. __ __ 2.540 0.711 0.457 0.254 20.955 7.620 1.270 6.782 8.509 __ __ __ __ 3.556 __ 2.667 0.813 0.559 0.356 21.209 7.747 1.422 7.290 8.763 __ 1.143 0.102 10° B b c D E e e1 1 16 He L S Y θ D A2 A c L S B b e1 e A1 θ Seating Plane Y -8- W24512A Package Dimensions, continued 32-pin Standard Type One TSOP HD Symbol Dimension in Inches Min. Nom. Max. 0.047 0.006 0.041 0.009 0.007 Dimension in mm Min. Nom. Max. 1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20 D c A A1 A2 b __ 0.002 0.037 0.007 __ __ 0.039 0.008 __ 0.05 0.95 0.17 0.12 __ __ 1.00 0.20 0.15 M e E c D E HD e L L1 0.005 0.006 0.720 0.311 0.780 0.724 0.315 0.787 0.020 0.020 0.031 0.10(0.004) 0.728 18.30 18.40 0.319 7.90 8.00 20.00 0.50 0.50 0.80 b 0.795 19.80 __ 0.016 __ 0.024 __ 0.40 __ 0.60 __ 0.000 1 __ 0.004 5 __ 0.00 1 __ 0.10 5 A A2 θ L L1 A1 Y Y __ 3 __ 3 θ Controlling dimension: Millimeter -9- Publication Release Date: April 1997 Revision A3 W24512A Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792647 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 1-408-9436666 Voice & Fax-on-demand: 886-2-7197006 FAX: 1-408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 10 -