W24LH8

W24LH8 32K × 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24LH8 is a normal speed, very low power CMOS static RAM organized as 32768 × 8 bits that operates on a wide voltage range from 2.7V to 5.5V power supply. The W24LH8 family, W24LH8-55LE and W24LH8-55LI, can meet requirement of various operating temperature. This device is manufactured using Winbond's high performance CMOS technology. FEATURES • • • • • Low power consumption Access time: 55 nS (5V ±10%), 100 nS (3V ±10%) 2.7V to 5.5V supply voltage Fully static operation All inputs and outputs directly TTL compatible • Three-state outputs • Battery back-up operation capability • Data retention voltage: 2V (min.) • Available packages: 330 mil SOP and standard type one TSOP (8 mm × 13.4 mm) PIN CONFIGURATIONS BLOCK DIAGRAM CLK GEN. A12 A14 PRECHARGE CKT. A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin SOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD #WE A13 A8 A9 A11 #OE A10 #CS I/O8 I/O7 I/O6 I/O5 I/O4 A2 A3 A4 A5 A6 A7 A13 I/O1 I/O8 R O W D E C O D E R CORE CELL ARRAY 512 ROWS 64 X 8 COLUMNS DATA CNTRL. CLK GEN. I/O CKT. COLUMN DECODER #WE #CS #OE A11 A10 A1 A0 A8 A9 PIN DESCRIPTION #OE A11 A9 A8 A13 #WE VDD A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 #CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 SYMBOL A0−A14 I/O1−I/O8 #CS #WE #OE VDD VSS DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground 28-pin TSOP -1- Publication Release Date: March 2001 Revision A3 W24LH8 TRUTH TABLE #CS H L L L #OE X H L X #WE X H H L MODE Not Selected Output Disable Read Write I/O1− I/O8 High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 IDD IDD IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature LE LI RATING -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 -20 to 85 -40 to 85 UNIT V V W °C °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VSS = 0V; TA (°C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current SYM. VIL VIH ILI ILO TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, #CS = VIH (min.) or #OE = VIH (min.) or #WE = VIL (max.) IOL = +2.1 mA IOH = -1.0 mA MIN. -0.5 +2.0 -1 -1 MAX. +0.6 VDD +0.5 +1 +1 UNIT V V µA µA Output Low Voltage Output High Voltage VOL VOH 2.2 0.4 - V V -2- W24LH8 Operating Characteristics, continued PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT Operating Power Supply Current Standby Power Supply Current IDD ISB ISB1 #CS = VIL (max.), I/O = 0 mA, Cycle = min. Duty = 100% #CS = VIH (min.), Cycle = min. Duty = 100% #CS ≥ VDD -0.2V 5V 3V - 0.5 70 40 1 5 mA mA µA Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V/ 3V. CAPACITANCE (TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Input/Output Capacitance SYM. CIN CI/O CONDITIONS VIN = 0V VOUT = 0V MAX. 6 8 UNIT pF pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 2.4V 5 nS 1.5V See the drawing below CONDITIONS AC Test Loads and Waveform 1 TTL OUTPUT 100 pF Including Jig and Scope , 1 TTL OUTPUT 5 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ TOHZ, TWHZ, TOW ) 2.4V 0V 5 nS 90% 10% 90% 10% 5 nS -3- Publication Release Date: March 2001 Revision A3 W24LH8 AC Characteristics, continued (VSS = 0V; TA (°C) = -20 to 85 for LE; -40 to 85 for LI) Read Cycle PARAMETER SYMBOL 3V ± 10% MIN. Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change ∗ These parameters are sampled but not 100% tested 5V ± 10% MIN. 55 10 5 10 MAX. 55 55 30 20 20 - UNIT MAX. 100 100 50 35 35 - TRC TAA TACS TAOE TCLZ* TOLZ* TCHZ* TOHZ* TOH 100 15 5 15 nS nS nS nS nS nS nS nS nS Write Cycle PARAMETER SYMBOL 3V ± 10% MIN. Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time #CS, #WE Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write ∗ These parameters are sampled but not 100% tested TWC TCW TAW TAS TWP TWR TDW TDH TWHZ* TOHZ* TOW 100 80 80 0 70 0 40 0 5 MAX. 35 35 5V ± 10% MIN. 55 40 40 0 30 0 25 0 5 MAX. 20 20 nS nS nS nS nS nS nS nS nS nS nS UNIT -4- W24LH8 TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TRC Address TOH DOUT TAA TOH Read Cycle 2 (Chip Select Controlled) #CS TACS TCLZ DOUT TCHZ Read Cycle 3 (Output Enable Controlled) T RC Address T AA #OE T AOE T OLZ #CS T ACS D OUT TCLZ T CHZ T OHZ TOH -5- Publication Release Date: March 2001 Revision A3 W24LH8 Timing Waveforms, continued Write Cycle 1 TWC Address T WR #OE T CW #CS T AW #WE TAS TOHZ D OUT T DW D IN TDH (1, 4) T WP Write Cycle 2 (#OE = VIL Fixed) T WC Address TCW #CS TAW #WE TAS TWP TWHZ (1, 4) TOH (2) TOW (3) TWR D OUT TDW DIN TDH Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested. -6- W24LH8 DATA RETENTION CHARACTERISTICS (TA (°C) = -20 to 85 for LE; -40 to 85 for LI) PARAMETER VDD for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time * Read Cycle Time SYM. VDR IDDDR TCDR TR TEST CONDITIONS #CS ≥ VDD -0.2V #CS ≥ VDD -0.2V, VDD = 3V See data retention waveform MIN. 2.0 0 TRC* TYP. - MAX. UNIT 5 V µA nS nS DATA RETENTION WAVEFORM VDD 0.9 V DD TCDR VDR > 2V = 0.9 V DD TR #CS VIH #CS > V DD - 0.2V = VIH -7- Publication Release Date: March 2001 Revision A3 W24LH8 ORDERING INFORMATION PART NO. ACCESS TIME (nS) 55 100 W24LH8Q-55LE 55 100 W24LH8S-55LI 55 100 W24LH8Q-55LI 55 100 OPERATING VOLTAGE (V) 4.5V to 5.5V 2.7V to 3.3V 4.5V to 5.5V 2.7V to 3.3V 4.5V to 5.5V 2.7V to 3.3V 4.5V to 5.5V 2.7V to 3.3V OPERATING TEMPERATURE (° C) -20 to 85 -20 to 85 -20 to 85 -20 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 Standard type one TSOP Standard type one TSOP 330 mil SOP PACKAGE W24LH8S-55LE 330 mil SOP Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. -8- W24LH8 PACKAGE DIMENSIONS 28-pin SOP Wide Body Dimension in Inches Dimension in mm Symbol Min. Nom. Max. 0.112 0.004 0.093 0.014 0.008 0.098 0.016 0.010 0.713 0.326 0.044 0.453 0.028 0.059 0.331 0.050 0.465 0.036 0.067 0.103 0.020 0.014 0.733 0.336 0.056 0.477 0.044 0.075 0.047 0.004 0 10 Min. Nom. Max. 2.85 0.10 2.36 0.36 0.20 2.49 0.41 0.25 18.11 8.28 1.12 11.51 0.71 1.50 8.41 1.27 11.81 0.91 1.70 2.62 0.51 0.36 18.62 8.53 1.42 12.12 1.12 1.91 1.19 0.10 0 10 28 15 e1 E HE θ L Detail F 1 b 14 A A1 A2 b c D E e HE L LE S y θ Notes: D e1 c A2 A 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. S e y A1 LE See Detail F Seating Plane 28-pin Standard Type One TSOP HD Symbol Dimension In Inches Min. Nom. Max. 0.047 0.002 0.035 0.007 0.004 0.461 0.311 0.520 0.040 0.008 0.006 0.465 0.315 0.528 0.022 0.020 0.024 0.010 0.000 0 3 0.004 5 0.028 0.006 0.041 0.011 0.008 0.469 0.319 0.536 Dimension In mm Min. Nom. Max. 1.20 0.05 0.95 0.17 0.10 11.70 7.90 13.20 1.00 0.20 0.15 11.80 8.00 13.40 0.55 0.50 0.60 0.25 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.21 11.90 8.10 13.60 D c 1 e E b A2 A θ A A1 A2 b c D E HD e L L1 Y θ L L1 A1 Controlling dimension: Millimeters Y -9- Publication Release Date: March 2001 Revision A3 W24LH8 VERSION HISTORY VERSION A1 A2 DATE Nov. 1998 Jan. 1999 PAGE 1 3 A3 Mar. 2001 1 Initial Issued Change low power consumption active: from 108 to 156 mW (max.) Change operating power supply current (IDD) from 30 to 40 mA (max.) Change operating power supply voltage from (2.7V to 3.6V) to (2.7V to 5.5V), access time from 70 nS to (55 nS (5V ±10%), 100 nS (3V ±10%)), and remove 28-pin 600 mil DIP package. Change operating power supply current (IDD) from 40 mA to (70 mA/5V, 40 mA/3V)(max.) Add 55 nS (5V ±10%) spec. and change 3V ±10% spec. from 70 nS to 100 nS. Delete SL grade Correct Ordering Information DESCRIPTION 3 4 2, 4, 7, 8 8 Headquarters Headquarters Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852 -27513100 TEL: 886-3-5770066 FAX: 852 -27552064 FAX: 886 -3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886 -2-27197502 Note: All data and specifications are subject to change withou t notice. - 10 -