W25N01JWxxxG/T
1.8V 1G-BIT
SERIAL SLC NAND FLASH MEMORY
DUAL/QUAD SPI WITH 166MHZ STR & 80MHZ DTR
BUFFER READ & CONTINUOUS READ
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
Table of Contents
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTIONS ....................................................................................................... 6
FEATURES ................................................................................................................................. 6
PACKAGE TYPES AND PIN CONFIGURATIONS .................................................................... 7
3.1
Pad Configuration WSON 8x6-mm ................................................................................ 7
3.2
Pad Description WSON 8x6-mm .................................................................................... 7
3.3
Pin Configuration SOIC 300-mil ..................................................................................... 8
3.4
Pin Description SOIC 300-mil ......................................................................................... 8
3.5
Ball Configuration TFBGA 8x6-mm (5x5-1 Ball Array) ................................................... 9
3.6
Ball Description TFBGA 8x6-mm ................................................................................... 9
PIN DESCRIPTIONS ................................................................................................................ 10
4.1
Chip Select (/CS) .......................................................................................................... 10
4.2
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ............................ 10
4.3
Write Protect (/WP)....................................................................................................... 10
4.4
HOLD (/HOLD) ............................................................................................................. 10
4.5
Serial Clock (CLK) ........................................................................................................ 10
4.6
Reset (/RESET) ............................................................................................................ 10
BLOCK DIAGRAM .................................................................................................................... 11
FUNCTIONAL DESCRIPTIONS ............................................................................................... 12
6.1
Device Operation Flow ................................................................................................. 12
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
7.
Standard SPI Instructions .............................................................................................. 12
Dual SPI Instructions...................................................................................................... 12
Quad SPI Instructions .................................................................................................... 13
DTR Read Instructions ................................................................................................... 13
Hold Function ................................................................................................................. 13
Software Reset .............................................................................................................. 13
Hardware Reset ............................................................................................................. 14
6.2
Write Protection ............................................................................................................ 14
6.3
DLP (Data Learning Pattern) ........................................................................................ 15
6.4
Interface States ............................................................................................................ 16
PROTECTION, CONFIGURATION AND STATUS REGISTERS ............................................ 17
7.1
Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ................... 17
7.1.1
7.1.2
7.1.3
7.2
Configuration Register / Status Register-2 (Volatile Writable) ..................................... 19
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3
Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable ........... 17
Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable .......................... 18
Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable .............. 18
One Time Program Lock Bit (OTP-L) – OTP lockable.................................................... 19
Enter OTP Access Mode Bit (OTP-E) – Volatile Writable .............................................. 19
Status Register-1 Lock Bit (SR1-L) – OTP lockable ....................................................... 19
ECC Enable Bit (ECC-E) – Volatile Writable .................................................................. 20
Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable .............................. 21
Quad Enable (QE) – Volatile Writable ............................................................................ 21
Status Register-3 (Status only) .................................................................................... 22
7.3.1
7.3.2
Look-Up Table Full (LUT-F) – Status Only ..................................................................... 22
Cumulative ECC Status (ECC-1, ECC-0) – Status Only ................................................ 22
-1-
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.3.3
7.3.4
7.3.5
7.3.6
7.4
Status Register-4 (Writable and Status) ....................................................................... 24
7.4.1
7.4.2
7.4.3
8.
Program Failure (P-FAIL) – Status Only ........................................................................ 23
Erase Failure (E-FAIL) – Status Only ............................................................................. 23
Write Enable Latch (WEL) – Status Only ....................................................................... 23
Read/Erase/Program in Progress (BUSY) – Status Only ............................................... 23
Output Driver Strength (ODS1, ODS0) – Volatile Writable............................................. 24
Data Learning Pattern Enable (DLP-E) – Volatile Writable ............................................ 24
High Speed Enable (HS) – Volatile Writable .................................................................. 24
7.5
Extended Register ........................................................................................................ 25
7.6
W25N01JW Status Register Memory Protection ......................................................... 26
INSTRUCTIONS ....................................................................................................................... 27
8.1
Device ID and Instruction Set Tables ........................................................................... 27
8.1.1
8.1.2
8.1.3
8.2
Manufacturer and Device Identification .......................................................................... 27
Instruction Set Table 1 (Continuous Read, BUF = 0, xxxT Default Power Up Mode) (11) 28
Instruction Set Table 2 (Buffer Read, BUF = 1, xxxG Default Power Up Mode) (12) ........ 30
Instruction Descriptions ................................................................................................ 33
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.2.16
8.2.17
8.2.18
8.2.19
8.2.20
8.2.21
8.2.22
8.2.23
8.2.24
8.2.25
8.2.26
8.2.27
8.2.28
8.2.29
8.2.30
8.2.31
8.2.32
Device Reset (FFh), Enable Reset (66h) and Reset Device (99h) ................................. 33
Read JEDEC ID (9Fh).................................................................................................... 35
Read Status Register (0Fh / 05h) .................................................................................. 36
Write Status Register (1Fh / 01h) ................................................................................... 37
Write Data Learning Pattern (4Ah) ................................................................................. 37
Write Enable (06h) ......................................................................................................... 38
Write Disable (04h) ........................................................................................................ 38
Bad Block Management (A1h) ....................................................................................... 39
Read BBM Look Up Table (A5h) .................................................................................... 40
Last ECC Failure Page Address (A9h)......................................................................... 41
Deep Power-down (B9h) .............................................................................................. 42
Release Deep Power-down (ABh) ............................................................................... 43
128KB Block Erase (D8h) ............................................................................................ 44
Load Program Data (02h) / Random Load Program Data (84h) .................................. 45
Quad Load Program Data (32h) / Quad Random Load Program Data (34h) ............... 46
Program Execute (10h) ................................................................................................ 47
Page Data Read (13h) ................................................................................................. 48
Read Data (03h) .......................................................................................................... 49
Fast Read (0Bh) ........................................................................................................... 50
Fast Read with 4-Byte Address (0Ch) .......................................................................... 51
Fast Read Dual Output (3Bh)....................................................................................... 52
Fast Read Dual Output with 4-Byte Address (3Ch) ...................................................... 53
Fast Read Quad Output (6Bh) ..................................................................................... 54
Fast Read Quad Output with 4-Byte Address (6Ch) .................................................... 55
Fast Read Dual I/O (BBh) ............................................................................................ 56
Fast Read Dual I/O with 4-Byte Address (BCh) ........................................................... 57
Fast Read Quad I/O (EBh) ........................................................................................... 58
Fast Read Quad I/O with 4-Byte Address (ECh) .......................................................... 60
DTR Fast Read (0Dh) .................................................................................................. 62
DTR Fast Read with 4-Byte Address (0Eh).................................................................. 63
DTR Fast Read Dual Output (3Dh) .............................................................................. 64
DTR Fast Read Quad Output (6Dh) ............................................................................. 65
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Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.33
8.2.34
8.2.35
8.2.36
8.2.37
8.2.38
9.
10.
11.
12.
13.
DTR Fast Read Dual I/O (BDh) .................................................................................... 67
DTR Fast Read Dual I/O with 4-Byte Address (BEh) ................................................... 68
DTR Fast Read Quad I/O (EDh) .................................................................................. 69
DTR Fast Read Quad I/O with 4-Byte Address (EEh) .................................................. 70
Accessing Unique ID / Parameter / OTP Pages (OTP-E=1) ........................................ 72
Parameter Page Data Definitions ................................................................................. 73
ELECTRICAL CHARACTERISTICS......................................................................................... 74
9.1
Absolute Maximum Ratings .......................................................................................... 74
9.2
Operating Ranges ........................................................................................................ 74
9.3
Power-up Power-down Timing Requirements .............................................................. 75
9.4
DC Electrical Characteristics ........................................................................................ 76
9.5
AC Measurement Conditions ....................................................................................... 77
9.6
AC Electrical Characteristics ........................................................................................ 78
9.7
Serial Output Timing ..................................................................................................... 80
9.8
Serial Input Timing........................................................................................................ 80
9.9
/HOLD Timing ............................................................................................................... 81
9.10 /WP Timing ................................................................................................................... 81
INVALID BLOCK MANAGEMENT ............................................................................................ 82
10.1 Invalid Blocks................................................................................................................ 82
10.2 Initial Invalid Blocks ...................................................................................................... 82
10.3 Error in Operation ......................................................................................................... 83
10.4 Addressing in Program Operation ................................................................................ 83
PACKAGE SPECIFICATIONS ................................................................................................. 84
11.1 8-Pad WSON 8x6-mm (Package Code ZE) ................................................................. 84
11.2 16-Pin SOIC 300mil (Package Code SF) ..................................................................... 85
11.3 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array) ................................... 86
ORDERING INFORMATION .................................................................................................... 87
12.1 Valid Part Numbers and Top Side Marking .................................................................. 88
REVISION HISTORY ................................................................................................................ 89
-3-
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
List of Figures
Figure 3-1 W25N01JW Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE) ........................ 7
Figure 3-2 W25N01JW Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) ............................ 8
Figure 3-3 W25N01JW Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB) ...................... 9
Figure 5-1 W25N01JW Flash Memory Architecture and Addressing ................................................... 11
Figure 6-1 W25N01JW Flash Memory Operation Diagram .................................................................. 12
Figure 6-2 DLP (Data Learning Pattern) output example in DTR Fast Read Quad I/O (BUF=1) ......... 15
Figure 7-1 Protection Register / Status Register-1 (Address Axh) ....................................................... 17
Figure 7-2 Configuration Register / Status Register-2 (Address Bxh) .................................................. 19
Figure 7-3 Status Register-3 (Address Cxh) ......................................................................................... 22
Figure 7-4 Status Register-4 (Address Dxh) ......................................................................................... 24
Figure 7-5 Extended Register ............................................................................................................... 25
Figure 8-1 Device Reset Instruction (FFh) ............................................................................................ 33
Figure 8-2 Device Reset Instruction (66h+99h) .................................................................................... 33
Figure 8-3 Read JEDEC ID Instruction ................................................................................................. 35
Figure 8-4 Read Status Register Instruction ......................................................................................... 36
Figure 8-5 Write Status Register-1/2/3 Instruction ................................................................................ 37
Figure 8-6 Write Data Learning Pattern ................................................................................................ 37
Figure 8-7 Write Enable Instruction ...................................................................................................... 38
Figure 8-8 Write Disable Instruction ...................................................................................................... 38
Figure 8-9 Bad Block Management Instruction ..................................................................................... 39
Figure 8-10 Read BBM Look Up Table Instruction ............................................................................... 40
Figure 8-11 Last ECC Failure Page Address Instruction ...................................................................... 41
Figure 8-12 Deep Power-down Instruction ........................................................................................... 42
Figure 8-13 Release Deep Power-down Instruction ............................................................................. 43
Figure 8-14 128KB Block Erase Instruction .......................................................................................... 44
Figure 8-15 Load / Random Load Program Data Instruction ................................................................ 45
Figure 8-16 Quad Load / Quad Random Load Program Data Instruction ............................................ 46
Figure 8-17 Program Execute Instruction ............................................................................................. 47
Figure 8-18 Page Data Read Instruction .............................................................................................. 48
Figure 8-19 Read Data Instruction (Buffer Read Mode, BUF=1) .......................................................... 49
Figure 8-20 Read Data Instruction (Continuous Read Mode, BUF=0) ................................................. 49
Figure 8-21 Fast Read Instruction (Buffer Read Mode, BUF=1) .......................................................... 50
Figure 8-22 Fast Read Instruction (Continuous Read Mode, BUF=0) .................................................. 50
Figure 8-23 Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ......................... 51
Figure 8-24 Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ................ 51
Figure 8-25 Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1) ...................................... 52
Figure 8-26 Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0) ............................. 52
Figure 8-27 Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ..... 53
Figure 8-28 Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
....................................................................................................................................................... 53
Figure 8-29 Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) .................................... 54
Figure 8-30 Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0) ............................ 54
Figure 8-31 Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ... 55
-4-
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
Figure 8-32 Fast Read Quad Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
....................................................................................................................................................... 55
Figure 8-33 Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1) ............................................ 56
Figure 8-34 Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0) ................................... 56
Figure 8-35 Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ........... 57
Figure 8-36 Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) .. 57
Figure 8-37 Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1) ........................................... 58
Figure 8-38 Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0) .................................. 59
Figure 8-39 Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ......... 60
Figure 8-40 Fast Read Quad I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) . 61
Figure 8-41 DTR Fast Read Instruction (Buffer Read Mode, BUF=1) .................................................. 62
Figure 8-42 DTR Fast Read Instruction (Continuous Read Mode, BUF=0) ......................................... 62
Figure 8-43 DTR Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................. 63
Figure 8-44 DTR Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ........ 63
Figure 8-45 DTR Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1) ............................. 64
Figure 8-46 DTR Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0) ..................... 64
Figure 8-47 DTR Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) ............................ 65
Figure 8-48 DTR Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0) ................... 66
Figure 8-49 DTR Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1) ................................... 67
Figure 8-50 DTR Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0) ........................... 67
Figure 8-51 DTR Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) .. 68
Figure 8-52 DTR Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
....................................................................................................................................................... 68
Figure 8-53 DTR Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1) .................................. 69
Figure 8-54 DTR Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0) ......................... 69
Figure 8-55 DTR Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) . 70
Figure 8-56 DTR Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0) ......................... 71
Figure 9-1 Power-up Power-down Timing and Voltage Levels ............................................................. 75
Figure 9-2 Power-up, Power-Down Requirement ................................................................................. 75
Figure 9-3 AC Measurement I/O Waveform ......................................................................................... 77
Figure 9-4 Serial Output Timing (STR) ................................................................................................. 80
Figure 9-5 Serial Output Timing (DTR) ................................................................................................. 80
Figure 9-6 Serial Input Timing (STR) .................................................................................................... 80
Figure 9-7 Serial Input Timing (DTR) .................................................................................................... 80
Figure 9-8 /HOLD Timing ...................................................................................................................... 81
Figure 9-9 /WP Timing .......................................................................................................................... 81
Figure 10-1 Flow Chart of Create Initial Invalid Block Table ................................................................. 82
Figure 10-2 Bad Block Replacement .................................................................................................... 83
Figure 11-1 8-Pad WSON 8x6-mm (Package Code ZE) ...................................................................... 84
Figure 11-2 16-Pin SOIC 300mil (Package Code SF) .......................................................................... 85
Figure 11-3 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array) ........................................ 86
-5-
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
1. GENERAL DESCRIPTIONS
The W25N01JW (1G-bit) Serial SLC NAND Flash Memory provides a storage solution for systems with
limited space, pins and power. The W25N SpiFlash family incorporates the popular SPI interface and
the traditional large NAND non-volatile memory space. The device operates on a single 1.70V to 1.95V
power supply with current consumption as low as 25mA active and 10µA for standby. All W25N SpiFlash
family devices are offered in space-saving packages which were impossible to use in the past for the
typical NAND flash memory.
The W25N01JW 1G-bit memory array is organized into 65,536 programmable pages of 2,048-Byte
each. The entire page can be programmed at one time using the data from the 2,048-Byte internal
buffer. Pages can be erased in groups of 64 (128KB block erase). The W25N01JW has 1,024 erasable
blocks.
The W25N01JW supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial
Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock
frequencies of up to 166MHz are supported allowing equivalent clock rates of 332MHz (166MHz x 2)
for Dual I/O and 664MHz (166MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O
instructions. The W25N01JW adds support for DTR (Double Transfer Rate) commands that transfer
addresses and read data on both edges of the clock.
The W25N01JW provides a new Continuous Read Mode that allows for efficient access to the entire
memory array with a single Read command. This feature is ideal for code shadowing applications.
A Hold pin, Write Protect pin and programmable write protection, provide further control flexibility.
Additionally, the device supports JEDEC standard manufacturer and device ID, Unique ID page,
parameter page and ten 2,048-Byte OTP pages. To provide better NAND flash memory manageability,
user configurable internal ECC, Bad block management are also available in W25N01JW.
2. FEATURES
New W25N Family of SpiFlash Memories
– W25N01JW: 1G-bit / 128M-Byte
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold,
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Compatible SPI Serial Flash commands
Highest Performance Serial NAND Flash
– 166MHz Standard/Dual/Quad SPI clocks
– 332/664MHz equivalent Dual/Quad SPI
– DTR (Dual Transfer Rate) up to 80MHz
– 80MB/s continuous data transfer rate
– Fast Program/Erase performance
– 100,000 erase/program cycles
– 10-year data retention
Efficient “Continuous Read Mode”(1)
– Alternative method to the Buffer Read Mode
– No need to issue “Page Data Read” between
Read commands
– Allows direct read access to the entire array
Low Power, Wide Temperature Range
– Single 1.70 to 1.95V power supply
– 25mA active, 10µA standby current
– -40°C to +85/+105°C operating range
Flexible Architecture with 128KB blocks
– Uniform 128K-Byte Block Erase
– Flexible page data load methods
Advanced Features
– On-chip 1-Bit ECC for memory array
– ECC status bits indicate ECC results
– Bad Block Management and LUT(2) access
– Software and Hardware Write-Protect
– Power Supply Lock-Down and OTP protection
– Unique ID and Parameter page(3)
– Ten 2KB OTP pages(4)
Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 16-pin SOIC-300mil
– 24-ball TFBGA 8x6-mm
– Contact Winbond for other package options
Notes:
1.
2.
3.
4.
5.
-6-
Only the Read command structures are different between
the “Continuous Read Mode (BUF=0)” and the “Buffer Read
Mode (BUF=1)”, all other commands are identical
W25N01JWxxxG: Default BUF=1 after power up
W25N01JWxxxT: Default BUF=0 after power up
LUT stands for Look-Up Table
Please refer to 8.2.38 and 8.2.39 for detail information
OTP pages can only be programmed
Endurance specification is based on the on-chip ECC or
1bit/528 byte ECC(Error Correcting Code)
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W25N01JW is offered in an 8-pad WSON 8x6-mm (package code ZE), 160pin SOIC-300mil (package
code SF), and 24-ball 8x6-mm TFBGA (package code TB) packages as shown in Figure 3-1, 3-2 and
3-3 respectively. Package diagrams and dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
Top View
/CS
1
8
VCC
DO (IO1)
2
7
/HOLD (IO3)
/WP (IO2)
3
6
CLK
GND
4
5
DI (IO0)
Figure 3-1 W25N01JW Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE)
3.2
Pad Description WSON 8x6-mm
PAD NO.
PAD NAME
I/O
FUNCTION
1
/CS
I
2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
3
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2)(2)
4
GND
5
DI (IO0)
Chip Select Input
Ground
I/O
6
CLK
I
7
/HOLD (IO3)
I/O
8
VCC
Data Input (Data Input Output 0)(1)
Serial Clock Input
Hold Input (Data Input Output 3)(2)
Power Supply
Notes:
1.
2.
IO0 and IO1 are used for Standard and Dual SPI instructions
IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
-7-
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
3.3 Pin Configuration SOIC 300-mil
Figure 3-2 W25N01JW Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
3.4
Pin Description SOIC 300-mil
PIN NO.
PIN NAME
I/O
FUNCTION
1
/HOLD (IO3)
I/O
2
VCC
3
/RESET
4
N/C
No Connect
5
N/C
No Connect
6
N/C
7
/CS
I
8
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
9
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2)(2)
10
GND
Ground
11
N/C
No Connect
12
N/C
No Connect
13
N/C
No Connect
14
N/C
No Connect
15
DI (IO0)
I/O
16
CLK
I
Hold Input (Data Input Output 3)(2)
Power Supply
I
Reset Input(3)
No Connect
Chip Select Input
Data Input (Data Input Output 0)(1)
Serial Clock Input
Notes:
1.
2.
3.
IO0 and IO1 are used for Standard and Dual SPI instructions
IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
The /RESET pin on SOIC-16 package is a dedicated hardware reset pin.
-8-
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
3.5
Ball Configuration TFBGA 8x6-mm (5x5-1 Ball Array)
Top View
Package Code TB
Figure 3-3 W25N01JW Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB)
3.6
Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
I/O
FUNCTION
A4
/RESET
I
Reset Input
B2
CLK
I
Serial Clock Input
B3
GND
Ground
B4
VCC
Power Supply
C2
/CS
I
C4
/WP (IO2)
I/O
Write Protect Input (Data Input Output 2)(2)
D2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
D3
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
D4
/HOLD (IO3)
I/O
Hold Input (Data Input Output 3)(2)
Multiple
NC
Chip Select Input
No Connect
Notes:
1.
2.
3.
IO0 and IO1 are used for Standard and Dual SPI instructions
IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
The /RESET pin on TFBGA 24 package is a dedicated hardware reset pin.
-9-
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program
or write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, /CS must transition from high to low before a new instruction will be accepted.
The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection”
and “Power-up Power-down Timing Requirements”). If needed, a pull-up resistor on the /CS pin can be
used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25N01JW supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output)
to read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect bits BP[3:0] and Status Register Protect SRP bits
SRP[1:0], a portion as small as 256K-Byte (2x128KB blocks) or up to the entire memory array can be
hardware protected. The WP-E bit in the Protection Register (SR-1) controls the functions of the /WP
pin. When QE=1, the /WP pin function is not available since this pin is used for IO2.
When WP-E=0, the device is in the Software Protection mode that only SR-1 can be protected. The
/WP pin functions as a data I/O pin for the Quad SPI operations, as well as an active low input pin for
the Write Protection function for SR-1. Refer to section 7.1.3 for detail information.
When WP-E=1, the device is in the Hardware Protection mode that /WP becomes a dedicated active
low input pin for the Write Protection of the entire device. If /WP is tied to GND, all “Write/Program/Erase”
functions are disabled. The entire device (including all registers, memory array and OTP pages) will
become read-only. Quad SPI read operations are also disabled when WP-E is set to 1.
4.4 HOLD (/HOLD)
During Standard and Dual SPI operations, the /HOLD pin allows the device to be paused while it is
actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance
and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device
operation can resume. The /HOLD function can be useful when multiple devices are sharing the same
SPI signals. The /HOLD pin is active low. When QE=1 or DTR operation is enabled, the /HOLD pin
function is not available since this pin is used for IO3. The system has to drive high to /HOLD (IO3), or
has to put an external pull-up resistor on the PCB.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.
4.6 Reset (/RESET)
The /RESET pin allows the device to be reset by the controller, and provides hardware level resetting.
This is highest priority among all the input signals. The /RESET pin is adopted on SOIC and TFBGA24
package types.
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Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
5. BLOCK DIAGRAM
2,112 Bytes
Column Address CA[11:0]
64
Byte
Data Buffer (2,048 Byte)
1,024 Blocks X 64 Pages
(65,536 Pages)
Page Address PA[15:0]
Main Array
64 X
64B
Block (64 Pages, 64 X 2KB)
Address Bits
Page Address (PA)[15:0]
Column Address (CA)[11:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128KB Block Addr (1024 Blocks) Page Addr (64 Pages)
Byte Address(0-2047 Byte)
X X X X Ext
Main Memory Array(2,048-Byte)
ECC Protected
Spare Area(64-Byte)
Page
Structure
(2,112-Byte)
Sector 0
512-Byte
Sector 1
512-Byte
Sector 2
512-Byte
Sector 3
512-Byte
Spare 0
16-Byte
Spare 1
16-Byte
Spare 2
16-Byte
Spare 3
16-Byte
Column
Address
000h--1FFh
200h--3FFh
400h--5FFh
600h--7FFh
800h--80Fh
810h--81Fh
820h--82Fh
830h--83Fh
Byte
Definition
Bad Block
Marker
Byte
Address
0
1
User Data
Ⅱ
2
3
User Data
Ⅰ
4
5
6
No ECC
Protection
7
8
ECC for Sector 0
and Spare 0 User Data I
9
A
B
C
D
E
F
ECC
Protected
Figure 5-1 W25N01JW Flash Memory Architecture and Addressing
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Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
6.
FUNCTIONAL DESCRIPTIONS
6.1 Device Operation Flow
Power Up
(Default BUF=1, ECC-E=1)
Power Up
(Default BUF=0, ECC-E=1)
Initialization &
Auto Page Data Read (13h)(1) ~500us
Initialization &
Auto Page Data Read (13h)(1) ~500us
Read
Block00, Page 00?
Y
Read
Block 00, Page 00?
N
Load Block xx, Page yy
tRD2 ~60us
Y
N
Load Block xx, Page yy
tRD2 ~60us
Start “Buffer Read” with column address
(Page 00 or Page yy)
Start “Continuous Read” from column 0
(Page 00 or Page yy)
Set BUF=0
Set BUF=1
Load Block xx, Page yy
tRD2 ~60us
Load Page yy
tRD2 ~60us
Start “Continuous Read” from column 0
(Page yy)
Start “Buffer Read” with column address
(Page yy)
W25N01JWxxxG
W25N01JWxxxT
Notes:
1.
Automatically execution of Page Data Read (13h) command for Block0, Page0.
Figure 6-1 W25N01JW Flash Memory Operation Diagram
6.1.1 Standard SPI Instructions
The W25N01JW is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0
and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and
data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the
falling and rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising
edges of /CS.
6.1.2 Dual SPI Instructions
The W25N01JW supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)”, “Fast Read Dual I/O (BBh)”, “DTR Fast Read Dual Output (3Dh)” and “DTR Fast Read Dual I/O
(BDh)”. These instructions allow data to be transferred to or from the device at two to three times the
rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly downloading
code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly from
the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become bidirectional I/O pins:
IO0 and IO1.
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Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
6.1.3 Quad SPI Instructions
The W25N01JW supports Quad SPI operation when using instructions such as “Fast Read Quad
Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “DTR Fast Read Quad Output (6Dh)”, “DTR Fast Read
Quad I/O (EDh)” and “Quad Program Data Load (32h/34h)”. These instructions allow data to be
transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad Read
instructions offer a significant improvement in continuous and random access transfer rates allowing
fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI
instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become
IO2 and IO3 respectively.
6.1.4 DTR Read Instructions
To effectively improve the read operation throughput without increasing the serial clock frequency,
W25N01JW introduces DTR (Double Transfer Rate) Read instructions that support
Standard/Dual/Quad SPI modes. The byte-long instruction code is latched into the device on the rising
edge of the serial clock similar to all other SPI instructions. Once a DTR instruction code is accepted
by the device, the address input and data output will be latched on both rising and falling edges of the
serial clock.
6.1.5 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25N01JW operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume
where it left off once the bus is available again. The /HOLD function is only available for standard SPI
and Dual SPI operation, not during Quad SPI. When QE=1 or DTR operation is enabled, the /HOLD
function is not available.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate
on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low
the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate
on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial
Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored.
The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to
avoid resetting the internal logic state of the device.
6.1.6 Software Reset
6.1.6.1 Device Reset (FFh) instruction
The Device Reset (FFh) instruction terminates any on-going internal operations without initialization for
all volatile writable bits in the Status Registers. If the command sequence is successfully accepted, the
device will take approximately tRST to reset. No command will be accepted during the reset period.
Please refer to “8.2.1 Device Reset (FFh), Enable Reset (66h) and Reset Device (99h)” for detail
information about command sequence and the value of each Status Registers after reset.
6.1.6.2 Enable Reset (66h) and Reset Device (99h) instructions
The W25N01JW can be reset to the initial state by Enable Reset (66h) & Reset (99h) instructions. If the
command sequence is successfully accepted, the device will take approximately tRST to reset. No
command will be accepted during the reset period. Please refer to “8.2.1 Device Reset (FFh), Enable
Reset (66h) and Reset Device (99h)” for detail information about command sequence and the value of
each Status Registers after reset.
- 13 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
6.1.7 Hardware Reset
6.1.7.1 /RESET Pin
For the SOIC and TFBGA package types, the W25N01JW provides a dedicated /RESET pin. Drive
/RESET pin low for a minimum period of 1us (tRESET) will reset the device to its initial power-on state.
It takes same busy time with power-on (tVSL and tPUW) because Hardware Reset goes into the same
state of after power-on. No command will be accepted during the tVSL period. Hardware /RESET pin
has the highest priority among all the input signals. Drive /RESET low for a minimum of 1us (tRESET)
will interrupt any on-going external/internal operations, regardless the status of other SPI signals (/CS,
CLK, IOs, /WP and /HOLD). Please refer to “8.2.1 Device Reset (FFh), Enable Reset (66h) and Reset
Device (99h)” for detail information about the value of each Status Registers after reset.
Notes:
1.
2.
6.2
While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum pulse is
recommended to ensure reliable operation.
There is an internal pull-up resistor for the dedicated /RESET pin on SOIC and TFBGA package. If the reset function is not
used, this pin can be left floating in the system.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the
W25N01JW provides several means to protect the data from inadvertent writes.
Device resets when VCC is below threshold
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Protection Register (SR-1)
Lock Down write protection for Protection Register (SR-1) until the next power-up
One Time Program (OTP) write protection for memory array using Protection Register (SR-1)
Hardware write protection using /WP pin when WP-E is set to 1
Upon power-up or at power-down, while VCC is below VCC (min), (see “Power-up Power-down Timing
Requirements”), all operations are disabled and no instructions are recognized. During power-up, after
the VCC voltage exceeds VCC (min) and tVSL has elapsed, all program and erase related instructions
are further disabled for a time delay of tPUW. This includes the Write Enable, Program Execute, Block
Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC
supply level at power-up until the VCC-min level and tVSL time delay is reached, and it must also track
the VCC supply level at power-down to prevent adverse command sequence. If needed a pull-up
resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Program Execute or
Block Erase or Bad Block Management instruction will be accepted. After completing a program or
erase instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (TB, BP[3:0]) bits. These settings allow a
portion or the entire memory array to be configured as read only. Used in conjunction with the Write
Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control.
See Protection Register section for further information.
The WP-E bit in Protection Register (SR-1) is used to enable the hardware protection. When WP-E is
set to 1, bringing /WP low in the system will block any Write/Program/Erase command to the
W25N01JW, the device will become read-only. The Quad SPI operations are also disabled when WPE is set to 1.
When QE=1, the Write Protection function is not available.
- 14 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
6.3
DLP (Data Learning Pattern)
For Quad DTR Read commands (6Dh, EDh, EEh), a pre-defined "Data Learning Pattern" can be used
by the flash memory controller to determine the flash data output timing on 4 I/O pins.
When DLP-E=1, during the last 4 dummy clocks just prior to the data output, W25N01JW will output
"00110100" Data Learning Pattern sequence on each of the 4 I/O pins. During this period, controller
can fine tune the data latching timing for each I/O pins to achieve optimum system performance. DLPE=0 will disable the Data Learning Pattern output.
The Data Learning Pattern can also be defined by a "Write Data Learning Pattern (4Ah)" command
followed by 8-bits user-defined pattern. The user-defined pattern is volatile. After device power cycle,
the Data Learning Pattern will return to its "00110100" default value.
/CS
CLK
Mode 3
Mode 0
0
7
Instrustion
DI
(IO0)
8
9
10
11
12
13
14
15
17
16
Dummy
Clocks
Column
Address[15:0]
18
19
Data Data
Out 1 Out 2
12 8
4
0
0
0
1
1
0
1
0
0
D
4
D
0
D
4
D
0
13 9
5
1
0
0
1
1
0
1
0
0
D
5
D
1
D
5
D
1
IO2
14 10 6
2
0
0
1
1
0
1
0
0
D
6
D
2
D
6
D
2
IO3
15 11 7
3
0
0
1
1
0
1
0
0
D D D D
7 3 7 3
＊
＊
＊=MSB
DO
(IO1)
EDh
Data Learning
Pattern
Figure 6-2 DLP (Data Learning Pattern) output example in DTR Fast Read Quad I/O (BUF=1)
- 15 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
6.4
Interface States
This section describes the input and output signal levels.
State
Power-off
Power-on Reset
Reset (during tRST)
HW Reset
Interface Standby
Hold Cycle
Instruction Cycle
Single Input Cycle
Single Dummy Cycle
Single Output Cycle
Dual Input Cycle
Dual Dummy Cycle
Dual Output Cycle
Quad Input Cycle
Quad Dummy Cycle
Quad Output Cycle
Transfer Rate
STR/DTR
STR/DTR
STR/DTR
STR/DTR
STR/DTR
STR only
DTR
STR
DTR
STR
DTR
STR
DTR
STR
DTR
STR
DTR
STR
DTR
STR
DTR
STR
DTR
STR
DTR
/RESET
X
*2
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
/CS
X
*2
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
CLK
/HOLD (IO3) /WP (IO2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L or H or T
L
X
T
H
X
T
H
X
T
X
X
T
H
X
T
X
X
T
H
X
T
X
X
T
H
X
T
X
X
T
H
X
T
X
X
T
H
X
T
X
X
T
(Input)
(Input)
T
(Input)
(Input)
T
Z
Z
T
Z
Z
T
(Output)
(Output)
T
(Output)
(Output)
DO (IO1)
Z
Z
Z
Z
Z
Z *1
Z
Z
Z
Z
Z
(Output)
(Output)
(Input)
(Input)
Z
Z
(Output)
(Output)
(Input)
(Input)
Z
Z
(Output)
(Output)
DI (IO0)
X
X
X
X
X
X
(Input)
(Input)
(Input)
Z
Z
X
X
(Input)
(Input)
Z
Z
(Output)
(Output)
(Input)
(Input)
Z
Z
(Output)
(Output)
H= High input/output level
L= Low input/outut level
Z= Hi-Z
X= H or L level
T= Toggling between H and L
*1: During input sequence in Dual or Quad mode, this states is “X”.
*2: Refer to Fig 9.2
- 16 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.
PROTECTION, CONFIGURATION AND STATUS REGISTERS
Three Status Registers are provided for W25N01JW: Protection Register (SR-1), Configuration
Register (SR-2) & Status Register (SR-3). Each register is accessed by Read Status Register and Write
Status Register commands combined with 1-Byte Register Address respectively.
The Read Status Register instruction (05h / 0Fh) can be used to provide status on the availability of the
flash memory array, whether the device is write enabled or disabled, the state of write protection, Read
modes, Protection Register/OTP area lock status, Erase/Program results and ECC usage/status.
The Write Status Register instruction can be used to configure the device write protection features,
Software/Hardware write protection, Read modes and enable/disable ECC, Protection Register/OTP area
lock, enable/disable Data Learning Pattern, number of dummy clocks, enable/disable Quad operation.
Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect
bits (SRP0, SRP1), the Write Enable instruction, and when WP-E is set to 1, the /WP pin.
7.1
Protection Register / Status Register-1 (Volatile Writable, OTP lockable)
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP3
BP2
BP1
BP0
TB
WP-E
SRP1
Status Register Protect-0
(Volatile Writable, OTP Lock)
Block Protect Bits
(Volatile Writable, OTP Lock)
Top/Bottom Protect Bit
(Volatile Writable, OTP Lock)
/WP Enable Bit
(Volatile Writable, OTP Lock)
Status Register Protect-1
(Volatile Writable, OTP Lock)
Figure 7-1 Protection Register / Status Register-1 (Address Axh)
7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable
The Block Protect bits (BP3, BP2, BP1, BP0 & TB) are volatile read/write bits in the status register-1
(S6, S5, S4, S3 & S2) that provide Write Protection control and status. Block Protect bits can be set
using the Write Status Register Instruction. All, none or a portion of the memory array can be protected
from Program and Erase instructions (see Status Register Memory Protection table). The default values
for the Block Protection bits are 1 after power up to protect the entire array. If the SR1-L bit in the
Configuration Register (SR-2) is set to 1, the default values will the values that are OTP locked.
- 17 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.1.2 Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable
The Write Protection Enable bit (WP-E) is a volatile read/write bits in the status register-1 (S1). The
WP-E bit, in conjunction with SRP1 & SRP0, controls the method of write protection: software protection,
hardware protection, power supply lock-down or one time programmable (OTP) protection, /WP pin
functionality, and Quad SPI operation enable/disable. When WP-E = 0 (default value), the device is in
Software Protection mode, /WP & /HOLD pins are multiplexed as IO pins, and Quad program/read
functions are enabled all the time. When WP-E is set to 1, the device is in Hardware Protection mode,
all Quad functions are disabled and /WP & /HOLD pins become dedicated control input pins.
7.1.3 Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable
The Status Register Protect bits (SRP1 and SRP0) are volatile read/write bits in the status register (S0
and S7). The SRP bits control the method of write protection: software protection, hardware protection,
power supply lock-down or one time programmable (OTP) protection.
Software Protection (Driven by Controller, WP-E is disabled)
SRP1
SRP0
WP-E
/WP/IO2
QE
Descriptions
0
0
0
X
0
No /WP functionality
0
1
0
0
0
SR-1 cannot be changed (/WP = 0 during Write Status)
0
1
0
1
0
SR-1 can be changed (/WP = 1 during Write Status)
1
0
0
X
0
Power Lock Down(1) SR-1
1
1
0
X
0
Enter OTP mode to protect SR-1 (allow SR1-L=1)
0
0
0
X
1
No /WP functionality
/WP pin will always function as IO2
0
1
0
X
1
SR-1 can be changed
/WP pin will function as IO2 for Quad operations
1
0
0
X
1
Power Lock Down(1) SR-1
/WP pin will always function as IO2
1
1
0
X
1
Enter OTP mode to protect SR-1 (allow SR1-L=1)
/WP pin will always function as IO2
Hardware Protection (System Circuit / PCB layout, Quad Program/Read is disabled)
SRP1
SRP0
WP-E
/WP only
QE
Descriptions
0
X
1
VCC
0
SR-1 can be changed
1
0
1
VCC
0
Power Lock-Down(1) SR-1
1
1
1
VCC
0
Enter OTP mode to protect SR-1 (allow SR1-L=1)
X
X
1
GND
0
All "Write/Program/Erase" commands are blocked
Entire device (SRs, Array, OTP area) is read-only
Notes:
1.
2.
When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
When WP-E=1, QE bit have to be ignored.
- 18 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.2
Configuration Register / Status Register-2 (Volatile Writable)
S7
S6
S5
S4
S3
S2
S1
S0
OTP-L
OTP-E
SR1-L
ECC-E
BUF
R
R
QE
OTP Data Pages Lock
(OTP Lock)
Enter OTP Mode
(Volatile Writable)
Status Register-1 Lock
(OTP Lock)
Enable ECC
(Volatile Writable)
Buffer Mode
(Volatile Writable)
Reserved
Quad Enable
(Volatile Writable)
Figure 7-2 Configuration Register / Status Register-2 (Address Bxh)
7.2.1 One Time Program Lock Bit (OTP-L) – OTP lockable
In addition to the main memory array, W25N01JW also provides an OTP area for the system to store
critical data that cannot be changed once it’s locked. The OTP area consists of 10 pages of 2,112-Byte
each. The default data in the OTP area are FFh. Only Program command can be issued to the OTP
area to change the data from “1” to “0”, and data is not reversible (“0” to “1”) by the Erase command.
Once the correct data is programmed in and verified, the system developer can set OTP-L bit to 1, so
that the entire OTP area will be locked to prevent further alteration to the data.
7.2.2 Enter OTP Access Mode Bit (OTP-E) – Volatile Writable
The OTP-E bit must be set to 1 in order to use the standard Program/Read commands to access the
OTP area as well as to read the Unique ID / Parameter Page information. The default value after power
up or a RESET command is 0.
7.2.3 Status Register-1 Lock Bit (SR1-L) – OTP lockable
The SR1-L lock bit is used to OTP lock the values in the Protection Register (SR-1). Depending on the
settings in the SR-1, the device can be configured to have a portion of or up to the entire array to be
write-protected, and the setting can be OTP locked by setting SR1-L bit to 1. SR1-L bit can only be set
to 1 permanently when SRP1 & SRP0 are set to (1, 1), and OTP Access Mode must be entered (OTPE=1) to execute the programming. Please refer to 8.2.38 for detailed information.
- 19 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.2.4 ECC Enable Bit (ECC-E) – Volatile Writable
W25N01JW has a built-in ECC algorithm that can be used to preserve the data integrity. Internal ECC
calculation is done during page programming, and the result is stored in the extra 64-Byte area for each
page. During the data read operation, ECC engine will verify the data values according to the previously
stored ECC information and to make necessary corrections if needed. The verification and correction
status is indicated by the ECC Status Bit. ECC function is enabled by default when power on (ECCE=1), and it will not be reset to 0 by the Device Reset command.
The constraint when ECC-E=1 are as follows:
The areas protected by ECC is shown in the table below. User Data I is protected by ECC, but
User Data II is out of protected by ECC.
The Number of Partial Page Program (NoP) is 4 for the entire page, including the spare area.
Therefore the user needs to program one sector and optionally User Data 1 of pared spare area
(example, main area-sector 0 and spare area-spare 0) at one time program to properly and
automatically program the ECC parity code.
Main Memory Array(2,048-Byte)
ECC Protected
Spare Area(64-Byte)
Page
Structure
(2,112-Byte)
Sector 0
512-Byte
Sector 1
512-Byte
Sector 2
512-Byte
Sector 3
512-Byte
Spare 0
16-Byte
Spare 1
16-Byte
Spare 2
16-Byte
Spare 3
16-Byte
Column
Address
000h--1FFh
200h--3FFh
400h--5FFh
600h--7FFh
800h--80Fh
810h--81Fh
820h--82Fh
830h--83Fh
Byte
Definition
Bad Block
Marker
Byte
Address
0
User Data
Ⅱ
1
2
User Data
Ⅰ
3
4
5
6
7
8
No ECC
Protection
Area
Address
(Start)
Address
(End)
Size
ECC for Sector 0
and Spare 0 User Data I
9
A
B
C
D
E
F
ECC
Protected
Main area
Sector 1
Sector 2
Sector 0
Sector 3
000h
200h
400h
600h
1FFh
3FFh
5FFh
7FFh
512B
512B
512B
512B
Spare area
Area
Address
(Start)
Address
(End)
Size
UD2
Spare 0
UD1
UD2
Spare 1
UD1
EPC
EPC
UD2
Spare 2
UD1
EPC
UD2
Spare 3
UD1
800h
804h
EPC
80Ch
810h
814h
81Ch
820h
824h
82Ch
830h
834h
83Ch
803h
4B
80Bh
80Fh
813h
81Bh
81Fh
823h
82Bh
82Fh
833h
83Bh
83Fh
8B
4B
4B
8B
4B
4B
8B
4B
4B
8B
4B
Notes:
1. UD2: User Data II
2. UD1: User Data I
3. EPC: ECC parity code
The gray area of the above table is protected by ECC
- 20 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.2.5 Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable
W25N01JW provides two different modes for read operations, Buffer Read Mode (BUF=1) and
Continuous Read Mode (BUF=0). Prior to any Read operation, a Page Data Read command is needed
to initiate the data transfer from a specified page in the memory array to the Data Buffer. By default,
after power up, the data in page 0 will be automatically loaded into the Data Buffer and the device is
ready to accept any read commands.
The Buffer Read Mode (BUF=1) requires a Column Address to start outputting the existing data inside
the Data Buffer, and once it reaches the end of the data buffer (Byte 2,111), DO (IO1) pin will become
high-Z state.
The Continuous Read Mode (BUF=0) doesn’t require the starting Column Address. The device will
always start output the data from the first column (Byte 0) of the Data buffer, and once the end of the
data buffer (Byte 2,048) is reached, the data output will continue through the next memory page. With
Continuous Read Mode, it is possible to read out the entire memory array using a single read command.
Please refer to respective command descriptions for the dummy cycle requirements for each read
commands under different read modes.
For W25N01JWxxxG part number, the default value of BUF bit after power up is 1. BUF bit can be
written to 0 in the Status Register-2 to perform the Continuous Read operation.
For W25N01JWxxxT part number, the default value of BUF bit after power up is 0. BUF bit can be
written to 1 in the Status Register-2 to perform the Buffer Read operation.
BUF
ECC-E
Read Mode
(Starting from Buffer)
ECC Status
Data Output Structure
1
1
0
1
Buffer Read
Buffer Read
N/A
Page based
2,048 + 64
2,048 + 64
0
0
Continuous Read
N/A
2,048
0
1
Continuous Read
Operation based
2,048
7.2.6 Quad Enable (QE) – Volatile Writable
The Quad Enable (QE) bit is a volatile read/write bit that enables Quad SPI operation. When QE=0, the
/WP and /HOLD pins are enabled, the device operates in Standard/Dual SPI modes. When QE=1
(factory default), the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled,
the device operates in Standard/Dual/Quad SPI modes.
If the SR1-L bit in the Configuration Register (SR-2) is set to 1, the default values will the values that
are OTP locked.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during standard SPI
or Dual SPI operation, the QE bit should never be set to a 1.
- 21 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.3
Status Register-3 (Status only)
S7
S6
S5
S4
S3
S2
S1
S0
R
LUT-F
ECC-1
ECC-0
P-FAIL
E-FAIL
WEL
BUSY
Reserved
BBM LUT Full
(Status Only)
ECC Status Bit
(Status Only)
Program Failure
(Status Only)
Erase Failure
(Status Only)
Write Enable Latch
(Status Only)
Operation In Progress
(Status Only)
Figure 7-3 Status Register-3 (Address Cxh)
7.3.1 Look-Up Table Full (LUT-F) – Status Only
To facilitate the NAND flash memory bad block management, the W25N01JW is equipped with an
internal Bad Block Management Look-Up-Table (BBM LUT). Up to 20 bad memory blocks may be
replaced by a good memory block respectively. The addresses of the blocks are stored in the internal
Look-Up Table as Logical Block Address (LBA, the bad block) & Physical Block Address (PBA, the
good block). The LUT-F bit indicates whether the 20 memory block links have been fully utilized or not.
The default value of LUT-F is 0, once all 20 links are used, LUT-F will become 1, and no more memory
block links may be established.
7.3.2 Cumulative ECC Status (ECC-1, ECC-0) – Status Only
ECC function is used in NAND flash memory to correct limited memory errors during read operations.
The ECC Status Bits (ECC-1, ECC-0) should be checked after the completion of a Read operation to
verify the data integrity. The ECC Status bits values are don’t care if ECC-E=0. These bits will be cleared
to 0 after a power cycle or a RESET command or a Page Data Read command.
- 22 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
ECC Status
Descriptions
ECC-1
ECC-0
0
0
The entire data output is provided without requiring any ECC correction.
0
1
The entire data output experienced a 1 bit correction event after reading either
single or multiple pages.
1
0
The entire data output experienced a 2 bit error event in a single page that
cannot be corrected2 in the Continuous Read Mode, an additional command
can be used to read out the Page Address (PA) that contains the error.
1
The entire data output experienced a 2 bit error event in multiple pages. In the
Continuous Read Mode, the additional command can only provide the last Page
Address (PA) that contain the 2 bit error. PAs for other pages with the 2 bit error
is not available. The data read is not suitable for use2, 3.
1
Notes:
1.
2.
3.
As the ECC engine is based on Hamming code, the ECC status bits are applicable for 1 bit ECC correction and 2 bit
ECC detection. This Serial NAND is not expected to experience 3 or more bits of error when used within the datasheet
specifications. When there is a 1 bit error correction event, user may decide to erase and reprogram the associated
block, based on the user’s quality policy.
If the read operation contains both 1 or 2 bit error event, the 2 bit error condition will be used.
ECC-1, ECC-0 = (1, 1) is only applicable during Continuous Read operation (BUF=0).
7.3.3 Program Failure (P-FAIL) – Status Only
The Program Failure Bit is used to indicate whether the internally-controlled Program operation was
executed successfully (P-FAIL=0) or timed out (P-FAIL=1). The P-FAIL bit is also set when the Program
command is issued to a locked or protected memory array or OTP area. This bit is cleared at the
beginning of the Program Execute instruction on an unprotected memory array or OTP area. Device
Reset instruction can also clear the P-FAIL bit.
7.3.4 Erase Failure (E-FAIL) – Status Only
The Erase Failure Bit is used to indicate whether the internally-controlled Erase operation was executed
successfully (E-FAIL=0) or timed out (E-FAIL=1). The E-FAIL bit is also set when the Erase command
is issued to a locked or protected memory array. This bit is cleared at the beginning of the Block Erase
instruction on an unprotected memory array. Device Reset instruction can also clear the E-FAIL bit.
7.3.5 Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Program
Execute, Block Erase, Page Data Read and Program Execute and Bad Block Management for OTP
pages.
7.3.6 Read/Erase/Program in Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is powering
up or executing a Page Data Read, BBM Management, Program Execute, Block Erase and Program
Execute for OTP area, OTP Locking or after a Continuous Read instruction. During this time the device
will ignore further instructions except for the Read Status Register, Reset and Read JEDEC ID
instructions. When the program, erase or write status register instruction has completed, the BUSY bit
will be cleared to a 0 state indicating the device is ready for further instructions.
- 23 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.4
Status Register-4 (Writable and Status)
S7
S6
S5
S4
S3
S2
S1
S0
R
ODS1
ODS0
R
DLP-E
HS
R
R
Reserved
Output Driver Strength
(Volatile Writable)
Reserved
Enable Data Learning Pattern
(Volatile Writable)
Enable High Speed Mode
(Volatile Writable)
Reserved
Figure 7-4 Status Register-4 (Address Dxh)
7.4.1 Output Driver Strength (ODS1, ODS0) – Volatile Writable
The ODS1 & ODS0 bits are used to determine the output driver strength for the Read operations.
ODS1, ODS0
Output Driver Strength
0, 0
100% (Default setting)
0, 1
75%
1, 0
50%
1, 1
25%
7.4.2 Data Learning Pattern Enable (DLP-E) – Volatile Writable
For Quad DTR Read commands, a pre-defined “Data Learning Pattern” can be used by the flash
memory controller to determine the flash data output timing on I/O pins. When DLP-E=1, during the last
4 dummy cycles just prior to the data output, W25N01JW will output “00110100” Data Learning Pattern
sequence on each of the 4 I/O pins. During the period, controller can fine tune the data latching timing
for each I/O pins to achieve optimum system performance. DLP-E=0 will disable the Data Learning
Pattern output. The Data Learning Pattern can also be defined by a “Write Data Learning Pattern (4Ah)”
command followed by 8-bits user-defined pattern. The user defined pattern is volatile. After device
power cycle, the Data Learning Pattern will return to its “00110100” default value.
7.4.3 High Speed Enable (HS) – Volatile Writable
The HS bit enables the following commands to operate at 166 MHz.
Fast Read Dual I/O (BBh)
Fast Read Dual I/O with 4-Byte Address (BCh)
Fast Read Quad I/O (EBh)
Fast Read Quad I/O with 4-Byte Address (ECh)
When HS = 1, the dummy cycles of these commands are set from 4 to 8, allowing operation at 166
MHz. When HS = 0, the dummy cycle of these commands is 4, and operation up to 104 MHz is possible.
- 24 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.5
Extended Register
The Data Learning Pattern can be defined by a "Write Data Learning Pattern (4Ah)" command followed
by 8-bits user-defined pattern. The user defined pattern is volatile. After device power cycle, the Data
Learning Pattern will return to its "00110100" default value.
S7
S6
S5
S4
S3
S2
S1
S0
DLP7
DLP6
DLP5
DLP4
DLP3
DLP2
DLP1
DLP0
Data Learning Pattern definition bit
(Volatile Writable)
Figure 7-5 Extended Register
- 25 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
7.6
W25N01JW Status Register Memory Protection
STATUS REGISTER(1)
W25N01JW (1G-BIT / 128M-BYTE) MEMORY PROTECTION(2)
PROTECTED
PROTECTED
PROTECTED
PROTECTED
PAGE ADDRESS
BLOCK(S)
DENSITY
PORTION
PA[15:0]
TB
BP3
BP2
BP1
BP0
X
0
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
1022 & 1023
FF80h - FFFFh
256KB
Upper 1/512
0
0
0
1
0
1020 thru 1023
FF00h - FFFFh
512KB
Upper 1/256
0
0
0
1
1
1016 thru 1023
FE00h - FFFFh
1MB
Upper 1/128
0
0
1
0
0
1008 thru 1023
FC00h - FFFFh
2MB
Upper 1/64
0
0
1
0
1
992 thru 1023
F800h - FFFFh
4MB
Upper 1/32
0
0
1
1
0
960 thru 1023
F000h - FFFFh
8MB
Upper 1/16
0
0
1
1
1
896 thru 1023
E000h - FFFFh
16MB
Upper 1/8
0
1
0
0
0
768 thru 1023
C000h - FFFFh
32MB
Upper 1/4
0
1
0
0
1
512 thru 1023
8000h - FFFFh
64MB
Upper 1/2
1
0
0
0
1
0&1
0000h – 007Fh
256KB
Lower 1/512
1
0
0
1
0
0 thru 3
0000h - 00FFh
512KB
Lower 1/256
1
0
0
1
1
0 thru 7
0000h - 01FFh
1MB
Lower 1/128
1
0
1
0
0
0 thru 15
0000h - 03FFh
2MB
Lower 1/64
1
0
1
0
1
0 thru 31
0000h - 07FFh
4MB
Lower 1/32
1
0
1
1
0
0 thru 63
0000h - 0FFFh
8MB
Lower 1/16
1
0
1
1
1
0 thru 127
0000h - 1FFFh
16MB
Lower 1/8
1
1
0
0
0
0 thru 255
0000h - 3FFFh
32MB
Lower 1/4
1
1
0
0
1
0 thru 511
0000h - 7FFFh
64MB
Lower 1/2
X
1
0
1
X
0 thru 1023
0000h - FFFFh
128MB
ALL
X
1
1
X
X
0 thru 1023
0000h - FFFFh
128MB
ALL
Notes:
1.
2.
X = don’t care
If any Erase or Program command specifies a memory region that contains protected data portion, this command will be
ignored.
- 26 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25N01JW are fully controlled through the SPI bus
(see Instruction Set Table). Instructions are initiated with the falling edge of Chip Select (/CS). The first
byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on
the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
Figures of each commands description. All read instructions can be completed after any clocked bit.
However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven
high after a full 8-bits have been clocked) otherwise the instruction will be ignored. This feature further
protects the device from inadvertent writes. Additionally, while the device is performing Program or
Erase operation, BBM management, Page Data Read or OTP locking operations, BUSY bit will be high,
and all instructions except for Read Status Register or Read JEDEC ID will be ignored until the current
operation cycle has completed.
8.1
Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID
(MF7 - MF0)
Winbond Serial Flash
EFh
Device ID
(ID15 - ID0)
W25N01JW
BC21h
- 27 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.1.2 Instruction Set Table 1 (Continuous Read, BUF = 0, xxxT Default Power Up Mode)(11)
Default
Dummy
HS=1
Dummy
RESET Enable + RESET
66h+99h
Memory (NOR compatible)
Op
Code
0
-
Device RESET
FFh
0
-
Read JEDEC ID
9Fh
8
Read Status Register-1
0Fh/05h
Read Status Register-2
Byte2
Byte3
Byte4
Byte5
Byte6
Byte7
-
Dummy
MF7-0
ID15-8
ID7-0
0
-
Axh
S7-0
S7-0
S7-0
S7-0
S7-0
0Fh/05h
0
-
Bxh
S7-0
S7-0
S7-0
S7-0
S7-0
Read Status Register-3
0Fh/05h
0
-
Cxh
Read Status Register-4
0Fh/05h
0
-
Dxh
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Write Status Register-1
1Fh/01h
0
-
Axh
S7-0
Write Status Register-2
1Fh/01h
0
-
Bxh
S7-0
Write Status Register-4
1Fh/01h
0
-
Dxh
S7-0
Write Data Learning
Pattern
4Ah
0
-
P7-0
Write Enable
06h
-
-
Write Disable
04h
-
-
Deep Power-down
B9h
-
-
Release Deep Powerdown
ABh
-
-
Bad Block Management
(Swap Blocks)
A1h
0
-
LBA0
LBA0
PBA0
PBA0
LBA1
LBA1
Read BBM LUT
A5h
8
-
Last ECC failure Page
Address
Dummy
LBA0
LBA0
PBA0
PBA0
LBA1
A9h
8
-
Dummy
PA15-8
PA7-0
Block Erase
D8h
8
-
Dummy
PA15-8
PA7-0
Program Data Load
Random Program Data
Load
02h
0
-
CA15-8
CA7-0
D0
D1
D2
D3
84h
0
-
CA15-8
CA7-0
D0
D1
D2
D3
Quad Program Data Load 32h
0
-
CA15-8
CA7-0
D0
D1
D2
D3
Random Quad Program
Data Load
34h
0
-
CA15-8
CA7-0
D0
D1
D2
D3
Program Execute
10h
8
-
Dummy
PA15-8
PA7-0
Command
- 28 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
(Continue instruction set table of BUF=0)
Command
Op
Code
Default
Dummy
HS=1
Dummy
Byte2
Byte3
Byte4
PA23-16
PA15-8
PA7-0
Page Data Read
13h
8
-
Read
03h
24
-
Fast Read
0Bh
32
-
Fast Read
with 4-Byte Address
0Ch
40
-
Fast Read Dual Output
3Bh
32
-
Fast Read Dual Output
with 4-Byte Address
3Ch
40
-
Fast Read Quad Output
6Bh
32
-
Fast Read Quad Output
with 4-Byte Address
6Ch
40
-
Fast Read Dual I/O
BBh
16
20
Fast Read Dual I/O
with 4-Byte Address
BCh
20
24
Fast Read Quad I/O
EBh
12
16
Fast Read Quad I/O
with 4-Byte Address
ECh
14
18
DTR Fast Read
0Dh
18
-
DTR Fast Read
with 4-Byte Address
0Eh
22
-
DTR Fast Read Dual
Output
3Dh
18
-
DTR Fast Read Quad
Output
6Dh
20
-
DTR Fast Read Dual I/O
BDh
12
-
DTR Fast Read Dual I/O
with 4-Byte Address
BEh
14
-
DTR Fast Read Quad I/O
EDh
11
-
DTR Fast Read Quad I/O
with 4-Byte Address
EEh
12
-
Byte5
Byte6
Byte7
D0
D1
D2
D0
D1
Dummy
Dummy
Dummy
D0
Dummy
D0
D1
Dummy
Dummy
D0
D1
D2
D3
Dummy
Dummy
D0
Dummy
Dummy
D0
Dummy
D5
D6
D7
D0
D1
D2
D3
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D0
D1
D2
D0
D0
D1
D2
D3
D1
D3
D4
D4
D2
D5
D6
D5
D3
D7
D8
D4
D9
D10
D11
D6
D5
D12
D13
…
…
D14
D D D D D D D D D D D D D D D D D D D D D D D D D D D D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Dummy
Dummy
D4
D1
Dummy
Dummy
D1
D2
Dummy
Dummy
D3
D0
D1
Dummy
Dummy
D2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
- 29 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.1.3 Instruction Set Table 2 (Buffer Read, BUF = 1, xxxG Default Power Up Mode)(12)
Default
Dummy
HS=1
Dummy
RESET Enable + RESET
66h+99h
Memory (NOR compatible)
Op
Code
0
-
Device RESET
FFh
0
-
Read JEDEC ID
9Fh
8
Read Status Register-1
0Fh/05h
Read Status Register-2
Byte2
Byte3
Byte4
Byte5
Byte6
Byte7
-
Dummy
MF7-0
ID15-8
ID7-0
0
-
Axh
S7-0
S7-0
S7-0
S7-0
S7-0
0Fh/05h
0
-
Bxh
S7-0
S7-0
S7-0
S7-0
S7-0
Read Status Register-3
0Fh/05h
0
-
Cxh
Read Status Register-4
0Fh/05h
0
-
Dxh
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Write Status Register-1
1Fh/01h
0
-
Axh
S7-0
Write Status Register-2
1Fh/01h
0
-
Bxh
S7-0
Write Status Register-4
1Fh/01h
0
-
Dxh
S7-0
Write Data Learning
Pattern
4Ah
0
-
P7-0
Write Enable
06h
-
-
Write Disable
04h
-
-
Deep Power-down
B9h
-
-
Release Deep Powerdown
ABh
-
-
Bad Block Management
(Swap Blocks)
A1h
0
-
LBA0
LBA0
PBA0
PBA0
LBA1
LBA1
Read BBM LUT
A5h
8
-
Last ECC failure Page
Address
Dummy
LBA0
LBA0
PBA0
PBA0
LBA1
A9h
8
-
Dummy
PA15-8
PA7-0
Block Erase
D8h
8
-
Dummy
PA15-8
PA7-0
Program Data Load
Random Program Data
Load
02h
0
-
CA15-8
CA7-0
D0
D1
D2
D3
84h
0
-
CA15-8
CA7-0
D0
D1
D2
D3
Quad Program Data Load 32h
0
-
CA15-8
CA7-0
D0
D1
D2
D3
Random Quad Program
Data Load
34h
0
-
CA15-8
CA7-0
D0
D1
D2
D3
Program Execute
10h
8
-
Dummy
PA15-8
PA7-0
Command
- 30 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
(Continue instruction set table of BUF=1)
Op
Code
Default
Dummy
HS=1
Dummy
Byte2
Byte3
Byte4
Page Data Read
13h
8
-
PA23-16
PA15-8
PA7-0
Read
03h
8
-
CA15-8
CA7-0
Fast Read
0Bh
8
-
CA15-8
CA7-0
Fast Read
with 4-Byte Address
0Ch
24
-
CA15-8
CA7-0
Fast Read Dual Output
3Bh
8
-
CA15-8
CA7-0
Fast Read Dual Output
with 4-Byte Address
3Ch
24
-
CA15-8
CA7-0
Fast Read Quad Output
6Bh
8
-
CA15-8
CA7-0
Fast Read Quad Output
with 4-Byte Address
6Ch
24
-
CA15-8
CA7-0
Fast Read Dual I/O
BBh
4
8
CA15-0
Fast Read Dual I/O
with 4-Byte Address
BCh
12
8
CA15-0
Fast Read Quad I/O
EBh
4
8
CA15-0
Fast Read Quad I/O
with 4-Byte Address
ECh
10
8
CA15-0
DTR Fast Read
0Dh
8
-
CA15-0
DTR Fast Read
with 4-Byte Address
0Eh
14
-
CA15-0
DTR Fast Read Dual
Output
3Dh
8
-
CA15-0
Dummy
DTR Fast Read Quad
Output
6Dh
8
-
CA15-0
Dummy
DTR Fast Read Dual I/O
BDh
8
-
DTR Fast Read Dual I/O
with 4-Byte Address
BEh
10
-
Command
CA15-0
Dummy
DTR Fast Read Quad I/O
EDh
8
-
DTR Fast Read Quad I/O
with 4-Byte Address
EEh
10
-
CA
15-0
Byte6
Byte7
Dummy
D0
D1
D2
Dummy
D0
D1
D2
Dummy
Dummy
Dummy
D0
D1
Dummy
Dummy
D1
D0
Dummy
Dummy
Dummy
D3
D1
D2
D3
D4
D5
D6
D7
D4
D5
D0
D1
D8
D9
D10
D11
D0
D1
D2
D3
D2
D3
D4
D5
D6
D7
D8
D0
D1
D2
D3
D4
D5
D6
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D0
D1
D2
Dummy
D0
D2
D3
Dummy
Dummy
D1
Dummy
D0
D2
D0
D0
Dummy
Dummy
CA15-0
CA
15-0
Byte5
D3
D0
D0
D1
D2
D3
D4
D1
D4
D5
D5
D2
D6
D7
D3
D8
D9
D10
D6
D4
D11
D12
D7
D5
D13
D14
…
D15
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
- 31 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
Notes:
1.
Output designates data output from the device.
2.
Column Address (CA) only requires CA[11:0], CA[15:12] are considered as dummy bits.
3.
Page Address (PA) requires 16 bits. PA[15:6] is the address for 128KB blocks (total 1,024 blocks), PA[5:0] is the
address for 2KB pages (total 64 pages for each block).
4.
Logical and Physical Block Address (LBA & PBA) each consists of 16 bits. LBA[9:0] & PBA[9:0] are effective Block
Addresses. LBA[15:14] is used for additional information.
5.
Status Register Addresses:
Status Register 1 / Protection Register:
Status Register 2 / Configuration Register:
Status Register 3 / Status Register:
6.
Dual SPI Address Input (CA15-8 and CA7-0) format:
IO0 = x, x, CA10, CA8, CA6, CA4,
IO1 = x, x, CA11, CA9, CA7, CA5,
7.
Dual SPI Data Output (D7-0) format:
IO0 = D6, D4, D2, D0, ……
IO1 = D7, D5, D3, D1, ……
8.
Quad SPI Address Input (CA15-8 and CA7-0) format:
IO0 = x, CA8, CA4,
CA0
IO1 = x, CA9, CA5,
CA1
IO2 = x, CA10, CA6,
CA2
IO3 = x, CA11, CA7,
CA3
9.
Quad SPI Data Input/Output (D7-0) format:
IO0 = D4, D0, ……
IO1 = D5, D1, ……
IO2 = D6, D2, ……
IO3 = D7, D3, ……
Addr = Axh
Addr = Bxh
Addr = Cxh
CA2,
CA3,
CA0
CA1
10. All Quad Program/Read commands are disabled when WP-E bit is set to 1 in the Protection Register.
11. For all Read operations in the Continuous Read Mode, once the /CS signal is brought to high to terminate the read
operation, the device will still remain busy for tRD3 (BUSY=1), and all the data inside the Data buffer will be lost and
un-reliable to use. A new Page Data Read instruction must be issued to reload the correct page data into the Data
Buffer.
12. For all Read operations in the Buffer Read Mode, as soon as /CS signal is brought to high to terminate the read
operation, the device will be ready to accept new instructions and all the data inside the Data Buffer will remain
unchanged from the previous Page Data Read instruction.
- 32 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2
Instruction Descriptions
8.2.1 Device Reset (FFh), Enable Reset (66h) and Reset Device (99h)
Once the Reset instruction is accepted, any on-going internal operations will be terminated and will take
approximately tRST to reset. It depending on the current operation the device is performing, tRST can
be 5us~500us. During this period, no command will be accepted. After the execution of the Reset
instruction is completed, the each bits of Status Register will follow the following table.
If there is an on-going internal Erase or Program operation when Reset command sequence is
accepted by the device, data corruption may happen at only the address that is the target of the ongoing operation. It is recommended to check the BUSY bit in Status Register before issuing the Reset
command.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (FFh)
DI
(IO0)
High Impedance
DO
(IO1)
Figure 8-1 Device Reset Instruction (FFh)
/CS
CLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
0
1
Instrustion (66h)
2
3
4
5
6
7
Mode 3
Mode 0
Instrustion (99h)
DI
(IO0)
DO
(IO1)
Hight Impedance
Figure 8-2 Device Reset Instruction (66h+99h)
- 33 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
Register
Status Register-1
Status Register-2
Status Register-3
Address
Axh
Bxh
Cxh
Status Register-4
Dxh
Extended Register
-
Bits
Shipment
Default
Power Up after
LUT is full
Power Up after
OTP area
locked
Power Up after
SR-1 locked
After Reset cmd
(FFh)
After Reset cmd
(66h+99h)
or HW RESET
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
BP3
BP2
BP1
BP0
TB
WP-E
SRP1
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1 (locked)
x (locked)
x (locked)
x (locked)
x (locked)
x (locked)
x (locked)
1 (locked)
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
0
1
1
1
1
1
0
0
S7
S6
S5
S4
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
Clear to 0 befor OTP set
Clear to 0 before OTP set
1
1
1
1
0
0
0
S2
S1
S0
OTP-L
OTP-E
SR1-L
ECC-E
BUF
W25N01JWxxxG
BUF
W25N01JWxxxT
Reserved
Reserved
QE
1
1
1
S7
Reserved
-
-
-
-
-
S6
LUT-F
0
1
0
0
No Change
S5
S4
S3
S2
S1
S0
ECC-1
ECC-0
P-FAIL
E-FAIL
WEL
BUSY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S7
S6
S5
S4
S3
S2
S1
S0
Reserved
ODS1
ODS0
Reserved
DLP-E
HS
Reserved
Reserved
0
0
0
0
-
0
0
0
0
-
0
0
0
0
-
0
0
0
0
-
No Change
No Change
No Change
No Change
-
0
0
0
0
-
00110100
00110100
00110100
00110100
No Change
00110100
S3
DLP[7:0]
0
0
Clear to 0 befor OTP set
Clear to 0 before OTP set
No Change
1
No Change
1
0
No Change
0
1
No Change
1
0
(1)
Default values of the Status Registers after power up and Device Reset
Notes:
1.
If LUT is full, the bit indicates to "1" after Reset command (66h+99h) and HW RESET.
Auto Page Data Read (13h) (1)
During Power Up
sequence
After Reset cmd
(FFh)
After Reset cmd
(66h+99h)
or HW RESET
Execute
Execute
Execute
Auto Page Data Read (13h) execution during power up and after Device Reset
Notes:
1.
Automatically execution of Page Data Read (13h) command for Block0, Page0.
- 34 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.2 Read JEDEC ID (9Fh)
The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial
memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting
the instruction code “9Fh” followed by 8 dummy clocks.
The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes are then
shifted out on the falling edge of CLK with most significant bit (MSB) first. For memory type and
capacity values refer to Manufacturer and Device Identification table.
/CS
Mode 3
CLK
0
7
DO
(IO1)
15
16
23
24
31
32
38
Mode 3
Mode 0
Instruction
DI
(IO0)
8
Mode 0
8 Dummy
Clocks
9Fh
High Impedance
Mfr.ID[7-0]
*
* = MSB
Device ID[15:8]
Device ID[7:0]
*
*
Figure 8-3 Read JEDEC ID Instruction
- 35 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.3 Read Status Register (0Fh / 05h)
The Read Status Register instructions allow the 8-bits Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “0Fh or 05h” into the DI pin on the rising
edge of CLK followed by 8-bits Status Register Address. The status register bits are then shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first. Refer to section 7 for Status
Register descriptions.
The read status register instruction can be used, even while a Program or Erase cycle is in progress.
This allows the BUSY status bit to be checked to determine when the cycle is complete and if the
device can accept another instruction. The Status Register can be read continuously. The instruction
is completed by driving /CS high.
/CS
Mode 3
CLK
0
7
8
15
16
17
18
19
20
21
22
23
Mode 0
Mode 3
Mode 0
Instruction
DI
(IO0)
9
0Fh / 05h
SR Address
7
6
1
0
SR Value[7:0]
DO
(IO1)
High Impedance
7
6
5
4
3
2
1
0
Figure 8-4 Read Status Register Instruction
- 36 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.4 Write Status Register (1Fh / 01h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status
Register bits include: SRP[1:0], TB, BP[3:0] and WP-E bit in Status Register-1; OTP-L, OTP-E, SR1-L,
ECC-E and BUF bit in Status Register-2. All other Status Register bits locations are read-only and will
not be affected by the Write Status Register instruction.
To write the Status Register bits, the instruction is entered by driving /CS low, sending the instruction
code “1Fh or 01h”, followed by 8-bits Status Register Address, and then writing the status register
data byte. Refer to section 7 for Status Register descriptions. After power up, factory default for
BP[3:0], TB, ECC-E bits are 1, while other bits are 0.
/CS
Mode 3
CLK
0
7
8
9
15
16
17
18
19
20
21
22
23
Mode 3
Mode 0
Mode 0
Instruction
DI
(IO0)
SR Address
1Fh / 01h
7
6
1
SR Value[7:0]
0
7
6
5
4
3
2
1
0
High Impedance
DO
(IO1)
Figure 8-5 Write Status Register-1/2/3 Instruction
8.2.5 Write Data Learning Pattern (4Ah)
The Data Learning Pattern can be defined by a "Write Data Learning Pattern (4Ah)" command followed
by 8-bits user-defined pattern. The user defined pattern is volatile. After device power cycle, the Data
Learning Pattern will return to its "00110100" default value.
/CS
CLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
Instrustion (4Ah)
11
12
13
14
15
Mode 3
Mode 0
Data Learning Pattern
DI
(IO0)
DO
(IO1)
10
7
6
5
4
3
2
1
0
Hight Impedance
Figure 8-6 Write Data Learning Pattern
- 37 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.6 Write Enable (06h)
The Write Enable instruction sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The
WEL bit must be set prior to every Page Program, Quad Page Program and Block Erase instruction.
The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the
Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction (06h)
DI
(IO0)
High Impedance
DO
(IO1)
Figure 8-7 Write Enable Instruction
8.2.7 Write Disable (04h)
The Write Disable instruction resets the Write Enable Latch (WEL) bit in the Status Register to a 0.
The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Page Program, Quad Page Program, Block Erase and Reset and Bad Block
Management instructions.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
Mode 0
7
Mode 3
Mode 0
Instruction (04h)
DI
(IO0)
DO
(IO1)
High Impedance
Figure 8-8 Write Disable Instruction
- 38 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.8 Bad Block Management (A1h)
Due to large NAND memory density size and the technology limitation, NAND memory devices are
allowed to be shipped to the end customers with certain amount of “Bad Blocks” found in the factory
testing. Up to 2% of the memory blocks can be marked as “Bad Blocks” upon shipment, which is a
maximum of 20 blocks for W25N01JW. In order to identify these bad blocks, it is recommended to scan
the entire memory array for bad block markers set in the factory. A “Bad Block Marker” is a non-FFh
data byte stored at Byte 0 of Page 0 for each bad block. An additional marker is also stored in the first
two bytes of the 64-Byte spare area.
W25N01JW offers a convenient method to manage the bad blocks typically found in NAND flash
memory after extensive use. The “Bad Block Management” command is initiated by shifting the
instruction code “A1h” into the DI pin and followed by the 16-bits “Logical Block Address” and 16-bits
“Physical Block Address”. The logical block address is the address for the “bad” block that will be
replaced by the “good” block indicated by the physical block address.
A Write Enable instruction must be executed before the device will accept the Bad Block Management
instruction (Status Register bit WEL=1). The Bad Block Management instruction is initiated by driving
the /CS pin low and shifting the instruction code “A1h” followed by 16-bits LBA (Bad Block address) and
the 16-bits PBA (Good Block address). After /CS is driven high to complete the instruction cycle, the
self-timed Bad Block Management instruction will commence for a time duration of tPP (See AC
Characteristics). While the Bad Block Management cycle is in progress, the Read Status Register
instruction may still be used for checking the status of the BUSY bit. The BUSY bit is a 1 during the Bad
Block Management cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Bad Block Management cycle has finished, the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0.
Once a Bad Block Management command is successfully executed, the specified LBA-PBA link will
be added to the internal Look Up Table (LUT). Up to 20 links can be established in the non-volatile
LUT. If all 20 links have been written, the LUT-F bit in the Status Register will become a 1, and no
more LBA-PBA links can be established. Therefore, prior to issuing the Bad Block Management
command, the LUT-F bit value can be checked or a “Read BBM Look Up Table” command can be
issued to confirm if spare links are still available in the LUT.
To guarantee a continuous read operation on the first 1,000 blocks, the manufacturer may have used
some of the BBM LUT entrees. It is advisable for the user to scan all blocks and keep a table of all
manufacturer bad blocks prior to first erase/program operation.
Registering the same address in multiple PBAs is prohibited. It may cause unexpected behavior.
/CS
Mode 3
CLK
0
7
8
15
DO
(IO1)
23
24
31
32
39
Mode 3
Mode 0
Instruction
DI
(IO0)
16
Mode 0
A1h
LBA
[15:8]
PBA
[7:0]
[15:8]
[7:0]
High Impedance
Figure 8-9 Bad Block Management Instruction
- 39 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.9 Read BBM Look Up Table (A5h)
The internal Look Up Table (LUT) consists of 20 Logical-Physical memory block links (from LBA0/PBA0
to LBA19/PBA19). The “Read BBM Look Up Table” command can be used to check the existing address
links stored inside the LUT.
The “Read BBM Look Up Table” command is initiated by shifting the instruction code “A5h” into the DI
pin and followed by 8-bits dummy clocks, at the falling edge of the 16th clocks, the device will start to
output the 16-bits “Logical Block Address” and the 16-bits “Physical Block Address” as illustrated in
Figure 8-10. All block address links will be output sequentially starting from the first link (LBA0 & PBA0)
in the LUT. If there are available links that are unused, the output will contain all “00h” data.
The MSB bits LBA[15:14] of each link are used to indicate the status of the link.
LBA[15]
(Enable)
LBA[14]
(Invalid)
0
0
This link is available to use.
1
0
This link is enabled and it is a valid link.
1
1
This link was enabled, but it is not valid any more.
0
1
Not applicable.
Descriptions
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
8
15
16
23
24
31
32
40
47
48
8 Dummy
Clocks
A5h
LBA0
DO
(IO1)
39
Mode 0
High Impedance
[15:8]
*
PBA0
[7:0]
* = MSB
[15:8]
*
[7:0]
[15:8]
*
Figure 8-10 Read BBM Look Up Table Instruction
- 40 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.10 Last ECC Failure Page Address (A9h)
To better manage the data integrity, W25N01JW implements internal ECC correction for the entire
memory array. When the ECC-E bit in the Status/Configuration Register is set to 1 (also power up
default), the internal ECC algorithm is enabled for all Program and Read operations. During a “Program
Execute” command for a specific page, the ECC algorithm will calculate the ECC information based on
the data inside the 2K-Byte data buffer and write the ECC data into the extra 64-Byte ECC area in the
same physical memory page.
During the Read operations, ECC information will be used to verify the data read out from the physical
memory array and possible corrections can be made to limited amount of data bits that contain errors.
The ECC Status Bits (ECC-1 & ECC-0) will also be set indicating the result of ECC calculation.
For the “Continuous Read Mode (BUF=0)” operation, multiple pages of main array data can be read out
continuously by issuing a single read command. Upon finishing the read operation, the ECC status bits
should be check to verify if there’s any ECC correction or un-correctable errors existed in the read out
data. If ECC-1 & ECC-0 equal to (1, 0) or (1, 1), the previous read out data contain one or more pages
that contain ECC un-correctable errors.
The failure page address (or the last page address if it’s multiple pages) can be obtained by issuing
the “Last ECC failure Page Address” command. The 16-bits Page Address that contains uncorrectable ECC errors will be presented on the DO pin following the instruction code “A9h” and 8-bits
dummy clocks on the DI pin.
/CS
Mode 3
CLK
0
7
8
15
16
17
29
30
31
Mode 3
Mode 0
8 Dummy
Clocks
Instruction
DI
(IO0)
9
Mode 0
A9h
Page Address[15:0]
DO
(IO1)
High Impedance
15
14
13
2
1
0
Figure 8-11 Last ECC Failure Page Address Instruction
- 41 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.11
Deep Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Deep Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC
Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“B9h”.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep
Power-down instruction will not be executed. After /CS is driven high, the deep power-down state will
entered within the time duration of tDP (See AC Characteristics).
While in the deep power-down state only the Release Deep Power-down (ABh) and Devise Reset (FFh
or 66h/99h) instructions, which restores the device to normal operation, will be recognized. All other
instructions are ignored. This includes the Read Status Register instruction, which is always available
during normal operation. Ignoring almost instructions makes the Deep Power-down state a useful
condition for securing maximum write protection. The device always powers-up in the normal operation
with the standby current of ICC1.
/CS
tDP
CLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Instrustion (B9h)
DI
(IO0)
Stand-by current
Deep Powerdown current
Figure 8-12 Deep Power-down Instruction
- 42 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.12
Release Deep Power-down (ABh)
The Release Deep Power-down instruction can be used to release the device from the power-down
state. To release the device from the deep power-down state, the instruction is issued by driving the
/CS pin low, shifting the instruction code “ABh” and driving /CS high. Release from deep power-down
state will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal
operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time
duration.
/CS
tRES1
CLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Instrustion (ABh)
DI
(IO0)
Deep Powerdown current
Stand-by
current
Figure 8-13 Release Deep Power-down Instruction
- 43 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.13
128KB Block Erase (D8h)
The 128KB Block Erase instruction sets all memory within a specified block (64-Pages, 128K-Bytes) to
the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will
accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated
by driving the /CS pin low and shifting the instruction code “D8h” followed by 8-bits dummy clocks and
the 16-bits page address. The Block Erase instruction sequence is shown in below.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again.
After the Block Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is
cleared to 0. The Block Erase instruction will not be executed if the addressed block is protected by the
Block Protect (TB, BP3, BP2, BP1, and BP0) bits.
/CS
Mode 3
CLK
0
7
DO
(IO1)
9
15
16
17
29
30
31
Mode 3
Mode 0
Instruction
DI
(IO0)
8
Mode 0
D8h
8 Dummy
Clocks
Page Address[15:0]
15
14
13
2
1
0
High Impedance
Figure 8-14 128KB Block Erase Instruction
- 44 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.14 Load Program Data (02h) / Random Load Program Data (84h)
The Program operation allows from one byte to 2,112 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations.
A Program operation involves two steps:
1. Load the program data into the Data Buffer.
2. Issue “Program Execute” command to transfer the data from Data Buffer to the specified memory
page.
A Write Enable instruction must be executed before the device will accept the Load Program Data
Instructions (Status Register bit WEL=1). The “Load Program Data” or “Random Load Program Data”
instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” or “84h” followed
by a 16-bits column address (only CA[11:0] is effective). The /CS pin must be held low for the entire
length of the instruction while data is being sent to the device. If the number of data bytes sent to the
device exceeds the number of data bytes in the Data Buffer, the extra data will be ignored by the device.
The Load Program Data instruction sequence is shown in below.
Both “Load Program Data” and “Random Load Program Data” instructions share the same command
sequence. The difference is that “Load Program Data” instruction will reset the unused the data bytes
in the Data Buffer to FFh value, while “Random Load Program Data” instruction will only update the
data bytes that are specified by the command input sequence, the rest of the Data Buffer will remain
unchanged.
If internal ECC algorithm is enabled, all 2,112 bytes of data will be accepted, but the bytes designated
for ECC parity bits in the extra 64 bytes section will be overwritten by the ECC calculation. If the ECCE bit is set to a 0 to disable the internal ECC, the extra 64 bytes section can be used for external ECC
purpose or other usage.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
24
Mode 0
Instruction
DI
(IO0)
Column Address[15:0]
02h / 84h
15
14
13
2
1
0
7
High Impedance
DO
(IO1)
/CS
24
30
31
32
38
39
40
Mode 3
CLK
Mode 0
Data-0
DI
(IO0)
DO
(IO1)
7
6
1
Data-1
0
7
6
1
Data-2111
0
7
0
7
6
1
0
High Impedance
Figure 8-15 Load / Random Load Program Data Instruction
- 45 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.15 Quad Load Program Data (32h) / Quad Random Load Program Data (34h)
The “Quad Load Program Data” and “Quad Random Load Program Data” instructions are identical to
the “Load Program Data” and “Random Load Program Data” in terms of operation sequence and
functionality. The only difference is that “Quad Load” instructions will input the data bytes from all four
IO pins instead of the single DI pin. This method will significantly shorten the data input time when a
large amount of data needs to be loaded into the Data Buffer. The instruction sequence is shown in
below.
Both “Quad Load Program Data” and “Quad Random Load Program Data” instructions share the same
command sequence. The difference is that “Quad Load Program Data” instruction will reset the unused
the data bytes in the Data Buffer to FFh value, while “Quad Random Load Program Data” instruction
will only update the data bytes that are specified by the command input sequence, the rest of the Data
Buffer will remain unchanged.
When WP-E bit in the Status Register is set to a 1, all Quad SPI instructions are disabled.
/CS
Mode 3
CLK
0
7
8
DO
(IO1)
IO2
IO3
24
25
26
27
Mode 3
Mode 0
Column
Addr[15:0]
Instruction
DI
(IO0)
23
Mode 0
32h / 34h
15
High Impedance
High Impedance
High Impedance
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
Data
0
Data
1
Data
2111
Figure 8-16 Quad Load / Quad Random Load Program Data Instruction
- 46 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.16
Program Execute (10h)
The Program Execute instruction is the second step of the Program operation. After the program data
are loaded into the 2,112-Byte Data Buffer (or 2,048 bytes when ECC is enabled), the Program Execute
instruction will program the Data Buffer content into the physical memory page that is specified in the
instruction. The instruction is initiated by driving the /CS pin low then shifting the instruction code “10h”
followed by 8-bits dummy clocks and the 16-bits Page Address into the DI pin.
After /CS is driven high to complete the instruction cycle, the self-timed Program Execute instruction
will commence for a time duration of tPP (See AC Characteristics). While the Program Execute cycle is
in progress, the Read Status Register instruction may still be used for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Program Execute cycle and becomes a 0 when the cycle is finished
and the device is ready to accept other instructions again. After the Program Execute cycle has finished,
the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Program Execute instruction
will not be executed if the addressed page is protected by the Block Protect (TB, BP3, BP2, BP1, and
BP0) bits.
The pages within the block have to be programmed sequentially from the lower order page address to
the higher order page address within the block. Programming pages out of sequence is prohibited.
/CS
Mode 3
CLK
0
7
DO
(IO1)
9
15
16
17
29
30
31
Mode 3
Mode 0
Instruction
DI
(IO0)
8
Mode 0
10h
8 Dummy
Clocks
Page Address[15:0]
15
14
13
2
1
0
High Impedance
Figure 8-17 Program Execute Instruction
- 47 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.17
Page Data Read (13h)
The Page Data Read instruction will transfer the data of the specified memory page into the 2,112-Byte
Data Buffer. The instruction is initiated by driving the /CS pin low then shifting the instruction code “13h”
followed by 8-bits dummy clocks and the 16-bits Page Address into the DI pin.
After /CS is driven high to complete the instruction cycle, the self-timed Read Page Data instruction will
commence for a time duration of tRD1 or tRD2 (See AC Characteristics). While the Read Page Data
cycle is in progress, the Read Status Register instruction may still be used for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Read Page Data cycle and becomes a 0 when the cycle
is finished and the device is ready to accept other instructions again.
After the 2,112 bytes of page data are loaded into the Data Buffer, several Read instructions can be
issued to access the Data Buffer and read out the data. Depending on the BUF bit setting in the Status
Register, either “Buffer Read Mode” or “Continuous Read Mode” may be used to accomplish the read
operations.
/CS
Mode 3
CLK
0
7
DO
(IO1)
9
15
16
17
29
30
31
Mode 3
Mode 0
Instruction
DI
(IO0)
8
Mode 0
13h
8 Dummy
Clocks
Page Address[15:0]
15
14
13
2
1
0
High Impedance
Figure 8-18 Page Data Read Instruction
- 48 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.18
Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the Data Buffer
after executing the Read Page Data instruction. The Read Data instruction is initiated by driving the /CS
pin low and then shifting the instruction code “03h” followed by the 16-bits Column Address and 8-bits
dummy clocks or a 24-bits dummy clocks into the DI pin. After the address is received, the data byte of
the addressed Data Buffer location will be shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first. The address is automatically incremented to the next higher address after
each byte of data is shifted out allowing for a continuous stream of data. The instruction is completed
by driving /CS high.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
31
32
38
39
40
46
47
Mode 0
Instruction
DI
(IO0)
8 Dummy
Clocks
Column Address[15:0]
03h
15
14
13
2
1
Data Out 1
High Impedance
DO
(IO1)
Data Out 2
0
7
*
6
1
0
7
6
1
0
*
* = MSB
7
*
Figure 8-19 Read Data Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
8
9
29
30
31
32
38
39
40
46
47
Mode 0
24 Dummy Clocks
Data Out 1
Data Out 2
03h
High Impedance
7
*
6
1
* = MSB
0
7
*
6
1
0
7
*
Figure 8-20 Read Data Instruction (Continuous Read Mode, BUF=0)
- 49 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.19 Fast Read (0Bh)
The Fast Read instruction allows one or more data bytes to be sequentially read from the Data Buffer
after executing the Read Page Data instruction. The Fast Read instruction is initiated by driving the /CS
pin low and then shifting the instruction code “0Bh” followed by the 16-bits Column Address and 8-bits
dummy clocks or a 32-bits dummy clocks into the DI pin. After the address is received, the data byte of
the addressed Data Buffer location will be shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first. The address is automatically incremented to the next higher address after
each byte of data is shifted out allowing for a continuous stream of data. The instruction is completed
by driving /CS high.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
31
32
38
39
40
46
47
Mode 0
Instruction
DI
(IO0)
8 Dummy
Clocks
Column Address[15:0]
0Bh
15
14
13
2
1
Data Out 1
High Impedance
DO
(IO1)
Data Out 2
0
7
*
6
1
0
7
6
1
0
*
* = MSB
7
*
Figure 8-21 Fast Read Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
8
9
21
22
23
39
40
46
47
48
54
55
Mode 0
32 Dummy Clocks
Data Out 1
Data Out 2
0Bh
High Impedance
7
*
6
1
0
* = MSB
7
*
6
1
0
7
*
Figure 8-22 Fast Read Instruction (Continuous Read Mode, BUF=0)
- 50 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.20 Fast Read with 4-Byte Address (0Ch)
The Fast Read instruction allows one or more data bytes to be sequentially read from the Data Buffer
after executing the Read Page Data instruction. The Fast Read instruction is initiated by driving the /CS
pin low and then shifting the instruction code “0Ch” followed by the 16-bits Column Address and 24-bits
dummy clocks (when BUF=1) or 40-bits dummy clocks (when BUF=0) into the DI pin. After the address
is received, the data byte of the addressed Data Buffer location will be shifted out on the DO pin at the
falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to
the next higher address after each byte of data is shifted out allowing for a continuous stream of data.
The instruction is completed by driving /CS high.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
47
48
54
55
56
62
63
Mode 0
Instruction
DI
(IO0)
24 Dummy
Clocks
Column Address[15:0]
0Ch
15
14
13
2
1
Data Out 1
0
High Impedance
DO
(IO1)
Data Out 2
7
*
6
1
0
7
6
1
0
*
* = MSB
7
*
Figure 8-23 Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
8
9
21
22
23
47
48
54
55
56
62
63
Mode 0
40 Dummy Clocks
Data Out 1
Data Out 2
0Ch
High Impedance
7
*
6
1
0
* = MSB
7
6
*
1
0
7
*
Figure 8-24 Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
- 51 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.21 Fast Read Dual Output (3Bh)
The Fast Read Dual Output instruction is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
31
32
33
34
35
36
37
38
39
40
Mode 0
Instruction
DI
(IO0)
8 Dummy
Clocks
Column Address[15:0]
3Bh
15
14
13
2
1
Data Out 1
0
High Impedance
DO
(IO1)
Data Out 2
6
4
2
0
6
4
2
0
6
7
5
3
1
7
5
3
1
7
*
*
* = MSB
*
Figure 8-25 Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
8
9
21
22
23
39
40
41
42
43
44
45
46
47
48
Mode 0
32 Dummy Clocks
3Bh
High Impedance
Data Out 1
Data Out 2
6
4
2
0
6
4
2
0
6
7
5
3
1
7
5
3
1
7
*
* = MSB
*
*
Figure 8-26 Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0)
- 52 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.22
Fast Read Dual Output with 4-Byte Address (3Ch)
The Fast Read Dual Output instruction is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
47
48
49
50
51
52
53
54
55
56
Mode 0
Instruction
DI
(IO0)
24 Dummy
Clocks
Column Address[15:0]
3Ch
15
14
13
2
1
Data Out 1
0
High Impedance
DO
(IO1)
Data Out 2
6
4
2
0
6
4
2
0
6
7
5
3
1
7
5
3
1
7
*
*
* = MSB
*
Figure 8-27 Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
8
9
29
30
31
47
48
49
50
51
52
53
54
55
56
Mode 0
40 Dummy Clocks
3Ch
High Impedance
Data Out 1
Data Out 2
6
4
2
0
7
5
3
1
*
* = MSB
6
4
2
0
7
5
3
1
*
6
7
*
Figure 8-28 Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
- 53 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.23
Fast Read Quad Output (6Bh)
The Fast Read Quad Output instruction is similar to the Fast Read Dual Output (3Bh) instruction except
that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status Register-2
must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read
Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
31
32
33
34
35
36
37
38
39
40
Mode 0
Instruction
DI
(IO0)
8 Dummy
Clocks
Column Address[15:0]
6Bh
15
14
13
2
1
0
High Impedance
DO
(IO1)
High Impedance
IO2
High Impedance
IO3
*
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
Data
Out 5
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
*
= MSB
*
*
*
*
Figure 8-29 Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
IO2
IO3
8
9
21
22
23
39
40
41
42
43
44
45
46
47
48
Mode 0
32 Dummy Clocks
6Bh
High Impedance
High Impedance
High Impedance
* = MSB
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
Data
Out 5
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
*
*
*
*
*
Figure 8-30 Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0)
- 54 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.24
Fast Read Quad Output with 4-Byte Address (6Ch)
The Fast Read Quad Output instruction is similar to the Fast Read Dual Output (3Bh) instruction except
that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status Register-2
must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read
Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
47
48
49
50
51
52
53
54
55
56
Mode 0
Instruction
DI
(IO0)
24 Dummy
Clocks
Column Address[15:0]
6Ch
15
14
13
2
1
0
High Impedance
DO
(IO1)
High Impedance
IO2
High Impedance
IO3
*
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
Data
Out 5
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
*
= MSB
*
*
*
*
Figure 8-31 Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
IO2
IO3
8
9
29
30
31
47
48
49
50
51
52
53
54
55
56
Mode 0
40 Dummy Clocks
6Ch
High Impedance
High Impedance
High Impedance
* = MSB
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
Data
Out 5
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
*
*
*
*
*
Figure 8-32 Fast Read Quad Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
- 55 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.25
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Column Address or the dummy clocks two bits per clock. This reduced instruction overhead
may allow for code execution (XIP) directly from the Dual SPI in some applications.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
Instruction
DI
(IO0)
DO
(IO1)
9
13
14
15
19
20
21
22
23
24
25
26
27
28
Mode 0
4 Dummy
Clocks
Column Address[15:0]
BBh
High Impedance
Data Out 1
Data Out 2
14
12
10
4
2
0
6
4
2
0
6
4
2
0
6
15
13
11
5
3
1
7
5
3
1
7
5
3
1
7
*
*
* = MSB
*
Figure 8-33 Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
8
9
15
16
17
23
24
25
26
27
28
29
30
31
32
Mode 0
16 Dummy Clocks
BBh
High Impedance
Data Out 1
Data Out 2
6
4
2
0
6
4
2
0
6
7
5
3
1
7
5
3
1
7
*
* = MSB
*
*
Figure 8-34 Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0)
- 56 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.26
Fast Read Dual I/O with 4-Byte Address (BCh)
The Fast Read Dual I/O instruction allows for improved random access while maintaining two IO pins,
IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Column Address or the dummy clocks two bits per clock. This reduced instruction overhead may
allow for code execution (XIP) directly from the Dual SPI in some applications.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
Instruction
DI
(IO0)
DO
(IO1)
9
13
14
15
27
28
29
30
31
32
33
34
35
36
Mode 0
12 Dummy
Clocks
Column Address[15:0]
BCh
High Impedance
Data Out 1
Data Out 2
14
12
10
4
2
0
6
4
2
0
6
4
2
0
6
15
13
11
5
3
1
7
5
3
1
7
5
3
1
7
*
*
* = MSB
*
Figure 8-35 Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
8
9
19
20
21
27
28
29
30
31
32
33
34
35
36
Mode 0
20 Dummy Clocks
BCh
High Impedance
Data Out 1
Data Out 2
6
4
2
0
7
5
3
1
*
* = MSB
6
4
2
0
7
5
3
1
*
6
7
*
Figure 8-36 Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
- 57 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.27
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 prior to the data output.
The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will accept the Fast
Read Quad I/O Instruction. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
CLK
0
7
8
DO
(IO1)
IO2
IO3
10
11
12
13
14
15
16
17
18
19
20
21
22
Mode 0
EBh
High Impedance
High Impedance
High Impedance
4 Dummy
Clocks
Column
Address[15:0]
Instruction
DI
(IO0)
9
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
12
8
4
0
4
0
4
0
4
0
4
13
9
5
1
5
1
5
1
5
1
5
14
10
6
2
6
2
6
2
6
2
6
15
11
7
3
7
3
7
3
7
3
7
* = MSB
*
*
*
*
Figure 8-37 Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1)
- 58 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
IO2
IO3
8
9
13
14
15
19
20
21
22
23
24
25
26
27
28
Mode 0
12 Dummy Clocks
EBh
High Impedance
High Impedance
High Impedance
* = MSB
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
Data
Out 5
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
*
*
*
*
*
Figure 8-38 Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0)
- 59 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.28
Fast Read Quad I/O with 4-Byte Address (ECh)
The Fast Read Quad I/O instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 prior to the data output.
The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will accept the Fast
Read Quad I/O Instruction. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
CLK
0
7
8
DO
(IO1)
IO2
IO3
10
11
12
21
ECh
High Impedance
High Impedance
High Impedance
10 Dummy
Clocks
Column
Address[15:0]
Instruction
DI
(IO0)
9
22
23
24
25
25
27
28
Mode 0
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
12
8
4
0
4
0
4
0
4
0
4
13
9
5
1
5
1
5
1
5
1
5
14
10
6
2
6
2
6
2
6
2
6
15
11
7
3
7
3
7
3
7
3
7
* = MSB
*
*
*
*
Figure 8-39 Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
- 60 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
/CS
Mode 3
CLK
0
7
Instruction
DI
(IO0)
DO
(IO1)
IO2
IO3
8
9
15
16
17
21
22
23
24
25
26
27
28
29
30
Mode 0
14 Dummy Clocks
ECh
High Impedance
High Impedance
High Impedance
*
= MSB
Data
Out 1
Data
Out 2
Data
Out 3
Data
Out 4
Data
Out 5
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
*
*
*
*
*
Figure 8-40 Fast Read Quad I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
- 61 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.29
DTR Fast Read (0Dh)
The DTR Fast Read instruction allows one or more data bytes to be sequentially read from the Data
Buffer after executing the Read Page Data instruction. The DTR Fast Read instruction is initiated by
driving the /CS pin low and then shifting the instruction code “0Dh” followed by the 16-bits Column
Address and 8-bits dummy clocks or 16-bits dummy clocks into the DI pin. After the address is received,
the data byte of the addressed Data Buffer location will be shifted out on the DO pin at the both edge
of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher
address after each byte of data is shifted out allowing for a continuous stream of data. The instruction
is completed by driving /CS high.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the
Data Buffer location specified by the 16-bits Column Address and continue to the end of the Data
Buffer. Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from
the first byte of the Data Buffer and increment to the next higher address. When the end of the Data
Buffer is reached, the data of the first byte of next memory page will be following and continues
through the entire memory array. This allows using a single Read instruction to read out the entire
memory array and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
10
13
14
15
23
24
25
26
27
29
28
30
31
Mode 0
Instrustion
DI
(IO0)
15 14 13 12 11 10
0Dh
DO
(IO1)
Dummy
Clocks
Column Address[15:0]
5
4
3
2
1
Data Out 1
Data Out 2
0
High Impedance
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
*
*
* = MSB
Figure 8-41 DTR Fast Read Instruction (Buffer Read Mode, BUF=1)
/CS
CLK
Mode 3
Mode 0
0
7
Instrustion
DI
(IO0)
DO
(IO1)
8
9
10
13
14
15
25
26
27
28
29
30
Data O ut 1
Dummy Cl ocks
31
32
33
Data O ut 2
0Dh
High Impe dance
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
*
* = MSB
*
Figure 8-42 DTR Fast Read Instruction (Continuous Read Mode, BUF=0)
- 62 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.30
DTR Fast Read with 4-Byte Address (0Eh)
The DTR Fast Read instruction allows one or more data bytes to be sequentially read from the Data
Buffer after executing the Read Page Data instruction. The DTR Fast Read instruction is initiated by
driving the /CS pin low and then shifting the instruction code “0Eh” followed by the 16-bits Column
Address and 24-bits dummy clocks or 40-bits dummy clocks into the DI pin. After the address is received,
the data byte of the addressed Data Buffer location will be shifted out on the DO pin at the both edge
of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher
address after each byte of data is shifted out allowing for a continuous stream of data. The instruction
is completed by driving /CS high.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the
Data Buffer location specified by the 16-bits Column Address and continue to the end of the Data
Buffer. Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from
the first byte of the Data Buffer and increment to the next higher address. When the end of the Data
Buffer is reached, the data of the first byte of next memory page will be following and continues
through the entire memory array. This allows using a single Read instruction to read out the entire
memory array and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
CLK
Mode 3
Mode 0
0
7
8
9
Instrustion
DI
(IO0)
0Eh
10
13
14
15
29
Dummy
Clocks
Column Address[15:0]
15 14 13 12 11 10
5
4
30
3
2
1
31
32
33
35
34
Data Out 1
36
37
Data Out 2
0
DO
(IO1)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
＊
＊=MSB
＊
Figure 8-43 DTR Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
CLK
Mode 3
Mode 0
0
7
Instrustion
DI
(IO0)
8
9
10
29
30
31
32
33
34
Data Out 1
Dummy Clocks
35
36
37
Data Out 2
0Eh
DO
(IO1)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
＊
＊=MSB
＊
Figure 8-44 DTR Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
- 63 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.31
DTR Fast Read Dual Output (3Dh)
The DTR Fast Read Dual Output instruction is similar to the DTR Fast Read (0Dh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of the
DTR Fast Read (0Dh) instruction.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
CLK
Mode 3
Mode 0
0
7
8
15
Column
Address[15:0]
Instrustion
DI
(IO0)
14
3Dh
15 14 13
2
Dummy
Clocks
1
24
23
0
DO
(IO1)
25
26
27
Data
Data
Out 1
Out 2
6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
＊
＊=MSB
＊
Figure 8-45 DTR Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1)
/CS
CLK
Mode 3
Mode 0
0
7
Instrustion
DI
(IO0)
8
26
25
Dummy
Clocks
3Dh
DO
(IO1)
27
28
29
Data
Data
Out 1
Out 2
6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
＊
＊=MSB
＊
Figure 8-46 DTR Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0)
- 64 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.32
DTR Fast Read Quad Output (6Dh)
The DTR Fast Read Quad Output instruction is similar to the DTR Fast Read Dual Output (3Dh)
instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in
Status Register-2 must be set to 1 before the device will accept the DTR Fast Read Quad Output
Instruction. The DTR Fast Read Quad Output Instruction allows data to be transferred at four times the
rate of the DTR Fast Read (0Dh) instruction.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
CLK
Mode 3
Mode 0
0
7
Instrustion
DI
(IO0)
6Dh
8
15
23
Column
Address[15:0]
15 14
1
Dummy
Clocks
0
24
25
Data Data
Out 1 Out 2
4 0 4 0
DO
(IO1)
5 1 5 1
IO2
6 2 6 2
7 3 7 3
IO3
＊
＊
＊=MSB
Figure 8-47 DTR Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1)
- 65 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
/CS
CLK
Mode 3
Mode 0
0
7
8
Dummy
Clocks
Instrustion
DI
(IO0)
9
27
28
29
Data Data
Out 1 Out 2
4 0 4 0
6Dh
DO
(IO1)
5 1 5 1
IO2
6 2 6 2
7 3 7 3
IO3
＊
＊
＊=MSB
Figure 8-48 DTR Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0)
- 66 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.33
DTR Fast Read Dual I/O (BDh)
The DTR Fast Read Dual I/O (BDh) instruction allows for improved random access while maintaining
two IO pins, IO0 and IO1. It is similar to the DTR Fast Read Dual Output (3Dh) instruction but with the
capability to input the Column Address or the dummy clocks four bits per clock. This reduced instruction
overhead may allow for code execution (XIP) directly from the Dual SPI in some applications.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from
the first byte of the Data Buffer and increment to the next higher address. When the end of the Data
Buffer is reached, the data of the first byte of next memory page will be following and continues
through the entire memory array. This allows using a single Read instruction to read out the entire
memory array and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
CLK
Mode 3
Mode 0
0
7
8
10
11
Column
Address[15:0]
Instrustion
DI
(IO0)
9
BDh
DO
(IO1)
Dummy
Clocks
14 12 10 8
6
4
2
0
15 13 11 9
7
5
3
1
20
19
21
22
23
Data
Data
Out 1
Out 2
6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
＊
＊=MSB
＊
Figure 8-49 DTR Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1)
/CS
CLK
Mode 3
Mode 0
0
7
Instrustion
DI
(IO0)
8
9
10
11
Dummy
Clocks
BDh
DO
(IO1)
20
19
21
22
23
Data
Data
Out 1
Out 2
6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
＊
＊=MSB
＊
Figure 8-50 DTR Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0)
- 67 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.34
DTR Fast Read Dual I/O with 4-Byte Address (BEh)
The DTR Fast Read Dual I/O instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the DTR Fast Read Dual Output (3Dh) instruction but with the capability
to input the Column Address or the dummy clocks four bits per clock. This reduced instruction overhead
may allow for code execution (XIP) directly from the Dual SPI in some applications.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from
the first byte of the Data Buffer and increment to the next higher address. When the end of the Data
Buffer is reached, the data of the first byte of next memory page will be following and continues
through the entire memory array. This allows using a single Read instruction to read out the entire
memory array and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
/CS
CLK
Mode 3
Mode 0
0
7
8
10
11
BEh
DO
(IO1)
22
21
Column
Address[15:0]
Instrustion
DI
(IO0)
9
Dummy
Clocks
14 12 10 8
6
4
2
0
15 13 11 9
7
5
3
1
23
24
25
Data
Data
Out 1
Out 2
6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
＊
＊=MSB
＊
Figure 8-51 DTR Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
CLK
Mode 3
Mode 0
0
7
Instrustion
DI
(IO0)
8
9
10
11
Dummy
Clocks
BEh
DO
(IO1)
22
21
23
24
25
Data
Data
Out 1
Out 2
6 4 2 0 6 4 2 0
7 5 3 1 7 5 3 1
＊
＊=MSB
＊
Figure 8-52 DTR Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0)
- 68 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.35
DTR Fast Read Quad I/O (EDh)
The DTR Fast Read Quad I/O instruction is similar to the DTR Fast Read Dual I/O (BDh) instruction
except that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 prior to
the data output. The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will
accept the DTR Fast Read Quad I/O Instruction. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
CLK
Mode 3
Mode 0
0
7
9
17
Column
Address[15:0]
Instrustion
DI
(IO0)
8
Dummy
Clocks
18
19
Data Data
Out 1 Out 2
12 8
4
0
4 0 4 0
13 9
5
1
5 1 5 1
IO2
14 10 6
2
6 2 6 2
IO3
15 11 7
3
EDh
DO
(IO1)
7 3 7 3
＊
＊
＊=MSB
Figure 8-53 DTR Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1)
/CS
CLK
Mode 3
Mode 0
0
7
8
Dummy
Clocks
Instrustion
DI
(IO0)
9
18
19
20
Data Data
Out 1 Out 2
4 0 4 0
EDh
DO
(IO1)
5 1 5 1
IO2
6 2 6 2
7 3 7 3
IO3
＊
＊
＊=MSB
Figure 8-54 DTR Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0)
- 69 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.36
DTR Fast Read Quad I/O with 4-Byte Address (EEh)
The DTR Fast Read Quad I/O instruction is similar to the DTR Fast Read Dual I/O (BDh) instruction
except that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 prior to
the data output. The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will
accept the DTR Fast Read Quad I/O Instruction. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
When BUF=1, the device is in the Buffer Read Mode. The data output sequence will start from the Data
Buffer location specified by the 16-bits Column Address and continue to the end of the Data Buffer.
Once the last byte of data is output, the output pin will become Hi-Z state.
When BUF=0, the device is in the Continuous Read Mode, the data output sequence will start from the
first byte of the Data Buffer and increment to the next higher address. When the end of the Data Buffer
is reached, the data of the first byte of next memory page will be following and continues through the
entire memory array. This allows using a single Read instruction to read out the entire memory array
and is also compatible to Winbond’s SpiFlash NOR flash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
CLK
Mode 3
Mode 0
0
7
8
9
20
21
22
12 8
4
0
Dummy Data Data
Clocks Out 1 Out 2
4 0 4 0
13 9
5
1
5 1 5 1
IO2
14 10 6
2
6 2 6 2
IO3
15 11 7
3
Instrustion
DI
(IO0)
DO
(IO1)
EEh
Column
Address[15:0]
7 3 7 3
＊
＊
＊=MSB
Figure 8-55 DTR Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
- 70 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
/CS
CLK
Mode 3
Mode 0
0
7
8
Dummy
Clocks
Instrustion
DI
(IO0)
9
19
20
21
Data Data
Out 1 Out 2
4 0 4 0
EEh
DO
(IO1)
5 1 5 1
IO2
6 2 6 2
7 3 7 3
IO3
＊
＊
＊=MSB
Figure 8-56 DTR Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0)
- 71 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.37 Accessing Unique ID / Parameter / OTP Pages (OTP-E=1)
In addition to the main memory array, the W25N01JW is also equipped with one Unique ID Page, one
Parameter Page, and ten OTP Pages.
Page Address
Page Name
Descriptions
Data Length
00h
01h
02h
…
0Bh
Unique ID Page
Parameter Page
OTP Page [0]
OTP Pages [1:8]
OTP Page [9]
Factory programmed, Read Only
Factory programmed, Read Only
Program Only, OTP lockable
Program Only, OTP lockable
Program Only, OTP lockable
32-Byte x 16
256-Byte x 3
2,112-Byte
2,112-Byte
2,112-Byte
To access these additional data pages, the OTP-E bit in Status Register-2 must be set to “1” first. Then,
Read operations can be performed on Unique ID and Parameter Pages, Read and Program operations
can be performed on the OTP pages if it’s not already locked. To return to the main memory array
operation, OTP-E bit needs to be to set to 0.
Read Operations
A “Page Data Read” command must be issued followed by a specific page address shown in the table
above to load the page data into the main Data Buffer. After the device finishes the data loading
(BUSY=0), all Read commands may be used to read the Data Buffer starting from any specified Column
Address. Please note all Read commands must now follow the “Buffer Read Mode” command structure
(CA[15:0], number of dummy clocks) regardless the previous BUF bit setting. ECC can also be enabled
for the OTP page read operations to ensure the data integrity.
Program and OTP Lock Operations
OTP pages provide the additional space (2K-Byte x 10) to store important data or security information
that can be locked to prevent further modification in the field. These OTP pages are in an erased state
set in the factory, and can only be programmed (change data from “1” to “0”) until being locked by OTPL bit in the Configuration/Status Register-2. OTP-E must be first set to “1” to enable the access to these
OTP pages, then the program data must be loaded into the main Data Buffer using any “Program Data
Load” commands. The “Program Execute” command followed by a specific OTP Page Address is used
to initiate the data transfer from the Data Buffer to the OTP page. When ECC is enabled, ECC
calculation will be performed during “Program Execute”, and the ECC information will be stored into the
64-Byte spare area.
Once the OTP pages are correctly programmed, OTP-L bit can be used to permanently lock these
pages so that no further modification is possible. While still in the “OTP Access Mode” (OTP-E=1), user
needs to set OTP-L bit in the Configuration/Status Register-2 to “1”, and issue a “Program Execute”
command (Page Address is “don’t care”). After the device finishes the OTP lock setting (BUSY=0), the
user can set OTP-E to “0” to return to the main memory array operation.
SR1-L OTP Lock Operation
The Protection/Status Register-1 contains protection bits that can be set to protect either a portion or
the entire memory array from being Programmed/Erased or set the device to either Software Write
Protection (WP-E=0) or Hardware Write Protection (WP-E=1). Once the BP[3:0], TB, WP-E bits are set
correctly, SRP1 and SRP0 should also be set to “1”s as well to allow SR1-L bit being set to “1” to
permanently lock the protection settings in the Status Register-1 (SR1). Similar to the OTP-L setting
procedure above, in order to set SR1-L lock bit, the device must enter the “OTP Access Mode” (OTPE=1) first, and SR1-L bit should be set to “1” prior to the “Program Execute” command (Page Address
is “don’t care”). Once SR1-L is set to “1” (BUSY=0), the user can set OTP-E to “0” to return to the main
memory array operation.
- 72 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
8.2.38
Parameter Page Data Definitions
The Parameter Page contains 3 identical copies of the 256-Byte Parameter Data. The table below lists
all the key data byte locations. All other unspecified byte locations have 00h data as default.
Byte
Number
Descriptions
0~3
4~5
6~7
8~9
10~31
Parameter page signature
Revision number
Feature supported
Optional command supported
Reserved
32~43
Device manufacturer
44~63
Device model
64
65~66
67~79
80~83
84~85
86~91
92~95
96~99
100
101
102
103~104
105~106
107
108~109
110
111
112
113
114
115~127
128
129~132
133~134
135~136
137~138
139~163
164~165
166~253
254~255
256~511
512~767
768~2111
Values
JEDEC manufacturer ID
Date code
Reserved
Number of data bytes per page
Number of spare bytes per page
Reserved
Number of pages per block
Number of blocks per logical unit
Number of logical units
Number of address bytes
Number of bits per cell
Bad blocks maximum per unit
Block endurance
Guaranteed valid blocks at beginning of target
Block endurance for guaranteed valid blocks
Number of programs per page
Reserved
Number of ECC bits
Number of plane address bits
Multi-plane operation attributes
Reserved
I/O pin capacitance, maximum
Reserved
Maximum page program time (us)
Maximum block erase time (us)
Maximum page read time (us)
Reserved
Vendor specific revision number
Vendor specific
Integrity CRC
Value of bytes 0~255
Value of bytes 0~255
Reserved
4Fh, 4Eh, 46h, 49h
00h, 00h
00h, 00h
00h, 00h
All 00h
57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,
20h
57h, 32h, 35h, 4Eh, 30h, 31h, 4Ah, 57h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h
EFh
00h, 00h
All 00h
00h, 08h, 00h, 00h
40h, 00h
All 00h
40h, 00h, 00h, 00h
00h, 04h, 00h, 00h
01h
00h
01h
14h, 00h
01h, 05h
01h
00h, 00h
04h
00h
00h
00h
00h
All 00h
08h
All 00h
BCh, 02h
10h, 27h
3Ch, 00h
All 00h
00h, 00h
All 00h
46h, 44h
- 73 -
Release Date: May 24th, 2021
Revision C
W25N01JWxxxG/T
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings (1)
PARAMETERS
SYMBOL
Supply Voltage
CONDITIONS
VCC
RANGE
UNIT
–0.6 to +2.5
V
Voltage Applied to Any Pin
VIO
Relative to Ground
–0.6 to VCC+0.4
V
Transient Voltage on any Pin
VIOT
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湘ICP备2023018690号
