W25N04KVxxIR/U
3V 4G-BIT
SLC QSPINAND FLASH MEMORY WITH
DUAL/QUAD SPI
BUFFER READ & SEQUENTIAL READ
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
Table of Contents
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTIONS ............................................................................................................. 6
FEATURES ....................................................................................................................................... 6
PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7
3.1
Pad Configuration WSON 8x6-mm ...................................................................................... 7
3.2
Pad Description WSON 8x6-mm .......................................................................................... 7
3.3
Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8
3.4
Ball Description TFBGA 8x6-mm ......................................................................................... 8
PIN DESCRIPTIONS ........................................................................................................................ 9
4.1
Chip Select (/CS) .................................................................................................................. 9
4.2
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................... 9
4.3
Write Protect (/WP)............................................................................................................... 9
4.4
HOLD (/HOLD) ..................................................................................................................... 9
4.5
Serial Clock (CLK) ................................................................................................................ 9
BLOCK DIAGRAM .......................................................................................................................... 10
FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11
6.1
Device Operation Flow ....................................................................................................... 11
6.1.1
6.1.2
6.1.3
6.1.4
7.
Standard SPI Instructions ..................................................................................................... 11
Dual SPI Instructions ............................................................................................................ 11
Quad SPI Instructions .......................................................................................................... 12
Hold Function ....................................................................................................................... 12
6.2
Write Protection .................................................................................................................. 13
PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 14
7.1
Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ......................... 14
7.1.1
7.1.2
7.1.3
7.2
Configuration Register / Status Register-2 (Volatile Writable) ........................................... 16
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
One Time Program Lock Bit (OTP-L) – OTP lockable .......................................................... 16
Enter OTP Access Mode Bit (OTP-E) – Volatile Writable ..................................................... 16
Status Register-1 Lock Bit (SR1-L) – OTP lockable ............................................................. 16
ECC Enable Bit (ECC-E) – Volatile Writable ........................................................................ 17
Output Driver Strength (ODS-1, ODS-0) – Volatile Writable................................................. 19
Hold Disable (H-DIS) - Volatile Writable ............................................................................... 19
Buffer Read / Sequential Read Mode Bit (BUF) - Volatile Writable ...................................... 19
Status Register-3 (Status Only) .......................................................................................... 20
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable ................. 14
Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable ................................. 15
Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable .................... 15
Cumulative ECC Status (ECC-1, ECC-0) – Status Only ...................................................... 20
Program Failure (P-FAIL)– Status Only ................................................................................ 21
Erase Failure (E-FAIL)– Status Only .................................................................................... 21
Write Enable Latch (WEL) – Status Only.............................................................................. 21
Erase/Program In Progress (BUSY) – Status Only .............................................................. 21
Extended Internal ECC feature registers............................................................................ 22
7.4.1
ECC Bit Flip Count Detection (BFD) – Volatile Writable ....................................................... 22
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.4.2
7.4.3
7.4.4
8.
7.5
Reserved Bits – Non Functional ......................................................................................... 24
7.6
W25N04KV Status Register Memory Protection ................................................................ 25
INSTRUCTIONS ............................................................................................................................. 26
8.1
Device ID and Instruction Set Tables ................................................................................. 26
8.1.1
8.1.2
8.1.3
8.2
Manufacturer and Device Identification ................................................................................ 26
Instruction Set Table 1 (Buffer Read, BUF = 1, default) ....................................................... 27
Instruction Set Table 2 (Sequential Read, BUF = 0, ECC-E = 0) ......................................... 28
Instruction Descriptions ...................................................................................................... 30
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.2.16
8.2.17
8.2.18
8.2.19
8.2.20
8.2.21
8.2.22
8.2.23
8.2.24
8.2.25
8.2.26
9.
ECC Bit Flip Count Detection Status (BFS) – Status Only ................................................... 23
ECC Bit Flip Count Report (BFR) – Status Only................................................................... 23
ECC Maximum Bit Flip Count Report (MBF, MFS) – Status Only ........................................ 24
Device Reset (FFh), Enable Reset (66h) and Reset Device (99h) ....................................... 30
Read JEDEC ID (9Fh) .......................................................................................................... 32
Read Status Register (0Fh / 05h) ......................................................................................... 33
Write Status Register (1Fh / 01h) ......................................................................................... 34
Write Enable (06h) ............................................................................................................... 35
Write Disable (04h) ............................................................................................................... 35
128KB Block Erase (D8h)..................................................................................................... 36
Load Program Data (02h) / Random Load Program Data (84h) ........................................... 37
Quad Load Program Data (32h) / Quad Random Load Program Data (34h) ....................... 38
Program Execute (10h) ...................................................................................................... 39
Page Data Read (13h)........................................................................................................ 40
Read Data (03h) ................................................................................................................. 41
Fast Read (0Bh) ................................................................................................................. 42
Fast Read with 4-Byte Address (0Ch) ................................................................................ 43
Fast Read Dual Output (3Bh) ............................................................................................. 44
Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 45
Fast Read Quad Output (6Bh)............................................................................................ 46
Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 47
Fast Read Dual I/O (BBh)................................................................................................... 48
Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 49
Fast Read Quad I/O (EBh) ................................................................................................. 50
Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................ 52
Accessing Unique ID / Parameter / OTP Pages (OTP-E=1) ............................................... 54
Parameter Page Data Definitions ....................................................................................... 55
Deep Power-Down (B9h).................................................................................................... 56
Release Power-Down (ABh)............................................................................................... 57
ELECTRICAL CHARACTERISTICS............................................................................................... 58
9.1
Absolute Maximum Ratings(1) ............................................................................................. 58
9.2
Operating Ranges .............................................................................................................. 58
9.3
Power-up Power-down Timing Requirements .................................................................... 59
9.4
DC Electrical Characteristics .............................................................................................. 60
9.5
AC Measurement Conditions ............................................................................................. 61
9.6
AC Electrical Characteristics(3) ........................................................................................... 62
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
10.
11.
12.
13.
9.7
Serial Output Timing ........................................................................................................... 64
9.8
Serial Input Timing.............................................................................................................. 64
9.9
/HOLD Timing ..................................................................................................................... 64
9.10 /WP Timing ......................................................................................................................... 64
INVALID BLOCK MANAGEMENT .................................................................................................. 65
10.1 Invalid Blocks...................................................................................................................... 65
10.2 Initial Invalid Blocks ............................................................................................................ 65
10.3 Error in Operation ............................................................................................................... 66
10.4 Addressing in Program Operation ...................................................................................... 66
PACKAGE SPECIFICATIONS ....................................................................................................... 67
11.1 8-Pad WSON 8x6-mm (Package Code ZE) ....................................................................... 67
11.2 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array) ......................................... 68
11.3 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 Ball Array) ............................................ 69
ORDERING INFORMATION .......................................................................................................... 70
12.1 Valid Part Numbers and Top Side Marking ........................................................................ 71
REVISION HISTORY ...................................................................................................................... 72
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
Table of Figures
Figure 1a. W25N04KV Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE)............................... 7
Figure 1b. W25N04KV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC) ................... 8
Figure 2. W25N04KV Flash Memory Architecture and Addressing ............................................................ 10
Figure 3. W25N04KV Flash Memory Operation Diagram ........................................................................... 11
Figure 4a. Protection Register / Status Register-1 (Address Axh) ............................................................. 14
Figure 4b. Configuration Register / Status Register-2 (Address Bxh) ........................................................ 16
Figure 4c. Status Register-3 (Address Cxh) ............................................................................................... 20
Figure 4d. Extended Internal ECC feature registers ................................................................................... 22
Figure 5a. Device Reset Instruction ............................................................................................................ 30
Figure 5b. Enable Reset and Reset Instruction Sequence ......................................................................... 30
Figure 5c. Default values of the Status Registers after power up and Device Reset ................................. 31
Figure 6. Read JEDEC ID Instruction ......................................................................................................... 32
Figure 7. Read Status Register Instruction ................................................................................................. 33
Figure 8. Write Status Register-1/2/3 Instruction ........................................................................................ 34
Figure 9. Write Enable Instruction ............................................................................................................... 35
Figure 10. Write Disable Instruction ............................................................................................................ 35
Figure 11. 128KB Block Erase Instruction .................................................................................................. 36
Figure 12. Load / Random Load Program Data Instruction ........................................................................ 37
Figure 13. Quad Load / Quad Random Load Program Data Instruction .................................................... 38
Figure 14. Program Execute Instruction ..................................................................................................... 39
Figure 15. Page Data Read Instruction ....................................................................................................... 40
Figure 16a. Read Data Instruction (Buffer Read Mode, BUF=1) ................................................................ 41
Figure 16b. Read Data Instruction (Sequential Read Mode, BUF=0) ........................................................ 41
Figure 17a. Fast Read Instruction (Buffer Read Mode, BUF=1) ................................................................ 42
Figure 17b. Fast Read Instruction (Sequential Read Mode, BUF=0) ......................................................... 42
Figure 18a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ............................... 43
Figure 18b. Fast Read with 4-Byte Address Instruction (Sequential Read Mode, BUF=0) ........................ 43
Figure 19a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1) ............................................ 44
Figure 19b. Fast Read Dual Output Instruction (Sequential Read Mode, BUF=0) ..................................... 44
Figure 20a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ........... 45
Figure 20b. Fast Read Dual Output with 4-Byte Address Instruction (Sequential Read Mode, BUF=0) ... 45
Figure 21a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) ........................................... 46
Figure 21b. Fast Read Quad Output Instruction (Sequential Read Mode, BUF=0) ................................... 46
Figure 22a. Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ......... 47
Figure 22b. Fast Read Quad Output with 4-Byte Address Instruction (Sequential Read Mode, BUF=0) .. 47
Figure 23a. Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1) .................................................. 48
Figure 23b. Fast Read Dual I/O Instruction (Sequential Read Mode, BUF=0) ........................................... 48
Figure 24a. Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................. 49
Figure 24b. Fast Read Dual I/O with 4-Byte Address Instruction (Sequential Read Mode, BUF=0) ......... 49
Figure 25a. Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1) ................................................. 50
Figure 25b. Fast Read Quad I/O Instruction (Sequential Read Mode, BUF=0) ......................................... 51
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
Figure 26a. Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)................ 52
Figure 26b. Fast Read Quad I/O with 4-Byte Address Instruction (Sequential Read Mode, BUF=0) ........ 53
Figure 27. Deep Power-Down Instruction ................................................................................................... 56
Figure 28. Release Power-down Instruction ............................................................................................... 57
Figure 29. Power-up Timing and Voltage Levels ........................................................................................ 59
Figure 30. Power-up, Power-Down Requirement ....................................................................................... 59
Figure 31. AC Measurement I/O Waveform ................................................................................................ 61
Figure 32. Flow Chart of Create Initial Invalid Block Table ......................................................................... 65
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
1. GENERAL DESCRIPTIONS
The W25N04KV (4G-bit) SLC QspiNAND Flash Memory provides a storage solution for systems with limited
space, pins and power. The W25N QspiNAND family incorporates the popular SPI interface and the
traditional large NAND non-volatile memory space. They are ideal for code shadowing to RAM, executing
code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single
2.7V to 3.6V power supply with current consumption as low as 25mA active, 10µA for standby and 1µA for
deep power down. All W25N QspiNAND family devices are offered in space-saving packages which were
impossible to use in the past for the typical NAND flash memory.
The W25N04KV 4G-bit memory array is organized into 262,144 programmable pages of 2,048-bytes each.
The entire page can be programmed at one time using the data from the 2,048-Byte internal buffer. Pages
can be erased in groups of 64 (128KB block erase). The W25N04KV has 2,048 erasable blocks.
The W25N04KV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock,
Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to
104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz
(104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions.
The W25N04KV provides a new Sequential Read Mode that allows for efficient access to the entire memory
array with a single Read command.
A Hold pin, Write Protect pin and programmable write protection, provide further control flexibility.
Additionally, the device supports JEDEC standard manufacturer and device ID, one Unique ID page, one
parameter page and ten 2,048-Byte OTP pages. To provide better NAND flash memory manageability, user
configurable internal ECC is also available in W25N04KV.
2. FEATURES
New W25N Family of QspiNAND
Memories
– W25N04KV: 4G-bit / 512M-Byte
– Standard SPI: CLK, /CS, DI, DO, /WP,
/Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Compatible SPI serial flash commands
Highest Performance Serial NAND Flash
– 104MHz Standard/Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/S sequential data transfer rate
– Fast Program/Erase performance
– 60,000 erase/program cycles
– 10-year data retention
Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 25mA active, 20µA standby, 2µA DPD(3)
– -40°C to +85°C/105°C(4) operating range
Flexible Architecture with 128KB blocks
– Uniform 128K-Byte Block Erase
– Flexible page data load methods
Advanced Features
– On chip 8-Bit ECC for memory array
– ECC status bits indicate ECC results
– Software and Hardware Write-Protect
– Power Supply Lock-Down and OTP protection
– Unique ID and parameter pages(1)
– Ten 2KB OTP pages(2)
Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 24-ball TFBGA 8x6-mm
– Contact Winbond for other package options
Notes:
1.
2.
3.
4.
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Please refer to 8.2.23 and 8.2.24 for detail information
OTP pages can only be programmed.
DPD stands for Deep Power Down.
105°C is supported in Industrial Plus Grade.
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W25N04KV is offered in an 8-pad WSON 8x6-mm (package code ZE) and two 24-ball 8x6-mm TFBGA
(package code TB & TC) packages as shown in Figure 1a-b respectively. Package diagrams and
dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
Top View
/CS
1
8
VCC
DO (IO1)
2
7
/HOLD (IO3)
/WP (IO2)
3
6
CLK
GND
4
5
DI (IO0)
Figure 1a. W25N04KV Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE)
3.2
Pad Description WSON 8x6-mm
PAD NO.
PAD NAME
I/O
FUNCTION
1
/CS
I
2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
3
/WP (IO2)
I/O
Write Protect Input ( Data Input Output 2)(2)
4
GND
5
DI (IO0)
Chip Select Input
Ground
I/O
6
CLK
I
7
/HOLD (IO3)
I/O
8
VCC
Data Input (Data Input Output 0)(1)
Serial Clock Input
Hold Input (Data Input Output 3)(2)
Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
3.3
Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Top View
Top View
A2
A3
A4
A5
A1
A2
A3
A4
NC
NC
NC
NC
NC
NC
NC
NC
B1
B2
B3
B4
B1
B2
B3
B4
B5
NC
CLK
GND
VCC
NC
CLK
GND
VCC
NC
C1
C2
C3
C4
C1
C2
C3
C4
C5
NC
/CS
NC
/WP (IO2)
D3
D4
NC
/CS
NC
/WP (IO2)
NC
D1
D2
D1
D2
D3
D4
D5
NC
DO(IO1)
NC
DO(IO1)
NC
E1
E2
E3
E4
E1
E2
E3
E4
E5
NC
NC
NC
NC
NC
NC
NC
NC
NC
DI(IO0) /HOLD(IO3)
DI(IO0) /HOLD(IO3)
F1
F2
F3
F4
NC
NC
NC
NC
Package Code B
Package Code C
Figure 1b. W25N04KV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC)
3.4
Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
I/O
FUNCTION
B2
CLK
I
B3
GND
Ground
B4
VCC
Power Supply
C2
/CS
I
C4
/WP (IO2)
I/O
Write Protect Input (Data Input Output 2)(2)
D2
DO (IO1)
I/O
Data Output (Data Input Output 1)(1)
D3
DI (IO0)
I/O
Data Input (Data Input Output 0)(1)
D4
/HOLD (IO3)
I/O
Hold Input (Data Input Output 3)(2)
Multiple
NC
Serial Clock Input
Chip Select Input
No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal page read, erase,
program or write status register cycle is in progress. When /CS is brought low the device will be selected,
power consumption will increase to active levels and instructions can be written to and data read from the
device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The
/CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
33b). If needed, a pull-up resistor on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25N04KV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data
or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data
to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect bits BP[3:0] and Status Register Protect SRP bits
SRP[1:0], a portion as small as 512KB, four Blocks or up to the entire memory array can be hardware
protected. The WP-E bit in the Protection Register (SR-1) controls the functions of the /WP pin.
When WP-E=0, the device is in the Software Protection mode that only SR-1 can be protected. The /WP
pin functions as a data I/O pin for the Quad SPI operations, as well as an active low input pin for the Write
Protection function for SR-1. Refer to section 7.1.3 for detail information.
When WP-E=1, the device is in the Hardware Protection mode that /WP becomes a dedicated active low
input pin for the Write Protection of the entire device. If /WP is tied to GND, all “Write/Program/Erase”
functions are disabled. The entire device (including all registers, memory array, OTP pages) will become
read-only. Quad SPI read operations are also disabled when WP-E is set to 1.
4.4 HOLD (/HOLD)
During Standard and Dual SPI operations, the /HOLD pin allows the device to be paused while it is actively
selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can
resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The
/HOLD pin is active low.
When a Quad SPI Read/Buffer Load command is issued, /HOLD pin will become a data I/O pin for the
Quad operations and no HOLD function is available until the current Quad operation finishes. /HOLD (IO3)
must be driven high by the host, or an external pull-up resistor must be placed on the PCB, in order to avoid
allowing the /HOLD input to float.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. (“See SPI
Operations”)
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
5. BLOCK DIAGRAM
Address Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
64KB block address
Page address
SpiFlash(up to 128Mbit) X X X X X X X X
64KB block address
Page address
SpiFlash(up to 32Gbit)
Page address (PA) [17:0]
X X
QspiNAND(4Gbit)
128KB block address (4096 blocks)
Page address (64 Pages)
X X
9
8
7
6
5 4 3 2
Byte address
Byte address
Column address [11:0]
Byte address (0-2175 byte)
1
0
Figure 2. W25N04KV Flash Memory Architecture and Addressing
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
6.
FUNCTIONAL DESCRIPTIONS
6.1 Device Operation Flow
Figure 3. W25N04KV Flash Memory Operation Diagram
6.1.1 Standard SPI Instructions
The W25N04KV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO
output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising
edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.1.2 Dual SPI Instructions
The W25N04KV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
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W25N04KVxxIR/U
code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become
bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Instructions
The W25N04KV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh/6Ch)”, “Fast Read Quad I/O (EBh/ECh)” and “Quad Program Data Load (32h/34h)”. These instructions
allow data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The
Quad Read instructions offer a significant improvement in random access transfer rates allowing fast codeshadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI
and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3
respectively.
6.1.4 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25N04KV operation to be paused
while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI
data and clock signals are shared with other devices. For example, consider if the page buffer was only
partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can
save the state of the instruction and the data in the buffer so programming can resume where it left off once
the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation,
not during Quad SPI. When a Quad SPI command is issued, /HOLD pin will act as a dedicated IO pin (IO3).
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising
edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition
will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS)
signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal
logic state of the device.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
6.2
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25N04KV
provides several means to protect the data from inadvertent writes.
Device resets when VCC is below threshold
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Protection Register (SR-1)
Lock Down write protection for Protection Register (SR-1) until the next power-up
One Time Program (OTP) write protection for memory array using Protection Register (SR-1)
Hardware write protection using /WP pin when WP-E is set to 1
Upon power-up or at power-down, while VCC is below VCC(min), (see “Power-up Power-down Timing
Requirements”), all operations are disabled and no instructions are recognized. During power-up, after the
VCC voltage exceeds VCC(min) and tVSL has elapsed, all program and erase related instructions are
further disabled for a time delay of tPUW. This includes the Write Enable, Program Execute, Block Erase
and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply
level at power-up until the VCC-min level and tVSL time delay is reached, and it must also track the VCC
supply level at power-down to prevent adverse command sequence. If needed a pull-up resister on /CS
can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Program Execute or
Block Erase instruction will be accepted. After completing a program or erase instruction the Write Enable
Latch (WEL) is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (TB, BP[3:0]) bits. These settings allow a portion
or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP)
pin, changes to the Status Register can be enabled or disabled under hardware control. See Protection
Register section for further information.
The WP-E bit in Protection Register (SR-1) is used to enable the hardware protection. When WP-E is set
to 1, bringing /WP low in the system will block any Write/Program/Erase command to the W25N04KV, the
device will become read-only. The Quad SPI operations are also disabled when WP-E is set to 1.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.
PROTECTION, CONFIGURATION AND STATUS REGISTERS
Three Status Registers are provided for W25N04KV: Protection Register (SR-1), Configuration Register
(SR-2) & Status Register (SR-3). Each register is accessed by Read Status Register and Write Status
Register commands combined with 1-Byte Register Address respectively.
The Read Status Register instruction (05h / 0Fh) can be used to provide status on the availability of the
flash memory array, whether the device is write enabled or disabled, the state of write protection, Read
modes, Protection Register/OTP area lock status, Erase/Program results, ECC usage/status. The Write
Status Register instruction can be used to configure the device write protection features, Software/Hardware
write protection, Read modes, enable/disable ECC, Protection Register/OTP area lock. Write access to the
Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the
Write Enable instruction, and when WP-E is set to 1, the /WP pin.
7.1
Protection Register / Status Register-1 (Volatile Writable, OTP lockable)
Figure 4a. Protection Register / Status Register-1 (Address Axh)
7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable
The Block Protect bits (BP3, BP2, BP1, BP0 & TB) are volatile read/write bits in the status register-1 (S6,
S5, S4, S3 & S2) that provide Write Protection control and status. Block Protect bits can be set using the
Write Status Register Instruction. All, none or a portion of the memory array can be protected from Program
and Erase instructions (see Status Register Memory Protection table). The default values for the Block
Protection bits are 1 after power up to protect the entire array. If the SR1-L bit in the Configuration Register
(SR-2) is set to 1, the default values will the values that are OTP locked.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.1.2 Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable
The Write Protection Enable bit (WP-E) is a volatile read/write bits in the status register-1 (S1). The WP-E
bit, in conjunction with SRP1 & SRP0, controls the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection, /WP pin functionality, and
Quad SPI operation enable/disable. When WP-E = 0 (default value), the device is in Software Protection
mode, /WP & /HOLD pins are multiplexed as IO pins, and Quad program/read functions are enabled all the
time. When WP-E is set to 1, the device is in Hardware Protection mode, all Quad functions are disabled
and /WP & /HOLD pins become dedicated control input pins.
7.1.3 Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable
The Status Register Protect bits (SRP1 and SRP0) are volatile read/write bits in the status register (S0 and
S7). The SRP bits control the method of write protection: software protection, hardware protection, power
supply lock-down or one time programmable (OTP) protection.
Software Protection (Driven by Controller, Quad Program/Read is enabled)
SRP1
SRP0
WP-E
/WP / IO2
Descriptions
0
0
0
X
No /WP functionality
/WP pin will always function as IO2
0
1
0
0
SR-1 cannot be changed (/WP = 0 during Write Status)
/WP pin will function as IO2 for Quad operations
0
1
0
1
SR-1 can be changed (/WP = 1 during Write Status)
/WP pin will function as IO2 for Quad operations
1
0
0
X
Power Lock Down(1) SR-1
/WP pin will always function as IO2
1
1
0
X
Enter OTP mode to protect SR-1 (allow SR1-L=1)
/WP pin will always function as IO2
Hardware Protection (System Circuit / PCB layout, Quad Program/Read is disabled)
SRP1
SRP0
WP-E
/WP only
Descriptions
0
X
1
VCC
SR-1 can be changed
1
0
1
VCC
Power Lock-Down(1) SR-1
1
1
1
VCC
Enter OTP mode to protect SR-1 (allow SR1-L=1)
X
X
1
GND
All “Write/Program/Erase” commands are blocked
Entire device (SRs, Array, OTP area) is read-only
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.2
Configuration Register / Status Register-2 (Volatile Writable)
Figure 4b. Configuration Register / Status Register-2 (Address Bxh)
7.2.1 One Time Program Lock Bit (OTP-L) – OTP lockable
In addition to the main memory array, W25N04KV also provides an OTP area for the system to store critical
data that cannot be changed once it’s locked. The OTP area consists of 10 pages of 2,176-Byte each. The
default data in the OTP area are FFh. Only Program command can be issued to the OTP area to change
the data from “1” to “0”, and data is not reversible (“0” to “1”) by the Erase command. Once the correct data
is programmed in and verified, the system developer can set OTP-L bit to 1, so that the entire OTP area
will be locked to prevent further alteration to the data.
7.2.2 Enter OTP Access Mode Bit (OTP-E) – Volatile Writable
The OTP-E bit must be set to 1 in order to use the standard Program/Read commands to access the OTP
area as well as to read the Unique ID / Parameter Page information. The default value after power up or a
RESET command is 0.
7.2.3 Status Register-1 Lock Bit (SR1-L) – OTP lockable
The SR1-L lock bit is used to OTP lock the values in the Protection Register (SR-1). Depending on the
settings in the SR-1, the device can be configured to have a portion of or up to the entire array to be writeprotected, and the setting can be OTP locked by setting SR1-L bit to 1. SR1-L bit can only be set to 1
permanently when SRP1 & SRP0 are set to (1,1), and OTP Access Mode must be entered (OTP-E=1) to
execute the programming. Please refer to 10.2.23 for detailed information.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.2.4 ECC Enable Bit (ECC-E) – Volatile Writable
W25N04KV has a built-in ECC algorithm that can be used to preserve the data integrity. Internal ECC
calculation is done during page programming, and the result is stored in the extra 64-Byte area for each
page. During the data read operation, ECC engine will verify the data values according to the previously
stored ECC information and to make necessary corrections if needed. The verification and correction status
is indicated by the ECC Status Bits. ECC function is enabled by default when power on (ECC-E=1), and it
will not be reset to 0 by the Device Reset command.
The constraint when ECC-E=1 are as follows:
The areas protected by ECC is shown in the table below. User Data I is protected by ECC, but User
Data II is out of protected by ECC.
The Number of Partial Page Program (NoP) is 4 for the entire page, including the spare area and parity
area. Therefore the user needs to program one sector and User Data I of pared spare area (example,
main area-sector 0 and spare area-spare 0) at one time program to properly and automatically program
the ECC parity area.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
Area
Sector 0
Address
(Start)
Address
(End)
Size
Area
Address
(Start)
Address
(End)
Size
Area
Address
(Start)
Address
(End)
Size
Main area
Sector 1
Sector 2
Sector 3
000h
200h
400h
600h
1FFh
3FFh
5FFh
7FFh
512B
512B
512B
512B
Spare 0
UD2
UD1
Spare area
Spare 1
Spare 2
UD2
UD1
UD2
UD1
Spare 3
UD2
UD1
800h
804h
810h
814h
820h
824h
830h
834h
803h
80Fh
813h
81Fh
823h
82Fh
833h
83Fh
4B
12B
4B
12B
4B
12B
4B
12B
Parity 0
EPC
NU
Parity area
Parity 1
Parity 2
EPC
NU
EPC
NU
Parity 3
EPC
NU
840h
84Dh
850h
85Dh
860h
86Dh
870h
87Dh
84Ch
84Fh
85Ch
85Fh
86Ch
86Fh
87Ch
87Fh
13B
3B
13B
3B
13B
3B
13B
3B
Notes:
1. UD2: User Data II
2. UD1: User Data I
3. EPC: ECC Parity Code
4. NU: Not Use
The gray area of the above table is protected by ECC
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.2.5 Output Driver Strength (ODS-1, ODS-0) – Volatile Writable
ODS-1, ODS-0
Output driver strength
NMOS RonI
PMOS RonI
0, 0
Set 1 (default)
40 Ω
55 Ω
0, 1
Set 2
45 Ω
65 Ω
1, 0
Set 3
55 Ω
90 Ω
1, 1
Set 4
95 Ω
155 Ω
7.2.6 Hold Disable (H-DIS) – Volatile Writable
When the Hold Disable (H-DIS) bit set to 1, the hold function would be disabled.
7.2.7 Buffer Read / Sequential Read Mode Bit (BUF) – Volatile Writable
W25N04KV provides two different modes for read operations, Buffer Read Mode (BUF=1) and Sequential
Read Mode without ECC mode (BUF=0, ECC-E = 0). Prior to any Read operation, a Page Data Read
command is needed to initiate the data transfer from a specified page in the memory array to the Data
Buffer. By default, after power up, the data in page 0 will be automatically loaded into the Data Buffer and
the device is ready to accept any read commands.
The Buffer Read Mode (BUF=1) requires a Column Address to start outputting the existing data inside the
Data Buffer, and once it reaches the end of the data buffer (Byte 2,176), DO (IO1) pin will become high-Z
state.
The Sequential Read Mode without ECC mode (BUF=0, ECC-E = 0) doesn’t require the starting Column
Address. The device will always start output the data from the first column (Byte 0) of the Data buffer, and
once the end of the data buffer (Byte 2,048 + 128) is reached, the data output will continue through the next
memory page. With Sequential Read Mode, it is possible to read out the entire memory array using a single
read command.
In the Sequential Read Mode without ECC mode, for each read instruction: 03h, 0Bh, 0Ch, 3Bh, 3Ch, 6Bh,
6Ch, BBh, BCh, EBh and ECh, the CA [15:0] address input becomes dummy input. The read must start
from the beginning of the page. During this read mode, there is no built-in ECC algorithm that can be used
to preserve the data integrity.
BUF
ECC-E
Read Mode
(Starting from Buffer)
ECC Status
Data Output Structure
1
0
Buffer Read
N/A
2,048 + 128
1
1
Buffer Read
Page based
2,048 + 128
0
X
Sequential Read
N/A
2,048 + 128
Note:
When BUF set to 0, no matter which setting for ECC-E, there is no built-in ECC algorithm to preserve the data integrity.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.3
Status Register-3 (Status Only)
Figure 4c. Status Register-3 (Address Cxh)
7.3.1 Cumulative ECC Status (ECC-1, ECC-0) – Status Only
ECC function is used in NAND flash memory to correct limited memory errors during read operations. Bit
flips count in as sector equal or less than 8bits would be detected and corrected. The ECC Status Bits
(ECC-1, ECC-0) should be checked after the completion of a Read operation to verify the data integrity.
The ECC Status bits values are don’t care if ECC-E=0. These bits will be cleared to 0 after a power cycle
or a RESET command or a Page Data Read Command.
ECC Status
Descriptions
ECC-1
ECC-0
0
0
0
1
1
0
Multiple bit flips were detected and not corrected.
1
1
Bit flips were detected and corrected. Bit flip count *exceeded the bit flip
detection threshold. Page data refreshment or remove must be taken to
hold data retention.
Entire data output is successful. No bit flips were detected in previous
page read.
Entire data output is successful. Bit flips were detected and corrected.
Bit flip count did not exceed the bit flip detection threshold. The
threshold is set by bits [7:4] in address 10h in the feature table.
*note: Bit flip count > BFD setting
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.3.2 Program Failure (P-FAIL)– Status Only
The Program Failure Bit is used to indicate whether the internally-controlled Program operation was
executed successfully (P-FAIL=0) or timed out (P-FAIL=1). The P-FAIL bit is also set when the Program
command is issued to a locked or protected memory array or OTP area. This bit is cleared at the beginning
of the Program Execute instruction on an unprotected memory array or OTP area. Device Reset instruction
can also clear the P-FAIL bit.
7.3.3 Erase Failure (E-FAIL)– Status Only
The Erase Failure Bit is used to indicate whether the internally-controlled Erase operation was executed
successfully (E-FAIL=0) or timed out (E-FAIL=1). The E-FAIL bit is also set when the Erase command is
issued to a locked or protected memory array. This bit is cleared at the beginning of the Block/Chip Erase
instruction on an unprotected memory array. Device Reset instruction can also clear the E-FAIL bit.
7.3.4 Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable
state occurs upon power-up or after any of the following instructions: Write Disable, Program Execute, Block
Erase, Page Data Read and Program Execute for OTP pages.
7.3.5 Erase/Program In Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is powering up or
executing a Page Data Read, Program Execute, Block Erase. During this time the device will ignore further
instructions except for the Read Status Register and Read JEDEC ID instructions. When the program,
erase or write status register instruction has completed, the BUSY bit will be cleared to a 0 state indicating
the device is ready for further instructions.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.4
Extended Internal ECC feature registers
Address
Bit
S7
S6
S5
S4
S3
S2
S1
S0
10h
BFD3
BFD2
BFD1
BFD0
I
I
I
I
20h
I
I
I
I
BFS3
BFS2
BFS1
BFS0
30h
MBF3
MBF2
MBF1
MBF0
I
MFS2
MFS1
MFS0
40h
BFR7
BFR6
BFR5
BFR4
BFR3
BFR2
BFR1
BFR0
50h
BFR15
BFR14
BFR13
BFR12
BFR11
BFR10
BFR9
BFR8
* I = Reserved Bit
Figure 4d. Extended Internal ECC feature registers
7.4.1 ECC Bit Flip Count Detection (BFD) – Volatile Writable
The ECC Bit Flip Count Detection function detects the bit flip count in a page. The users set the threshold
bit count using the Write Extended Internal ECC feature registers command. The threshold bit count is
decided by the bit flip detection setting bit (BFD) in address 10h in the feature table as shown in Figure 4d.
The detected results will be indicated in the BFS bits (bits [7:0]) in address 20h. When bit flips exceed the
threshold in a sector, the BFS bits are set after the Page Data Read (13h) command with ECC-E = 1. The
setting start from 1 to 7.
BFD3
BFD2
BFD1
BFD0
Description
0
0
0
0
Reserved
0
0
0
1
Detect 1 bit flip in a sector.
0
0
1
0
Detect 2 bit flip in a sector.
0
0
1
1
Detect 3 bit flip in a sector.
0
1
0
0
Detect 4 bit flip in a sector. (default)
0
1
0
1
Detect 5 bit flip in a sector.
0
1
1
0
Detect 6 bit flip in a sector.
0
1
1
1
Detect 7 bit flip in a sector.
1
X
X
X
Reserved
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.4.2 ECC Bit Flip Count Detection Status (BFS) – Status Only
Symbol
Parameter
BFS3
Bit flip count detection
status in sector 3
1
Bit flips count is equal to or more than threshold bit count
0
Bit flips count is less than threshold bit count
Bit flip count detection
status in sector 2
1
Bit flips count is equal to or more than threshold bit count
0
Bit flips count is less than threshold bit count
Bit flip count detection
status in sector 1
1
Bit flips count is equal to or more than threshold bit count
0
Bit flips count is less than threshold bit count
Bit flip count detection
status in sector 0
1
Bit flips count is equal to or more than threshold bit count
0
Bit flips count is less than threshold bit count
BFS2
BFS1
BFS0
Status
Description
7.4.3 ECC Bit Flip Count Report (BFR) – Status Only
The ECC Bit Flip Count Report function reports the bit flip count of each sector in a page. The users can
read the bit flip count using the Read Extended Internal ECC status register command with address 40h
and 50h.
BFR15/11/7/3
BFR14/10/6/2
BFR13/9/5/1
BFR12/8/4/0
Description
0
0
0
0
No bit flip in a sector
0
0
0
1
Detect 1 bit flip in a sector and corrected.
0
0
1
0
Detect 2 bit flips in a sector and corrected.
0
0
1
1
Detect 3 bit flips in a sector and corrected.
0
1
0
0
Detect 4 bit flips in a sector and corrected.
0
1
0
1
Detect 5 bit flips in a sector and corrected.
0
1
1
0
Detect 6 bit flips in a sector and corrected.
0
1
1
1
Detect 7 bit flips in a sector and corrected.
1
0
0
0
Detect 8 bit flips in a sector and corrected.
1
1
1
1
Bit flips over 8 bits in a sector and were not
corrected.
BFR set
Parameter
BFR[15:12]
Bit flip count detection report for sector 3
BFR[11:8]
Bit flip count detection report for sector 2
BFR[7:4]
Bit flip count detection report for sector 1
BFR[3:0]
Bit flip count detection report for sector 0
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.4.4 ECC Maximum Bit Flip Count Report (MBF, MFS) – Status Only
The ECC Maximum Bit Flip Count Report function provides the maximum bit flip count in a page. The
maximum count is indicated in address 30h of the feature table shown in follow table 4d. The sector number
in which the maximum bit flip occurred in a page is indicated in the MFS bit (bits [2:0]) in address 30h as
shown in follow table. When several sector’s maximum bit flip count are the same, the lowest sector number
is indicated in these bits. The users get the report using the Read Extended Internal ECC status register
command.
MBF3
MBF2
MBF1
MBF0
0
0
0
0
No bit error is detected in the page.
0
0
0
1
Maximum bit flip count is 1 bit in a sector. Bit flip was corrected.
0
0
1
0
Maximum bit flip count is 2 bits in a sector. Bit flips were corrected.
0
0
1
1
Maximum bit flip count is 3 bits in a sector. Bit flips were corrected.
0
1
0
0
Maximum bit flip count is 4 bits in a sector. Bit flips were corrected.
0
1
0
1
Maximum bit flip count is 5 bits in a sector. Bit flips were corrected.
0
1
1
0
Maximum bit flip count is 6 bits in a sector. Bit flips were corrected.
0
1
1
1
Maximum bit flip count is 7 bits in a sector. Bit flips were corrected.
1
0
0
0
Maximum bit flip count is 8 bits in a sector. Bit flips were corrected.
1
1
1
1
Maximum bit flip count exceed 8 bits in a sector. Bit flips were not corrected.
MFS2
MFS1
MFS0
0
0
0
Maximum bit flips occurred in sector 0.
0
0
1
Maximum bit flips occurred in sector 1.
0
1
0
Maximum bit flips occurred in sector 2.
0
1
1
Maximum bit flips occurred in sector 3.
7.5
Description
Description
Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be written
as “0”, but there will not be any effects.
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
7.6
W25N04KV Status Register Memory Protection
STATUS REGISTER(1)
W25N04KV (4G-BIT / 512M-BYTE) MEMORY PROTECTION(2)
TB
BP3
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
PAGE ADDRESS
PA[23:0]
PROTECTED
DENSITY
PROTECTED
PORTION
X
0
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
4092 thru 4095
3FF00h – 3FFFFh
512KB
Upper 1/1024
0
0
0
1
0
4088 thru 4095
3FE00h – 3FFFFh
1MB
Upper 1/512
0
0
0
1
1
4080 thru 4095
3FC00h – 3FFFFh
2MB
Upper 1/256
0
0
1
0
0
4064 thru 4095
3F800h – 3FFFFh
4MB
Upper 1/128
0
0
1
0
1
4032 thru 4095
3F000h – 3FFFFh
8MB
Upper 1/64
0
0
1
1
0
3968 thru 4095
3E000h – 3FFFFh
16MB
Upper 1/32
0
0
1
1
1
3840 thru 4095
3C000h – 3FFFFh
32MB
Upper 1/16
0
1
0
0
0
3584 thru 4095
38000h – 3FFFFh
64MB
Upper 1/8
0
1
0
0
1
3072 thru 4095
30000h – 3FFFFh
128MB
Upper 1/4
0
1
0
1
0
2048 thru 4095
20000h – 3FFFFh
256MB
Upper 1/2
1
0
0
0
1
0 thru 3
0000h – 00FFh
512KB
Lower 1/1024
1
0
0
1
0
0 thru 7
0000h – 01FFh
1MB
Lower 1/512
1
0
0
1
1
0 thru 15
0000h – 03FFh
2MB
Lower 1/256
1
0
1
0
0
0 thru 31
0000h – 07FFh
4MB
Lower 1/128
1
0
1
0
1
0 thru 63
0000h – 0FFFh
8MB
Lower 1/64
1
0
1
1
0
0 thru 127
0000h – 1FFFh
16MB
Lower 1/32
1
0
1
1
1
0 thru 255
0000h – 3FFFh
32MB
Lower 1/16
1
1
0
0
0
0 thru 511
0000h – 7FFFh
64MB
Lower 1/8
1
1
0
0
1
0 thru 1023
0000h – FFFFh
128MB
Lower 1/4
1
1
0
1
0
0 thru 2047
0000h – 1FFFFh
256MB
Lower 1/2
X
1
0
1
1
0 thru 4095
0000h – 3FFFFh
512MB
ALL
X
1
1
X
X
0 thru 4095
0000h – 3FFFFh
512MB
ALL
Notes:
1. X = don’t care
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
- 25 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25N04KV consists of 31 basic instructions that are
fully controlled through the SPI bus (see Instruction Set Table1, 2). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5 through
32. All read instructions can be completed after any clocked bit. However, all instructions that Write,
Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked)
otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes.
Additionally, while the device is performing Program or Erase operation, Page Data Read or OTP locking
operations, BUSY bit will be high, and all instructions except for Read Status Register or Read JEDEC ID
will be ignored until the current operation cycle has completed.
8.1
Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID
(MF7 – MF0)
Winbond Serial Flash
EFh
Device ID
(ID15 – ID0)
W25N04KV
AA23h
- 26 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.1.2 Instruction Set Table 1 (Buffer Read, BUF = 1, default)
Commands
OpCode
Byte2
Byte3
Byte4
Byte5
Device RESET
FFh
JEDEC ID
Byte6
Byte7
Byte8
Byte9
9Fh
Dummy
EFh
AAh
23h
Read Status Register 1
0Fh / 05h
Axh
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Read Status Register 2
0Fh / 05h
Bxh
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Read Status Register 3
0Fh / 05h
Cxh
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Read Extended Internal
ECC
feature registers
0Fh / 05h
10h/20h/30
h/40h/50h
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Write Status Register 1
1Fh / 01h
Axh
S7-0
Write Status Register 2
1Fh / 01h
Bxh
S7-0
Write Extended Internal
ECC
feature registers
1Fh / 01h
10h
S7-0
Write Enable
06h
Write Disable
04h
Block Erase
D8h
*PA23-16
PA15-8
PA7-0
02h
CA15-8
CA7-0
Data-0
Data-1
Data-2
Data-3
Data-4
Data-5
84h
CA15-8
CA7-0
Data-0
Data-1
Data-2
Data-3
Data-4
Data-5
32h
CA15-8
CA7-0
Data-0 / 4
Data-1 / 4
Data-2 / 4
Data-3 / 4
Data-4 / 4
Data-5 / 4
34h
CA15-8
CA7-0
Data-0 / 4
Data-1 / 4
Data-2 / 4
Data-3 / 4
Data-4 / 4
Data-5 / 4
Program Execute
10h
*PA23-16
PA15-8
PA7-0
Page Data Read
13h
*PA23-16
PA15-8
PA7-0
Read
03h
CA15-8
CA7-0
Dummy
D7-0
D7-0
D7-0
D7-0
D7-0
Fast Read
0Bh
CA15-8
CA7-0
Dummy
D7-0
D7-0
D7-0
D7-0
D7-0
Fast Read
with 4-Byte Address
0Ch
CA15-8
CA7-0
Dummy
Dummy
Dummy
D7-0
D7-0
D7-0
Fast Read Dual Output
3Bh
CA15-8
CA7-0
Dummy
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Dual Output
with 4-Byte Address
3Ch
CA15-8
CA7-0
Dummy
Dummy
Dummy
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Quad Output
6Bh
CA15-8
CA7-0
Dummy
D7-0 / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Quad Output
with 4-Byte Address
6Ch
CA15-8
CA7-0
Dummy
Dummy
Dummy
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Dual I/O
BBh
CA15-8 / 2
CA7-0 / 2
Dummy / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Dual I/O
with 4-Byte Address
BCh
CA15-8 / 2
CA7-0 / 2
Dummy / 2
Dummy / 2
Dummy / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Quad I/O
EBh
CA15-8 / 4
CA7-0 / 4
Dummy / 4
Dummy / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Quad I/O
with 4-Byte Address
ECh
CA15-8 / 4
CA7-0 / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
D7-0 / 4
Deep Power-Down
B9h
Release Power-Down
ABh
Enable Reset
66h
Reset Device
99h
Program Data Load
(Reset Buffer)
Random Program
Data Load
Quad Program
Data Load (Reset Buffer)
Random Quad Program
Data Load
*note: PA[23:17] input would be ignored.
- 27 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.1.3 Instruction Set Table 2 (Sequential Read, BUF = 0, ECC-E = 0)
Commands
OpCode
Byte2
Byte3
Byte4
Byte5
Device RESET
FFh
JEDEC ID
Byte6
Byte7
Byte8
Byte9
9Fh
Dummy
EFh
AAh
23h
Read Status Register 1
0Fh / 05h
Axh
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Read Status Register 2
0Fh / 05h
Bxh
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Read Status Register 3
0Fh / 05h
Cxh
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Read Extended Internal
ECC
feature registers
0Fh / 05h
10h/20h/30
h/40h/50h
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
S7-0
Write Status Register 1
1Fh / 01h
Axh
S7-0
Write Status Register 2
1Fh / 01h
Bxh
S7-0
Write Extended Internal
ECC
feature registers
1Fh / 01h
10h
S7-0
Write Enable
06h
Write Disable
04h
Block Erase
D8h
*PA23-16
PA15-8
PA7-0
02h
CA15-8
CA7-0
Data-0
Data-1
Data-2
Data-3
Data-4
Data-5
84h
CA15-8
CA7-0
Data-0
Data-1
Data-2
Data-3
Data-4
Data-5
32h
CA15-8
CA7-0
Data-0 / 4
Data-1 / 4
Data-2 / 4
Data-3 / 4
Data-4 / 4
Data-5 / 4
34h
CA15-8
CA7-0
Data-0 / 4
Data-1 / 4
Data-2 / 4
Data-3 / 4
Data-4 / 4
Data-5 / 4
Program Execute
10h
Dummy
PA15-8
PA7-0
Page Data Read
13h
Dummy
PA15-8
PA7-0
Read
03h
Dummy
Dummy
Dummy
D7-0
D7-0
D7-0
D7-0
D7-0
Fast Read
0Bh
Dummy
Dummy
Dummy
Dummy
D7-0
D7-0
D7-0
D7-0
Fast Read
with 4-Byte Address
0Ch
Dummy
Dummy
Dummy
Dummy
Dummy
D7-0
D7-0
D7-0
Fast Read Dual Output
3Bh
Dummy
Dummy
Dummy
Dummy
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Dual Output
with 4-Byte Address
3Ch
Dummy
Dummy
Dummy
Dummy
Dummy
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Quad Output
6Bh
Dummy
Dummy
Dummy
Dummy
D7-0 / 4
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Quad Output
with 4-Byte Address
6Ch
Dummy
Dummy
Dummy
Dummy
Dummy
D7-0 / 4
D7-0 / 4
D7-0 / 4
Fast Read Dual I/O
BBh
Dummy / 2
Dummy / 2
Dummy / 2
Dummy / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Dual I/O
with 4-Byte Address
BCh
Dummy / 2
Dummy / 2
Dummy / 2
Dummy / 2
Dummy / 2
D7-0 / 2
D7-0 / 2
D7-0 / 2
Fast Read Quad I/O
EBh
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
D7-0 / 4
D7-0 / 4
Fast Read Quad I/O
with 4-Byte Address
ECh
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
Dummy / 4
D7-0 / 4
Deep Power-Down
B9h
Release Power-Down
ABh
Enable Reset
66h
Reset Device
99h
Program Data Load
(Reset Buffer)
Random Program
Data Load
Quad Program
Data Load (Reset Buffer)
Random Quad Program
Data Load
- 28 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
Notes:
1.
D7-0 designates data output from the device.
2.
Column Address (CA) only requires CA[11:0], CA[15:12] are considered as dummy bits.
3.
Page Address (PA) requires 18 bits. PA[17:6] is the address for 128KB blocks (total 4096 blocks), PA[5:0] is
the address for 2KB pages (total 64 pages for each block).
4.
Status Register Addresses:
Status Register 1 / Protection Register:
Status Register 2 / Configuration Register:
Status Register 3 / Status Register:
5.
Dual SPI Address Input (CA15-8 / 2 and CA7-0 / 2) format:
IO0 = x, x, CA10, CA8, CA6, CA4, CA2,
IO1 = x, x, CA11, CA9, CA7, CA5, CA3,
Addr = Axh
Addr = Bxh
Addr = Cxh
CA0
CA1
6.
Dual SPI Data Output (D7-0 / 2) format:
IO0 = D6, D4, D2, D0, ……
IO1 = D7, D5, D3, D1, ……
7.
Quad SPI Address Input (CA15-8 / 4 and CA7-0 / 4) format:
IO0 = x, CA8, CA4,
CA0
IO1 = x, CA9, CA5,
CA1
IO2 = x, CA10, CA6,
CA2
IO3 = x, CA11, CA7,
CA3
8.
Quad SPI Data Input/Output (D7-0 / 4) format:
IO0 = D4, D0, ……
IO1 = D5, D1, ……
IO2 = D6, D2, ……
IO3 = D7, D3, ……
9.
All Quad Program/Read commands are disabled when WP-E bit is set to 1 in the Protection Register.
10. For all Read operations, as soon as /CS signal is brought to high to terminate the read operation, the device
will be ready to accept new instructions and all the data inside the Data Buffer will remain unchanged from
the previous Page Data Read instruction.
11. For all Read operations in the Sequential Read Mode, once the /CS signal is brought to high to terminate the
read operation, the device will still remain busy for tRD3 (BUSY=1), and all the data inside the Data buffer
will be lost and un-reliable to use. A new Page Data Read instruction must be issued to reload the correct
page data into the Data Buffer.
- 29 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2
Instruction Descriptions
8.2.1 Device Reset (FFh), Enable Reset (66h) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the W25N04KV provide a software
Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going
internal operations will be terminated and the device state bits will follow the below table. Once the Reset
command is accepted by the device, the device will take approximately tRST to reset, depending on the
current operation the device is performing, tRST can be 5us~500us. During this period, no command will
be accepted.
Data corruption may happen if there is an on-going internal Erase or Program operation when Reset
command sequence is accepted by the device. It is recommended to check the BUSY bit in Status Register
before issuing the Reset command.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (FFh)
DI
(IO0)
High Impedance
DO
(IO1)
Figure 5a. Device Reset Instruction
/CS
Mode 3
CLK
0
1
2
3
4
Mode 0
5
6
7
Mode 3
0
1
2
3
4
Mode 0
Instruction (66h)
5
6
7
Mode 3
Mode 0
Instruction (99h)
DI
(IO0)
DO
(IO1)
High Impedance
Figure 5b. Enable Reset and Reset Instruction Sequence
- 30 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
No change
No change
0
0
0
0
After Reset
(66h+99h)
command or HW
Reset
1 1 1 1, 1
00
0
Clear to 0 before
OTP set
0
Clear to 0 before
OTP set
1
Based on speical
options
00
1
0
0
0
0
0100
No change
0100
Page 0 reload
Fix no reload
Option page reload
(default no reload)
Power up after OTP Power up after SRarea locked
1 locked
Register
Address
Bits
Shipment default
Status register - 1
Axh
BP[3:0], TB
SRP[1:0]
WP-E
1 1 1 1, 1
00
0
1 1 1 1, 1
00
0
xxx, x(locked)
11(locked)
x(locked)
Status register - 2
Bxh
OTP-L
0
1
0
OTP-E
0
0
0
SR1-L
0
0
1
ECC-E
ODS[1:0]
H-DIS
P-FAIL
E-FAIL
WEL
BUSY
1
Based on speical
options
00
1
0
0
0
0
1
Based on speical
options
00
1
0
0
0
0
1
Based on speical
options
00
1
0
0
0
0
BFD[3:0]
0100
0100
Page 0 reload
Page 0 reload
BUF
Status register -3
Cxh
Extended Internal
ECC feature register
10h
Page 0 Reload
After Reset (FFh)
command
No change
No change
No change
Clear to 0 before
OTP set
0
Clear to 0 before
OTP set
No change
No change
Figure 5c. Default values of the Status Registers after power up and Device Reset
- 31 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.2 Read JEDEC ID (9Fh)
The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories
that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction
code “9Fh” followed by 8 dummy clocks. The JEDEC assigned Manufacturer ID byte for Winbond (EFh)
and two Device ID bytes are then shifted out on the falling edge of CLK with most significant bit (MSB) first
as shown in Figure 6. For memory type and capacity values refer to Manufacturer and Device Identification
table.
Figure 6. Read JEDEC ID Instruction
- 32 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.3 Read Status Register (0Fh / 05h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving /CS low and shifting the instruction code “0Fh or 05h” into the DI pin on the rising edge of CLK
followed by an 8-bit Status Register Address. The status register bits are then shifted out on the DO pin at
the falling edge of CLK with most significant bit (MSB) first as shown in Figure 7. Refer to section 7.1-3 for
Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program, Erase or Page Read
cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle is complete
and if the device can accept another instruction. The Status Register can be read continuously. The
instruction is completed by driving /CS high.
/CS
Mode 3
CLK
0
7
8
15
16
17
18
19
20
21
22
23
Mode 0
Mode 3
Mode 0
Instruction
DI
(IO0)
9
0Fh / 05h
SR Address
7
6
1
0
SR Value[7:0]
DO
(IO1)
High Impedance
7
6
5
4
3
2
1
0
Figure 7. Read Status Register Instruction
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Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.4 Write Status Register (1Fh / 01h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status Register
bits include: SRP[1:0], TB, BP[3:0] and WP-E bit in Status Register-1; OTP-L, OTP-E, SR1-L and ECC-E
in Status Register-2. All other Status Register bit locations are read-only and will not be affected by the
Write Status Register instruction.
To write the Status Register bits, the instruction is entered by driving /CS low, sending the instruction code
“1Fh or 01h”, followed by an 8-bit Status Register Address, and then writing the status register data byte
as illustrated in Figure 8.
Refer to section 7.1-3 for Status Register descriptions. After power up, factory default for BP[3:0], TB, ECCE bits are 1, while other bits are 0.
/CS
Mode 3
CLK
0
7
8
DO
(IO1)
15
16
17
18
19
20
21
22
23
Mode 3
Mode 0
Instruction
DI
(IO0)
9
Mode 0
1Fh / 01h
SR Address
7
6
1
SR Value[7:0]
0
7
6
5
4
3
2
1
0
High Impedance
Figure 8. Write Status Register-1/2/3 Instruction
- 34 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.5 Write Enable (06h)
The Write Enable instruction (Figure 9) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
The WEL bit must be set prior to every Load Program Data (02h/84h/32h/34h), Program execute and Block
Erase instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code
“06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction (06h)
DI
(IO0)
High Impedance
DO
(IO1)
Figure 9. Write Enable Instruction
8.2.6 Write Disable (04h)
The Write Disable instruction (Figure 10) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Page Data Read, Program Execute, Block Erase and Reset instructions.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
Mode 0
7
Mode 3
Mode 0
Instruction (04h)
DI
(IO0)
DO
(IO1)
High Impedance
Figure 10. Write Disable Instruction
- 35 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.7 128KB Block Erase (D8h)
The 128KB Block Erase instruction sets all memory within a specified block (64-Pages, 128K-Bytes) to the
erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the
Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
/CS pin low and shifting the instruction code “D8h” followed by the 24-bit page address. The Block Erase
instruction sequence is shown in Figure 11.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if
the addressed block is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bits.
/CS
Mode 3
CLK
0
7
DO
(IO1)
9
15
16
17
29
30
31
Mode 0
Mode 3
Mode 0
Instruction
DI
(IO0)
8
D8h
Page Address [23:0]
15
14
13
2
1
0
High Impedance
Figure 11. 128KB Block Erase Instruction
- 36 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.8 Load Program Data (02h) / Random Load Program Data (84h)
The Program operation allows from one byte to 2,176 bytes (a page) of data to be programmed at previously
erased (FFh) memory locations. A Program operation involves two steps: 1. Load the program data into
the Data Buffer. 2. Issue “Program Execute” command to transfer the data from Data Buffer to the specified
memory page.
A Write Enable instruction must be executed before the device will accept the Load Program Data
Instructions (Status Register bit WEL= 1). The “Load Program Data” or “Random Load Program Data”
instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” or “84h” followed by
a 16-bit column address (only CA[11:0] is effective) and at least one byte of data into the DI pin. The /CS
pin must be held low for the entire length of the instruction while data is being sent to the device. If the
number of data bytes sent to the device exceeds the number of data bytes in the Data Buffer, the extra
data will be ignored by the device. The Load Program Data instruction sequence is shown in Figure 12.
Both “Load Program Data” and “Random Load Program Data” instructions share the same command
sequence. The difference is that “Load Program Data” instruction will reset the unused the data bytes in
the Data Buffer to FFh value, while “Random Load Program Data” instruction will only update the data bytes
that are specified by the command input sequence, the rest of the Data Buffer will remain unchanged.
If internal ECC algorithm is enabled, all 2,176 bytes of data will be accepted, but the bytes designated for
ECC parity bits in the extra 64 bytes section will be overwritten by the ECC calculation. If the ECC-E bit is
set to a 0 to disable the internal ECC, the extra 64 bytes section can be used for external ECC purpose or
other usage.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
24
Mode 0
Instruction
DI
(IO0)
Column Address[15:0]
02h / 84h
15
14
13
2
1
0
7
High Impedance
DO
(IO1)
/CS
24
30
31
32
38
39
40
Mode 3
CLK
Mode 0
Data-0
DI
(IO0)
DO
(IO1)
7
6
1
Data-1
0
7
6
1
Data-2175
0
7
0
7
6
1
0
High Impedance
Figure 12. Load / Random Load Program Data Instruction
- 37 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.9 Quad Load Program Data (32h) / Quad Random Load Program Data (34h)
The “Quad Load Program Data” and “Quad Random Load Program Data” instructions are identical to the
“Load Program Data” and “Random Load Program Data” in terms of operation sequence and functionality.
The only difference is that “Quad Load” instructions will input the data bytes from all four IO pins instead of
the single DI pin. This method will significantly shorten the data input time when a large amount of data
needs to be loaded into the Data Buffer. The instruction sequence is illustrated in Figure 13.
Both “Quad Load Program Data” and “Quad Random Load Program Data” instructions share the same
command sequence. The difference is that “Quad Load Program Data” instruction will reset the unused the
data bytes in the Data Buffer to FFh value, while “Quad Random Load Program Data” instruction will only
update the data bytes that are specified by the command input sequence, the rest of the Data Buffer will
remain unchanged.
When WP-E bit in the Status Register is set to a 1, all Quad SPI instructions are disabled.
Figure 13. Quad Load / Quad Random Load Program Data Instruction
- 38 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.10
Program Execute (10h)
The Program Execute instruction is the second step of the Program operation. After the program data are
loaded into the 2,176-Byte Data Buffer (or 2,048 bytes when ECC is enabled), the Program Execute
instruction will program the Data Buffer content into the physical memory page that is specified in the
instruction. The instruction is initiated by driving the /CS pin low then shifting the instruction code “10h”
followed by 24-bit Page Address into the DI pin as shown in Figure 14.
The pages within the block have to be programmed sequentially from the lower order page address to the
higher order page address within the block. Programming pages out of sequence is prohibited.
After /CS is driven high to complete the instruction cycle, the self-timed Program Execute instruction will
commence for a time duration of tpp (See AC Characteristics). While the Program Execute cycle is in
progress, the Read Status Register instruction may still be used for checking the status of the BUSY bit.
The BUSY bit is a 1 during the Program Execute cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Program Execute cycle has finished, the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Program Execute instruction will not be
executed if the addressed page is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bits.
Do not cross plane address boundaries to apply the Program Execute operation. The page data read from
one plane cannot program to different plane.
/CS
Mode 3
CLK
0
7
DO
(IO1)
9
15
16
17
29
30
31
Mode 3
Mode 0
Instruction
DI
(IO0)
8
Mode 0
10h
Page Address[23:0]
15
14
13
2
1
0
High Impedance
Figure 14. Program Execute Instruction
- 39 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.11
Page Data Read (13h)
The Page Data Read instruction will transfer the data of the specified memory page into the 2,176-Byte
Data Buffer. The instruction is initiated by driving the /CS pin low then shifting the instruction code “13h”
followed by 24-bit Page Address into the DI pin as shown in Figure 15.
After /CS is driven high to complete the instruction cycle, the self-timed Page Data Read instruction will
commence for a time duration of tRD (See AC Characteristics). While the Page Data Read cycle is in
progress, the Read Status Register instruction may still be used for checking the status of the BUSY bit.
The BUSY bit is a 1 during the Page Data Read cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again.
After the 2,176 bytes of page data are loaded into the Data Buffer, several Read instructions can be issued
to access the Data Buffer and read out the data.
/CS
Mode 3
CLK
0
7
DO
(IO1)
9
15
16
17
29
30
31
Mode 3
Mode 0
Instruction
DI
(IO0)
8
Mode 0
13h
Page Address [23:0]
15
14
13
2
1
0
High Impedance
Figure 15. Page Data Read Instruction
- 40 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.12
Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the Data Buffer after
executing the Read Page Data instruction. The Read Data instruction is initiated by driving the /CS pin low
and then shifting the instruction code “03h” followed by the 16-bit Column Address and 8-bit dummy clocks
or a 24-bit dummy clocks into the DI pin. After the address is received, the data byte of the addressed Data
Buffer location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB)
first. The address is automatically incremented to the next higher address after each byte of data is shifted
out allowing for a continuous stream of data. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in Figure 16a & 16b. When BUF=1, the device is in the Buffer
Read Mode. The data output sequence will start from the Data Buffer location specified by the 16-bit Column
Address and continue to the end of the Data Buffer. Once the last byte of data is output, the output pin will
become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data output sequence
will start from the first byte of the Data Buffer and increment to the next higher address. When the end of
the Data Buffer is reached, the data of the first byte of next memory page will be following and continues
through the entire memory array. This allows using a single Read instruction to read out the entire memory
array and is also compatible to Winbond’s NOR flash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
31
32
38
39
40
46
47
Mode 0
Instruction
DI
(IO0)
8 Dummy
Clocks
Column Address[15:0]
03h
15
14
13
2
1
0
Data Out 1
High Impedance
DO
(IO1)
7
*
6
1
Data Out 2
0
7
6
1
0
7
*
* = MSB
*
Figure 16a. Read Data Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
Instruction
DI
(IO0)
29
30
31
32
38
39
40
47
03h
24 Dummy Clocks
23
22
21
2
1
0
Data Out 1
DO
(IO1)
46
Mode 0
High Impedance
7
6
*
1
* = MSB
Data Out 2
0
7
*
6
1
0
7
*
Figure 16b. Read Data Instruction (Sequential Read Mode, BUF=0)
- 41 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.13 Fast Read (0Bh)
The Fast Read instruction allows one or more data bytes to be sequentially read from the Data Buffer after
executing the Read Page Data instruction. The Fast Read instruction is initiated by driving the /CS pin low
and then shifting the instruction code “0Bh” followed by the 16-bit Column Address and 8-bit dummy clocks
or a 32-bit dummy clocks into the DI pin. After the address is received, the data byte of the addressed Data
Buffer location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB)
first. The address is automatically incremented to the next higher address after each byte of data is shifted
out allowing for a continuous stream of data. The instruction is completed by driving /CS high.
The Fast Read instruction sequence is shown in Figure 17a & 17b. When BUF=1, the device is in the Buffer
Read Mode. The data output sequence will start from the Data Buffer location specified by the 16-bit Column
Address and continue to the end of the Data Buffer. Once the last byte of data is output, the output pin will
become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data output sequence
will start from the first byte of the Data Buffer and increment to the next higher address. When the end of
the Data Buffer is reached, the data of the first byte of next memory page will be following and continues
through the entire memory array. This allows using a single Read instruction to read out the entire memory
array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
31
32
38
39
40
46
47
Mode 0
Instruction
DI
(IO0)
8 Dummy
Clocks
Column Address[15:0]
0Bh
15
14
13
2
1
0
Data Out 1
High Impedance
DO
(IO1)
7
*
6
1
Data Out 2
0
7
6
1
0
*
* = MSB
7
*
Figure 17a. Fast Read Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
21
Instruction
DI
(IO0)
22
23
39
40
46
47
48
0Bh
55
32 Dummy Clocks
31
30
29
18
17
16
0
Data Out 1
DO
(IO1)
54
Mode 0
High Impedance
7
*
6
1
Data Out 2
0
* = MSB
7
*
6
1
0
7
*
Figure 17b. Fast Read Instruction (Sequential Read Mode, BUF=0)
- 42 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.14
Fast Read with 4-Byte Address (0Ch)
The Fast Read instruction allows one or more data bytes to be sequentially read from the Data Buffer after
executing the Read Page Data instruction. The Fast Read instruction is initiated by driving the /CS pin low
and then shifting the instruction code “0Ch” followed by the 16-bit Column Address and 24-bit dummy clocks
(when BUF=1) or a 40-bit dummy clocks (when BUF=0) into the DI pin. After the address is received, the
data byte of the addressed Data Buffer location will be shifted out on the DO pin at the falling edge of CLK
with most significant bit (MSB) first. The address is automatically incremented to the next higher address
after each byte of data is shifted out allowing for a continuous stream of data. The instruction is completed
by driving /CS high.
The Fast Read instruction sequence is shown in Figure 21a & 21b. When BUF=1, the device is in the Buffer
Read Mode. The data output sequence will start from the Data Buffer location specified by the 16-bit Column
Address and continue to the end of the Data Buffer. Once the last byte of data is output, the output pin will
become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data output sequence
will start from the first byte of the Data Buffer and increment to the next higher address. When the end of
the Data Buffer is reached, the data of the first byte of next memory page will be following and continues
through the entire memory array. This allows using a single Read instruction to read out the entire memory
array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
47
48
54
55
56
62
63
Mode 0
Instruction
DI
(IO0)
24 Dummy
Clocks
Column Address[15:0]
0Ch
15
14
13
2
1
0
Data Out 1
High Impedance
DO
(IO1)
7
*
6
1
Data Out 2
0
7
6
1
0
*
* = MSB
7
*
Figure 18a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
21
Instruction
DI
(IO0)
22
23
47
48
54
55
56
63
0Ch
40 Dummy Clocks
39
38
37
26
25
24
0
Data Out 1
DO
(IO1)
62
Mode 0
High Impedance
7
*
6
1
* = MSB
Data Out 2
0
7
6
*
1
0
7
*
Figure 18b. Fast Read with 4-Byte Address Instruction (Sequential Read Mode, BUF=0)
- 43 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.15 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices.
The Fast Read Dual Output instruction sequence is shown in Figure 19a & 19b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
31
32
33
34
35
36
37
38
39
40
Mode 0
Instruction
DI
(IO0)
8 Dummy
Clocks
Column Address[15:0]
3Bh
15
14
13
2
1
0
6
4
2
0
6
4
Data Out 1
High Impedance
DO
(IO1)
7
5
*
3
2
0
6
1
7
Data Out 2
1
7
5
3
*
* = MSB
*
Figure 19a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
21
Instruction
DI
(IO0)
22
23
39
40
41
42
43
44
46
47
48
3Bh
32 Dummy Clocks
31
30
29
18
17
16
0
6
4
2
0
6
Data Out 1
DO
(IO1)
45
Mode 0
High Impedance
7
*
5
3
* = MSB
4
2
0
6
Data Out 2
1
7
*
5
3
1
7
*
Figure 19b. Fast Read Dual Output Instruction (Sequential Read Mode, BUF=0)
- 44 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.16
Fast Read Dual Output with 4-Byte Address (3Ch)
The Fast Read Dual Output (3Ch) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices.
The Fast Read Dual Output instruction sequence is shown in Figure 20a & 20b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
47
48
49
50
51
52
53
54
55
56
Mode 0
Instruction
DI
(IO0)
24 Dummy
Clocks
Column Address[15:0]
3Ch
15
14
13
2
1
0
6
4
2
0
6
Data Out 1
High Impedance
DO
(IO1)
7
5
*
3
4
2
0
6
1
7
Data Out 2
1
7
5
3
*
* = MSB
*
Figure 20a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
29
Instruction
DI
(IO0)
30
31
47
48
49
50
51
52
54
55
56
3Ch
40 Dummy Clocks
39
38
37
18
17
16
0
6
4
2
0
6
Data Out 1
DO
(IO1)
53
Mode 0
High Impedance
7
*
5
3
* = MSB
4
2
0
6
Data Out 2
1
7
5
3
*
1
7
*
Figure 20b. Fast Read Dual Output with 4-Byte Address Instruction (Sequential Read Mode, BUF=0)
- 45 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.17
Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Fast Read Quad Output Instruction allows
data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction sequence is shown in Figure 21a & 21b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
31
32
33
34
35
36
37
38
39
40
Mode 0
Instruction
DI
(IO0)
8 Dummy
Clocks
Column Address[15:0]
6Bh
15
14
13
2
1
0
High Impedance
DO
(IO1)
High Impedance
IO2
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
High
/Hold
(IO3)
* = MSB
*Data
*Data
*Data
*Data
*Data
Out 1
Out 2
Out 3
Out 4
Out 5
46
48
Figure 21a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
21
Instruction
DI
(IO0)
DO
(IO1)
IO2
22
23
39
40
41
42
43
44
45
47
Mode 0
6Bh
32 Dummy Clocks
31
30
29
18
17
16
0
High Impedance
High Impedance
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
High
/Hold
(IO3)
* = MSB
*Data
*Data
*Data
*Data
*Data
Out 1
Out 2
Out 3
Out 4
Out 5
Figure 21b. Fast Read Quad Output Instruction (Sequential Read Mode, BUF=0)
- 46 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.18
Fast Read Quad Output with 4-Byte Address (6Ch)
The Fast Read Quad Output (6Ch) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Fast Read Quad Output Instruction allows
data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction sequence is shown in Figure 22a & 22b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
CLK
0
7
8
9
21
22
23
47
48
49
50
51
52
53
54
55
56
Mode 0
Instruction
DI
(IO0)
24 Dummy
Clocks
Column Address[15:0]
6Ch
15
14
13
2
1
0
High Impedance
DO
(IO1)
High Impedance
IO2
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
High
/Hold
(IO3)
* = MSB
*Data
*Data
*Data
*Data
*Data
Out 1
Out 2
Out 3
Out 4
Out 5
Figure 22a. Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
29
Instruction
DI
(IO0)
DO
(IO1)
IO2
30
31
47
48
49
50
51
52
53
54
55
56
Mode 0
6Ch
40 Dummy Clocks
39
38
37
18
17
16
0
High Impedance
High Impedance
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
High
/Hold
(IO3)
* = MSB
*Data
*Data
*Data
*Data
*Data
Out 1
Out 2
Out 3
Out 4
Out 5
Figure 22b. Fast Read Quad Output with 4-Byte Address Instruction (Sequential Read Mode, BUF=0)
- 47 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.19
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Column Address or the dummy clocks two bits per clock. This reduced instruction overhead may allow
for code execution (XIP) directly from the Dual SPI in some applications.
The Fast Read Quad Output instruction sequence is shown in Figure 23a & 23b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
13
14
15
19
20
21
22
23
24
Instruction
DI
(IO0)
26
27
28
4 Dummy
Clocks
Column Address[15:0]
BBh
14
12
10
4
2
0
6
4
2
0
6
Data Out 1
DO
(IO1)
25
Mode 0
High Impedance
15
13
11
5
3
1
7
5
*
3
4
2
0
6
1
7
Data Out 2
1
7
5
3
*
* = MSB
*
Figure 23a. Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
15
Instruction
DI
(IO0)
16
17
23
24
25
26
27
28
30
31
32
BBh
16 Dummy Clocks
30
28
26
16
14
12
0
6
4
2
0
6
Data Out 1
DO
(IO1)
29
Mode 0
High Impedance
31
29
27
17
15
13
1
7
*
5
3
4
2
0
6
1
7
Data Out 2
1
* = MSB
7
*
5
3
*
Figure 23b. Fast Read Dual I/O Instruction (Sequential Read Mode, BUF=0)
- 48 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.20
Fast Read Dual I/O with 4-Byte Address (BCh)
The Fast Read Dual I/O (BCh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Column Address or the dummy clocks two bits per clock. This reduced instruction overhead may allow
for code execution (XIP) directly from the Dual SPI in some applications.
The Fast Read Quad Output instruction sequence is shown in Figure 24a & 24b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
/CS
Mode 3
CLK
0
7
8
9
13
14
15
27
28
29
30
31
32
Instruction
DI
(IO0)
34
35
36
12 Dummy
Clocks
Column Address[15:0]
BCh
14
12
10
4
2
0
6
4
2
0
6
Data Out 1
DO
(IO1)
33
Mode 0
High Impedance
15
13
11
5
3
1
7
5
*
3
4
2
0
6
1
7
Data Out 2
1
7
5
3
*
* = MSB
*
Figure 24a. Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
/CS
Mode 3
CLK
0
7
8
9
19
Instruction
DI
(IO0)
20
21
27
28
29
30
31
32
34
35
36
BCh
20 Dummy Clocks
38
36
34
16
14
12
0
6
4
2
0
6
Data Out 1
DO
(IO1)
33
Mode 0
High Impedance
39
37
35
17
15
13
1
7
*
5
3
* = MSB
4
2
0
6
1
7
Data Out 2
1
7
5
3
*
*
Figure 24b. Fast Read Dual I/O with 4-Byte Address Instruction (Sequential Read Mode, BUF=0)
- 49 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.21
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 prior to the data output.
The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution
(XIP) directly from the Quad SPI.
The Fast Read Quad Output instruction sequence is shown in Figure 25a & 25b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
CLK
0
7
8
DI
(IO0)
IO2
10
11
12
13
14
15
16
17
18
19
20
21
22
EBh
High Impedance
High Impedance
4 Dummy
Clocks
Column
Address[15:0]
Instruction
DO
(IO1)
9
Mode 0
12
8
4
0
X
X
X
X
4
0
4
0
4
0
4
13
9
5
1
X
X
X
X
5
1
5
1
5
1
5
14
10
6
2
X
X
X
X
6
2
6
2
6
2
6
15
11
7
3
X
X
X
X
7
3
7
3
7
3
7
High
/Hold
(IO3)
* = MSB
*Data
*Data
*Data
*Data
Out 1
Out 2
Out 3
Out 4
Figure 25a. Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1)
- 50 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
/CS
Mode 3
CLK
0
7
8
9
13
Instruction
DI
(IO0)
DO
(IO1)
IO2
14
15
19
20
21
22
23
24
25
26
27
28
Mode 0
EBh
High Impedance
High Impedance
12 Dummy Clocks
44
40
36
24
20
16
0
4
0
4
0
4
0
4
0
4
45
41
37
25
21
17
1
5
1
5
1
5
1
5
1
5
46
42
38
26
22
18
2
6
2
6
2
6
2
6
2
6
47
43
39
27
23
19
3
7
3
7
3
7
3
7
3
7
High
/Hold
(IO3)
*
= MSB
*Data
*Data
*Data
*Data
*Data
Out 1
Out 2
Out 3
Out 4
Out 5
Figure 25b. Fast Read Quad I/O Instruction (Sequential Read Mode, BUF=0)
- 51 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.22
Fast Read Quad I/O with 4-Byte Address (ECh)
The Fast Read Quad I/O (ECh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 prior to the data output.
The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution
(XIP) directly from the Quad SPI.
The Fast Read Quad Output instruction sequence is shown in Figure 26a & 26b. When BUF=1, the device
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,
the output pin will become Hi-Z state. When BUF=0, the device is in the Sequential Read Mode, the data
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be following
and continues through the entire memory array. This allows using a single Read instruction to read out the
entire memory array and is also compatible to Winbond’s NOR SpiFlash memory command sequence.
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.
/CS
Mode 3
CLK
0
7
8
DI
(IO0)
IO2
10
11
12
21
22
23
24
25
25
27
28
ECh
High Impedance
High Impedance
10 Dummy
Clocks
Column
Address[15:0]
Instruction
DO
(IO1)
9
Mode 0
12
8
4
0
X
X
4
0
4
0
4
0
4
13
9
5
1
X
X
5
1
5
1
5
1
5
14
10
6
2
X
X
6
2
6
2
6
2
6
15
11
7
3
X
X
7
3
7
3
7
3
7
High
/Hold
(IO3)
* = MSB
*Data
*Data
*Data
*Data
Out 1
Out 2
Out 3
Out 4
Figure 26a. Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)
- 52 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
/CS
Mode 3
CLK
0
7
8
9
15
Instruction
DI
(IO0)
DO
(IO1)
IO2
16
17
21
22
23
24
25
26
27
28
29
30
Mode 0
ECh
High Impedance
High Impedance
14 Dummy Clocks
52
48
44
24
20
16
0
4
0
4
0
4
0
4
0
4
53
49
45
25
21
17
1
5
1
5
1
5
1
5
1
5
54
50
46
26
22
18
2
6
2
6
2
6
2
6
2
6
55
51
47
27
23
19
3
7
3
7
3
7
3
7
3
7
High
/Hold
(IO3)
* = MSB
*Data
*Data
*Data
*Data
*Data
Out 1
Out 2
Out 3
Out 4
Out 5
Figure 26b. Fast Read Quad I/O with 4-Byte Address Instruction (Sequential Read Mode, BUF=0)
- 53 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.23
Accessing Unique ID / Parameter / OTP Pages (OTP-E=1)
In addition to the main memory array, the W25N04KV is also equipped with one Unique ID Page, one
Parameter Page, and ten OTP Pages.
Page Address
Page Name
Descriptions
Data Length
00h
01h
02h
…
0Bh
Unique ID Page
Parameter Page
OTP Page [0]
OTP Pages [1:8]
OTP Page [9]
Factory programmed, Read Only
Factory programmed, Read Only
Program Only, OTP lockable
Program Only, OTP lockable
Program Only, OTP lockable
32-Byte x 16
256-Byte x 3
2,176-Byte
2,176-Byte
2,176-Byte
To access these additional data pages, the OTP-E bit in Status Register-2 must be set to “1” first. Then,
Read operations can be performed on Unique ID and Parameter Pages, Read and Program operations can
be performed on the OTP pages if it’s not already locked. To return to the main memory array operation,
OTP-E bit needs to be to set to 0.
Read Operations
A “Page Data Read” command must be issued followed by a specific page address shown in the table
above to load the page data into the main Data Buffer. After the device finishes the data loading (BUSY=0),
all Read commands may be used to read the Data Buffer starting from any specified Column Address.
Please note all Read commands must now follow the “Buffer Read Mode” command structure (CA[15:0],
number of dummy clocks). ECC can also be enabled for the OTP page read operations to ensure the data
integrity.
Program and OTP Lock Operations
OTP pages provide the additional space (2K-Byte x 10) to store important data or security information that
can be locked to prevent further modification in the field. These OTP pages are in an erased state set in
the factory, and can only be programmed (change data from “1” to “0”) until being locked by OTP-L bit in
the Configuration/Status Register-2. OTP-E must be first set to “1” to enable the access to these OTP
pages, then the program data must be loaded into the main Data Buffer using any “Program Data Load”
commands. The “Program Execute” command followed by a specific OTP Page Address is used to initiate
the data transfer from the Data Buffer to the OTP page. When ECC is enabled, ECC calculation will be
performed during “Program Execute”, and the ECC information will be stored into the 64-Byte parity area.
Once the OTP pages are correctly programmed, OTP-L bit can be used to permanently lock these pages
so that no further modification is possible. While still in the “OTP Access Mode” (OTP-E=1), user needs to
set OTP-L bit in the Configuration/Status Register-2 to “1”, and issue a “Program Execute” command(Page
address is “don’t care”). After the device finishes the OTP lock setting (BUSY=0), the user can set OTP-E
to “0” to return to the main memory array operation.
SR1-L OTP Lock Operation
The Protection/Status Register-1 contains protection bits that can be set to protect either a portion or the
entire memory array from being Programmed/Erased or set the device to either Software Write Protection
(WP-E=0) or Hardware Write Protection (WP-E=1). Once the BP[3:0], TB, WP-E bits are set correctly,
SRP1 and SRP0 should also be set to “1”s as well to allow SR1-L bit being set to “1” to permanently lock
the protection settings in the Status Register-1 (SR1). Similar to the OTP-L setting procedure above, in
order to set SR1-L lock bit, the device must enter the “OTP Access Mode” (OTP-E=1) first, and SR1-L bit
should be set to “1” prior to the “Program Execute” command (Page Address is “don’t care”). Once SR1-L
is set to “1” (BUSY=0), the user can set OTP-E to “0” to return to the main memory array operation.
- 54 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.24
Parameter Page Data Definitions
The Parameter Page contains 3 identical copies of the 256-Byte Parameter Data. The table below lists all
the key data byte locations. All other unspecified byte locations have 00h data as default.
Byte
Number
Descriptions
0~3
4~5
6~7
8~9
10~31
32~43
Parameter page signature
Revision number
Feature supported
Optional command supported
Reserved
Device manufacturer
44~63
Device model
64
65~66
67~79
80~83
84~85
86~91
92~95
96~99
100
101
102
103~104
105~106
107
108~109
110
111
112
113
114
115~127
128
129~132
133~134
135~136
137~138
139~163
164~165
166~253
254~255
256~511
512~767
768~2175
Values
JEDEC manufacturer ID
Date code
Reserved
Number of data bytes per page
Number of spare bytes per page
Reserved
Number of pages per block
Number of blocks per logical unit
Number of logical units
Number of address bytes
Number of bits per cell
Bad blocks maximum per unit
Block endurance
Guaranteed valid blocks at beginning of target
Block endurance for guaranteed valid blocks
Number of programs per page
Reserved
Number of ECC bits
Number of plane address bits
Multi-plane operation attributes
Reserved
I/O pin capacitance, maximum
Reserved
Maximum page program time (us)
Maximum block erase time (us)
Maximum page read time (us)
Reserved
Vendor specific revision number
Vendor specific
Integrity CRC
Value of bytes 0~255
Value of bytes 0~255
Reserved
4Fh, 4Eh, 46h, 49h
00h, 00h
00h, 00h
00h, 00h
All 00h
57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h, 20h
57h, 32h, 35h, 4Eh, 30h, 34h, 4Bh, 56h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h
EFh
00h, 00h
All 00h
00h, 08h, 00h, 00h
80h, 00h
All 00h
40h, 00h, 00h, 00h
00h, 08h, 00h, 00h
02h
00h
01h
28h, 00h
01h, 05h
01h
00h, 00h
04h
00h
00h
00h
00h
All 00h
08h
00h, 00h, 00h, 00h
BCh, 02h
10h, 27h
3Ch, 00h
All 00h
00h, 00h
All 00h
61h, 0Ch
- 55 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.25
Deep Power-Down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Deep Power-Down instruction. The lower power consumption makes the Power-Down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics).
The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in
Figure 27.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down
instruction will not be executed. After /CS is driven high, the power-down state will entered within the time
duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down /
Device ID (Abh) and reset (66h+99h, FFh) instruction, which restores the device to normal operation, will
be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which
is always available during normal operation. Ignoring all but one instruction makes the Power Down state
a useful condition for securing maximum write protection. The device always powers-up in the normal
operation with the standby current of ICC1.
Figure 27. Deep Power-Down Instruction
- 56 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
8.2.26
Release Power-Down (ABh)
The Release from Power-Down instruction is used to release the device from the power-down state.
To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting
the instruction code “ABh” and driving /CS high as shown in Figure 28. Release from power-down will take
the time duration of tRES (See AC Characteristics) before the device will resume normal operation and other
instructions are accepted. The /CS pin must remain high during the tRES time duration.
Figure 28. Release Power-down Instruction
- 57 -
Publication Release Date: February 07, 2022
Revision C
W25N04KVxxIR/U
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings(1)
PARAMETERS
SYMBOL
Supply Voltage
CONDITIONS
VCC
RANGE
UNIT
–0.6 to 4.6
V
Voltage Applied to Any Pin
VIO
Relative to Ground
–0.6 to 4.6
V
Transient Voltage on any Pin
VIOT
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