W25P022AF-7

W25P022A 64K × 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM GENERAL DESCRIPTION The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM organized as 65,536 × 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium™ burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode reduces power dissipation. The W25P022A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to VDDQ. The state of pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data output in a burst read cycle when the device is deselected by CE2/ CE3 . This mode supports 3-1-1-11-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables data output within one cycle in a burst read cycle when the device is deselected by CE2/ CE3 . In this mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle. FEATURES • • • • • • • Synchronous operation High-speed access time: 6/7 nS (max.) Single +3.3V power supply Individual byte write capability 3.3V LVTTL compatible I/O Clock-controlled and registered input Asynchronous output enable • • • • • Pipelined/non-pipelined data output capability Supports snooze mode (low-power state) Internal burst counter supports Intel burst mode & linear burst mode Supports both 2T/2T & 2T/1T mode Packaged in 100-pin QFP or TQFP BLOCK DIAGRAM A(15:0) INPUT REGISTER 64K X 32 CORE ARRAY CLK CE(3:1) GW BWE BW(4:1) OE ADSC ADSP ADV LBO FT ZZ MS CONTROL LOGIC REGISTE R DATA I/O REGISTER I/O(32:1) -1- Publication Release Date: September 1996 Revision A1 W25P022A PIN CONFIGURATION / // C CB B A A E EWW 67124 3 / B W 2 / B W 1 / C V VC/ EDSLG 3 DSKW / B/ WO EE / A D S C / A D S P / A DAA V89 NC I/O 17 I/O 18 VDDQ VSSQ I/O 19 I/O 20 I/O 21 I/O 22 VSSQ VDDQ I/O 23 I/O 24 /FT VDD NC VSS I/O 25 I/O 26 VDDQ VSSQ I/O 27 I/O 28 I/O 29 I/O 30 VSSQ VDDQ I/O 31 I/O 32 NC 19999999999888888888 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 80 79 20 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 11 70 12 69 68 13 14 67 66 15 65 16 17 64 63 18 62 19 61 20 60 21 59 22 58 23 24 57 56 25 55 26 54 27 28 53 52 29 30 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 5 51 12345678901234567890 100-pin TQFP MO-136 QFP MO-108 NC I/O 16 I/O 15 VDDQ VSSQ I/O 14 I/O 13 I/O 12 I/O 11 VSSQ VDDQ I/O 10 I/O 9 VSS NC VDD ZZ I/O 8 I/O 7 VDDQ VSSQ I/O 6 I/O 5 I/O 4 I/O 3 VSSQ VDDQ I/O 2 I/O 1 NC / A AA AA A NNV VMN A A A AA AN L 5 4 3 2 1 0 C C S DS C 1 1 1 1 1 1 C B SD 012345 O -2- W25P022A PIN DESCRIPTION SYMBOL A0−A15 I/O1−I/O32 CLK CE1 , CE2, CE3 GW BWE BW1 − BW4 TYPE Input, Synchronous I/O, Synchronous Input, Clock Input, Synchronous Input, Synchronous Input, Synchronous Input, Synchronous Input, Asynchronous Input, Synchronous Input, Synchronous Input, Synchronous Input, Asynchronous Input, Static Host Address DESCRIPTION Data Inputs/Outputs Processor Host Bus Clock Chip Enables Global Write Byte Write Enable from Cache Controller Host Bus Byte Enables used with BWE Output Enable Input Internal Burst Address Counter Advance Address Status from chip set Address Status from CPU Snooze Pin for Low-power State, internally pulled low Connected to VSSQ: Device operates in flow-through (non-pipelined) mode. Connected to VDDQ or unconnected: Device operates in piplined mode. OE ADV ADSC ADSP ZZ FT LBO Input, Static Lower Address Burst Order Connected to VSSQ: Device operates in linear mode. Connected to VDDQ or unconnected: Device is in nonlinear mode. MS Input, Static Mode Select for 2T/2T or 2T/1T When unconnected or pulled low, device is in 2T/1T mode; if pulled high (VDDQ), device enters 2T/2T mode. VDDQ VSSQ VDD VSS NC I/O Power Supply I/O Ground Power Supply Ground No Connection -3- Publication Release Date: September 1996 Revision A1 W25P022A TRUTH TABLE CYCLE Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write Notes: 1. For a detailed definition of read/write, see the Write Table below. 2. An "X" means don't care, "1" means logic high, and "0" means logic low. 3. The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled to the bus clock except for the OE pin. 4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of the write cycle to allow write data to set the SRAM. OE must also disable the output buffer prior to the end of a write cycle to ensure the SRAM data hold timings are met. up synchronous ADDRESS USED No No No No No External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current CE1 1 0 0 0 0 0 0 X X 1 1 X X 1 1 X 1 0 X 1 X 1 CE2 X X 0 X 0 1 1 X X X X X X X X X X 1 X X X X CE3 X 1 X 1 X 0 0 X X X X X X X X X X 0 X X X X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 X 1 1 X 1 X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 ADV X X X X X X X 0 0 0 0 1 1 1 1 1 1 X 0 0 1 1 OE X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X DATA Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z D-Out Hi-Z D-Out Hi-Z D-Out Hi-Z D-Out Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z WRITE* X X X X X X Read Read Read Read Read Read Read Read Read Write Write Write Write Write Write Write -4- W25P022A FUNCTIONAL DESCRIPTION The W25P022A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for Intel™ systems and linear mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC and the burst counter is incremented whenever ADV is sampled low. The device can also be switched to nonpipelined mode if necessary. Burst Address Sequence INTEL SYSTEM (LBO = VDDQ) A[1:0] External Start Address Second Address Third Address Fourth Address 00 01 10 11 A[1:0] 01 00 11 10 A[1:0] 10 11 00 01 A[1:0] 11 10 01 00 LINEAR MODE (LBO = VSSQ) A[1:0] 00 01 10 11 A[1:0] 01 10 11 00 A[1:0] 10 11 00 01 A[1:0] 11 00 01 10 The device supports several types of write mode operations. BWE and BW [4:1] support individual byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [4:1]. The GW signal is used to override the byte enable signals and allows the cache controller to write all bytes to the SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM latches both data and valid byte enable signals from the processor. WRITE TABLE READ/WRITE FUNCTION Read Read Write byte 1 I/O1−I/O8 Write byte 2 I/O9−I/O16 Write byte 2, byte 1 Write byte 3 I/O17−I/O24 Write byte 3, byte 1 Write byte 3, byte 2 Write byte 3, byte 2, byte 1 Write byte 4 I/O25−I/O32 Write byte 4, byte 1 GW 1 1 1 1 1 1 1 1 1 1 1 BWE 1 0 0 0 0 0 0 0 0 0 0 BW4 X 1 1 1 1 1 1 1 1 0 0 BW3 X 1 1 1 1 0 0 0 0 1 1 BW2 X 1 1 0 0 1 1 0 0 1 1 BW1 X 1 0 1 0 1 0 1 0 1 0 -5- Publication Release Date: September 1996 Revision A1 W25P022A Write Table, continued READ/WRITE FUNCTION Write byte 4, byte 2 Write byte 4, byte 2, byte 1 Write byte 4, byte 3 Write byte 4, byte 3, byte 1 Write byte 4, byte 3, byte 2 Write all bytes I/O1−I/O32 Write all bytes I/O1−I/O32 GW 1 1 1 1 1 1 0 BWE 0 0 0 0 0 0 X BW4 0 0 0 0 0 0 X BW3 1 1 0 0 0 0 X BW2 0 0 1 1 0 0 X BW1 1 0 1 0 1 0 X The ZZ state is a low-power state in which the device consumes less power than in the unselected mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data retention is guaranteed, but the chip will not monitor any input signal except for the ZZ pin. In the unselected mode, on the other hand, all the input signals are monitored. ABSOLUTE MAXIMUM RATINGS PARAMETER Core Supply Voltage to Vss I/O Supply Voltage to Vss Input/Output to VSSQ Potential Allowable Power Dissipation Storage Temperaure Operating Temperature RATING -0.5 to 4.6 -0.5 to 4.6 VSSQ -0.5 to VDDQ +0.5 1.0 -65 to 150 0 to +70 UNIT V V V W °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. -6- W25P022A OPERATING CHARACTERISTICS (VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C) PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Current Standby Current SYM. VIL VIH ILI ILO TEST CONDITIONS VIN = VSSQ to VDDQ VI/O = VSSQ to VDDQ, and data I/O pins in high-Z state defined in truth table IOL = +8.0 mA IOH = -4.0 mA TCYC ≥ min., I/O = 0 mA Unselected mode defined in truth table, VIN, VIO = VIH (min.) /VIL (max.) TCYC ≥ min. ZZ mode, TCYC ≥ min. MIN. -0.5 +2.0 -10 -10 TYP . - MAX. +0.8 VDD +0.3 +10 + 10 UNIT V V µA µA VOL VOH IDD ISB 2.4 - - 0.4 250 80 V V mA mA ZZ Mode Current IZZ - - 5 mA Note: Typical characteristics are measured at VDD = 3.3V, TA = 25° C. CAPACITANCE (VDD = 3.3V, TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Input/Output Capacitance SYM. CIN CI/O CONDITIONS VIN = 0V VOUT = 0V MAX. 6 8 UNIT pF pF Note: These parameters are sampled but not 100% tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3V 2 nS 1.5V CL = 30 pF, IOH/IOL = -4 mA/8 mA CONDITIONS -7- Publication Release Date: September 1996 Revision A1 W25P022A AC TEST LOADS AND WAVEFORM RL = 50 ohm VL = 1.5V OUTPUT Zo = 50 ohm 30 pF Including Jig and Scope R1 320 ohm 3.3V OUTPUT 5 pF Including Jig and Scope R2 350 ohm (For TKHZ, TKLZ, TOHZ, TOLZ, measurement) 3.0V 0V 2 nS 90% 10% 10% 90% 2 nS AC TIMING CHARACTERISTICS (VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C, all timings measured in pipelined mode) PARAMETER Add. Setup Time Add. Hold Time Write Data Setup Time Write Data Hold Time ADV Setup Time ADV Hold Time ADSP Setup Time ADSP Hold Time ADSC Setup Time ADSC Hold Time CE1 , CE2, CE3 Setup Time CE1 , CE2, CE3 Hold Time GW , BWE X Setup Time GW , BWE X Hold Time SYM. TAS TAH TDS TDH TADVS TADVH TADSS TADSH TADCS TADCH TCES TCEH TWS TWH W25P022A-6 MIN. 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 MAX. - W25P022A-7 MIN. 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 2.5 0.5 MAX. - UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS NOTES -8- W25P022A AC Timing Characteristics, continued PARAMETER SYM. W25P022A-6 MIN. MAX. 6 13.3 6 6 100 - W25P022A-7 MIN. 15 6 6 2 0 2 0 0 100 MAX. 7 15 7 7 100 - UNIT NOTES Clock Cycle Time Clock High Pulsh Width Clock Low Pulse Width Clock to Output Valid Clock to Output High-Z Clock to Output Low-Z Clock to Output Invalid Output Enable to Output Valid Output Enable to Output High-Z Output Enable to Output Low-Z Output Enable to Output Invalid ZZ Standby Time ZZ Recover Time Notes: TCYC TKH TKL TKQ TKHZ TKLZ TKX TOE TOHZ TOLZ TOX TZZS TZZR 13.3 5 5 2 0 2 0 0 100 nS nS nS nS nS nS nS nS nS nS nS nS nS 2 3 1 1 1 1 1 1. These parameters are sampled but not 100% tested 2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active. 3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode. 4. Configuration signals LBO and FT are static and should not be changed during operation. -9- Publication Release Date: September 1996 Revision A1 W25P022A TIMING WAVEFORMS Read Cycle Timing Pipelined Read Single Read CLK TADSS ADSP TADCS TADCH ADSC T ADVS ADV TAS A[15:0] TAH RD1 TWS GW TWS BWE TWH TWH RD2 RD3 TADVH Suspend Burst ADSC initiated read TADSH TCYC TKH T KL ADSP is blocked by CE1 inactive Burst Read Unselected BW[4:1] T CES CE1 TCES CE2 TCES CE3 TOE OE TOLZ Data-Out High-Z T KLZ TKQ Data-In High-Z TKHZ 1a TOX TKX 2a 2b 2c 2d 3a T KX TOHZ TCEH TCEH CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 TCEH CE1 masks ADSP DON'T CARE UNDEFINED - 10 - W25P022A Timing Waveforms, continued Write Cycle Timing Single Write CLK T KH TKL TADSS ADSP TADCS ADSC TADVS ADV T AS T AH A[15:0] WR1 TWS GW TWS BWE TWS BW[4:1] TCES CE1 TCES CE2 TCES CE3 TCEH TCEH CE2 and CE3 only sampled with ADSP or ADSC Unselected with CE2 T CEH TWH WR2 CE1 masks ADSP WR3 T WH T WH ADV must be inactive for ADSP write WR2 WR3 GWE allows processor address (and BE=BW) to be pipelined during a writeback TADVH TADCH ADSC initiated write T ADSH ADSP is blocked by CE1 inactive Burst Write Write Unselected TCYC WR1 OE Data-Out High-Z T DS TDH BW[4:1] are applied only to first cycle of WR2 2a 2b 2c 2d 3a Data-In High-Z 1a DON'T CARE UNDEFINED - 11 - Publication Release Date: September 1996 Revision A1 W25P022A Timing Waveforms, continued Read/Write Cycle Timing Single Read CLK TADSS ADSP TADSH Single Write T CYC TKH T KL Burst Read Unselected ADSP is blocked by CE1 inactive TADCS TADCH ADSC TADVS ADV T AS A[15:0] T AH WR1 TWS GW TWS BWE T WH T WH TADVH ADSC initiated read Suspend Burst RD1 RD2 TWS TWH BW[4:1] TCES CE1 TCES CE2 TCES CE3 TOE OE T OLZ Data-Out High-Z TKLZ T KQ Data-In High-Z 1a TKHZ TDSTDH 1a T OH 2a 2b 2c 2d T KHZ TKX T OHZ TCEH Unselected with CE3 TCEH CE2 and CE3 only sampled with ADSP or ADSC TCEH WR1 CE1 masks ADSP DON'T CARE UNDEFINED - 12 - W25P022A Timing Waveforms, continued ZZ and RD Timing Single Read CLK TADSS ADSP TADSH TCYC TKH TKL Snooze -with Data Retention Read ADSC TADVS ADV TAS A[15:0] RD1 TWS GW TWS BWE TWS BW[4:1] TCES CE1 TCES CE2 TCES CE3 TOE OE TOLZ Data-Out High-Z TKLZ TKQ Data-In High-Z 1a TKX TKHZ TOH TOHZ TCEH TCEH TCEH RD TWH RD RD TWH TWH TAH RD2 TADVH TZZS ZZ TZZR DON'T CARE UNDEFINED - 13 - Publication Release Date: September 1996 Revision A1 W25P022A Timing Waveforms, continued Dual-bank Burst Read Cycle CLK Select Bank 0 ADSP Select Bank 1 ADSC ADV A[31:3] Read 1 Read 2 GW BWE BW[4:1] CE1 CE[3:2] Bank 0 Active NonActive CE[3:2] Bank 1 NonActive Active OE D[63:0] Bank 0 D[63:0] Bank 1 1a 1b 1c 1d 2a 2b 2c 2d DON'T CARE UNDEFINED - 14 - W25P022A ORDERING INFORMATION PART NO. ACCESS TIME (nS) 6 7 6 7 OPERATING CURRENT MAX. (mA) 250 250 250 250 STANDBY CURRENT MAX. (mA) 80 80 80 80 PACKAGE W25P022AF-6 W25P022AF-7 W25P022AD-6 W25P022AD-7 Notes: 100-pin QFP 100-pin QFP 100-pin TQFP 100-pin TQFP 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 15 - Publication Release Date: September 1996 Revision A1 W25P022A PACKAGE DIMENSIONS 100-pin QFP Symbol HD D Dimension in inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.01 0.014 0.018 0.113 0.016 0.008 0.555 0.032 0.25 2.57 0.20 0.10 13.90 0.35 2.72 0.30 0.15 0.45 2.87 0.40 0.20 E HE A A1 A2 b c D E e HD HE L L1 y θ Notes: 0.101 0.107 0.008 0.012 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.026 0.669 0.905 0.025 0.677 0.913 0.031 0.063 14.00 14.10 20.00 20.10 0.802 17.40 23.40 0.95 17.20 23.20 0.80 1.60 0.791 19.90 0.685 17.00 0.921 23.00 0.037 0.003 0.65 0.498 0.65 0.08 0 7 0 7 e b 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. C A2 See Detail F A1 y L L1 Seating Plane 100-pin TQFP Symbol HD D Dimension in inches Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.002 0.004 0.053 0.055 0.009 0.013 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.026 0.626 0.862 0.018 0.630 0.866 0.024 0.039 0.003 0 7 0 0.006 0.057 0.015 0.008 0.555 0.032 0.05 1035 0.22 0.10 13.90 0.10 1.40 0.32 0.15 0.15 1.45 0.38 0.20 E HE A A1 A2 b c D E e HD HE L L1 y θ Notes: 14.00 14.10 20.00 20.10 0.802 16.00 16.10 22.00 22.10 0.60 1.00 0.08 7 0.75 0.791 19.90 0.634 15.90 0.870 21.90 0.030 0.45 0.498 0.65 e b 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. C A2 See Detail F A1 y L L1 Seating Plane - 16 - W25P022A Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 17 - Publication Release Date: September 1996 Revision A1