W25Q128JVSIQ

W25Q128JV 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI Publication Release Date: November 16, 2016 Revision C W25Q128JV Table of Contents 1. GENERAL DESCRIPTIONS ............................................................................................................. 4 2. FEATURES ....................................................................................................................................... 4 3. PACKAGE TYPES AND PIN CONFIGURATIONS........................................................................... 5 4. 3.1 Pin Configuration SOIC 208-mil ........................................................................................... 5 3.2 Pad Configuration WSON 6x5-mm/ 8x6-mm ....................................................................... 5 3.3 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm ................................................... 5 3.4 Pin Configuration SOIC 300-mil ........................................................................................... 6 3.5 Pin Description SOIC 300-mil ............................................................................................... 6 3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 7 3.7 Ball Description TFBGA 8x6-mm ......................................................................................... 7 PIN DESCRIPTIONS ........................................................................................................................ 8 4.1 Chip Select (/CS) .................................................................................................................. 8 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 8 4.3 Serial Clock (CLK) ................................................................................................................ 8 4.4 Reset (/RESET) .................................................................................................................... 8 5. BLOCK DIAGRAM ............................................................................................................................ 9 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 10 6.1 Standard SPI Instructions ................................................................................................... 10 6.2 Dual SPI Instructions .......................................................................................................... 10 6.3 Quad SPI Instructions ......................................................................................................... 10 6.4 Software Reset & Hardware /RESET pin ........................................................................... 10 6.5 Write Protection .................................................................................................................. 11 6.5.1 7. Write Protect Features ......................................................................................................... 11 STATUS AND CONFIGURATION REGISTERS ............................................................................ 12 7.1 Status Registers ................................................................................................................. 12 7.1.1 Erase/Write In Progress (BUSY) – Status Only ................................................................ 12 7.1.2 Write Enable Latch (WEL) – Status Only .......................................................................... 12 7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable ................................ 12 7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable ....................................... 13 7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable ....................................... 13 7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable ............................................ 13 7.1.7 Status Register Protect (SRL) .............................................................................................. 14 7.1.8 Erase/Program Suspend Status (SUS) – Status Only....................................................... 14 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable .......... 14 7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable ........................................................ 15 -1- W25Q128JV 8. 7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable ..................................... 15 7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable ......................... 15 7.1.13 Reserved Bits – Non Functional ...................................................................................... 15 7.1.14 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 0) ............................. 16 7.1.15 W25Q128JV Status Register Memory Protection (WPS = 0, CMP = 1) ............................. 17 7.1.16 W25Q128JV Individual Block Memory Protection (WPS=1) .............................................. 18 INSTRUCTIONS ............................................................................................................................. 19 8.1 Device ID and Instruction Set Tables ................................................................................. 19 8.1.1 Manufacturer and Device Identification ................................................................................ 19 8.1.2 Instruction Set Table 1 (Standard SPI Instructions) (1)........................................................... 20 8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions) ........................................................... 21 Notes:................................................................................................................................................ 21 8.2 Instruction Descriptions ...................................................................................................... 22 8.2.1 Write Enable (06h) ............................................................................................................... 22 8.2.2 Write Enable for Volatile Status Register (50h) .................................................................... 22 8.2.3 Write Disable (04h)............................................................................................................... 23 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 23 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 24 8.2.6 Read Data (03h) ................................................................................................................... 26 8.2.7 Fast Read (0Bh) ................................................................................................................... 27 8.2.8 Fast Read Dual Output (3Bh) ............................................................................................... 28 8.2.9 Fast Read Quad Output (6Bh) .............................................................................................. 29 8.2.10 Fast Read Dual I/O (BBh) ................................................................................................... 30 8.2.11 Fast Read Quad I/O (EBh) ................................................................................................. 31 8.2.12 Set Burst with Wrap (77h) .................................................................................................. 33 8.2.13 Page Program (02h) ........................................................................................................... 34 8.2.14 Quad Input Page Program (32h) ........................................................................................ 35 8.2.15 Sector Erase (20h) ............................................................................................................. 36 8.2.16 32KB Block Erase (52h) ..................................................................................................... 37 8.2.17 64KB Block Erase (D8h) ..................................................................................................... 38 8.2.18 Chip Erase (C7h / 60h) ....................................................................................................... 39 8.2.19 Erase / Program Suspend (75h) ......................................................................................... 40 8.2.20 Erase / Program Resume (7Ah) ......................................................................................... 41 8.2.21 Power-down (B9h) .............................................................................................................. 42 8.2.22 Release Power-down / Device ID (ABh) ............................................................................. 43 8.2.23 Read Manufacturer / Device ID (90h) ................................................................................. 44 8.2.24 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 45 8.2.25 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 46 8.2.26 Read Unique ID Number (4Bh)........................................................................................... 47 8.2.27 Read JEDEC ID (9Fh) ........................................................................................................ 48 8.2.28 Read SFDP Register (5Ah) ................................................................................................ 49 -2- Publication Release Date: November 16, 2016 Revision C W25Q128JV 9. 10. 11. Erase Security Registers (44h) ........................................................................................... 50 8.2.30 Program Security Registers (42h) ...................................................................................... 51 8.2.31 Read Security Registers (48h) ........................................................................................... 52 8.2.32 Individual Block/Sector Lock (36h) ..................................................................................... 53 8.2.33 Individual Block/Sector Unlock (39h) .................................................................................. 54 8.2.34 Read Block/Sector Lock (3Dh) ........................................................................................... 55 8.2.35 Global Block/Sector Lock (7Eh) .......................................................................................... 56 8.2.36 Global Block/Sector Unlock (98h) ....................................................................................... 56 8.2.37 Enable Reset (66h) and Reset Device (99h) ...................................................................... 57 ELECTRICAL CHARACTERISTICS ............................................................................................... 58 9.1 Absolute Maximum Ratings (1) ............................................................................................ 58 9.2 Operating Ranges............................................................................................................... 58 9.3 Power-Up Power-Down Timing and Requirements ............................................................ 59 9.4 DC Electrical Characteristics- ............................................................................................. 60 9.5 AC Measurement Conditions .............................................................................................. 61 9.6 AC Electrical Characteristics(6) ........................................................................................... 62 9.7 Serial Output Timing ........................................................................................................... 64 9.8 Serial Input Timing .............................................................................................................. 64 PACKAGE SPECIFICATIONS ........................................................................................................ 65 10.1 8-Pin SOIC 208-mil (Package Code S) .............................................................................. 65 10.2 16-Pin SOIC 300-mil (Package Code F) ............................................................................ 66 10.3 8-Pad WSON 6x5-mm (Package Code P) ......................................................................... 67 10.4 8-Pad WSON 8x6-mm (Package Code E) ......................................................................... 68 10.5 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array) ............................................ 69 10.6 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 ball array) ............................................... 70 ORDERING INFORMATION .......................................................................................................... 71 11.1 12. 8.2.29 Valid Part Numbers and Top Side Marking ........................................................................ 72 REVISION HISTORY ...................................................................................................................... 73 -3- W25Q128JV 1. GENERAL DESCRIPTIONS The W25Q128JV (128M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages. The W25Q128JV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128JV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See Figure 2.) The W25Q128JV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 and I/O3. SPI clock frequencies of W25Q128JV of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP, and a 64-bit Unique Serial Number and three 256-bytes Security Registers. 2. FEATURES   New Family of SpiFlash Memories – W25Q128JV: 128M-bit / 16M-byte – Standard SPI: CLK, /CS, DI, DO – Dual SPI: CLK, /CS, IO0, IO1 – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – Software & Hardware Reset(1)  Highest Performance Serial Flash – 133MHz Single, Dual/Quad SPI clocks – 266/532MHz equivalent Dual/Quad SPI – 66MB/S continuous data transfer rate – Min. 100K Program-Erase cycles per sector – More than 20-year data retention  Efficient “Continuous Read” – Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Allows true XIP (execute in place) operation  Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply –