W25Q16DVSSIQ

3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI -1- Publication Release Date: January 26, 2015 Revision J Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................... 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 6 4. 3.1 Pin Configuration SOIC 150 / 208-mil .................................................................................. 6 3.2 Pad Configuration WSON 6x5-mm / USON 4X3-mm / USON 4X4-mm .............................. 6 3.3 Pin Configuration PDIP 300-mil............................................................................................ 7 3.4 Pin Description SOIC 150/208-mil, WSON 6x5-mm / USON 4x3-mm / PDIP 300-mil ........ 7 3.5 Pin Configuration SOIC 300-mil ........................................................................................... 8 3.6 Pin Description SOIC 300-mil............................................................................................... 8 3.7 Ball Configuration TFBGA 8x6MM ....................................................................................... 9 3.8 Ball Description TFBGA 8x6-mm ......................................................................................... 9 PIN DESCRIPTIONS ...................................................................................................................... 10 4.1 Chip Select (/CS) ................................................................................................................ 10 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 10 4.3 Write Protect (/WP)............................................................................................................. 10 4.4 HOLD (/HOLD) ................................................................................................................... 10 4.5 Serial Clock (CLK) .............................................................................................................. 10 5. BLOCK DIAGRAM .......................................................................................................................... 11 6. FUNCTIONAL DESCRIPTION ....................................................................................................... 12 6.1 6.2 SPI OPERATIONS ............................................................................................................. 12 6.1.1 Standard SPI Instructions ..................................................................................................... 12 6.1.2 Dual SPI Instructions ............................................................................................................ 12 6.1.3 Quad SPI Instructions ........................................................................................................... 12 6.1.4 Hold Function........................................................................................................................ 12 WRITE PROTECTION ....................................................................................................... 13 6.2.1 7. Write Protect Features .......................................................................................................... 13 STATUS REGISTERS AND INSTRUCTIONS ............................................................................... 14 7.1 STATUS REGISTERS........................................................................................................ 14 7.1.1 BUSY Status (BUSY) ............................................................................................................ 14 7.1.2 Write Enable Latch Status (WEL) ......................................................................................... 14 7.1.3 Block Protect Bits (BP2, BP1, BP0) ...................................................................................... 14 7.1.4 Top/Bottom Block Protect Bit (TB) ........................................................................................ 14 7.1.5 Sector/Block Protect Bit (SEC) ............................................................................................. 14 7.1.6 Complement Protect Bit (CMP)............................................................................................. 14 7.1.7 Status Register Protect Bits (SRP1, SRP0) .......................................................................... 15 7.1.8 Erase/Program Suspend Status (SUS) ................................................................................. 15 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) ......................................................................... 15 7.1.10 Quad Enable Bit (QE) ......................................................................................................... 15 -2- 7.2 7.1.11 Status Register Memory Protection (CMP = 0) ................................................................... 17 7.1.12 Status Register Memory Protection (CMP = 1) ................................................................... 18 INSTRUCTIONS................................................................................................................. 19 7.2.1 Manufacturer and Device Identification ................................................................................. 19 7.2.2 Instruction Set Table 1 (Erase, Program Instructions)(1) ....................................................... 20 7.2.3 Instruction Set Table 2 (Read Instructions) ........................................................................... 21 7.2.4 Instruction Set Table 3 (ID, Security Instructions) ................................................................. 22 7.2.5 Write Enable (06h) ................................................................................................................ 23 7.2.6 Write Enable for Volatile Status Register (50h) ..................................................................... 23 7.2.7 Write Disable (04h) ............................................................................................................... 24 7.2.8 Read Status Register-1 (05h) and Read Status Register-2 (35h) ......................................... 25 7.2.9 Write Status Register (01h)................................................................................................... 25 7.2.10 Read Data (03h) ................................................................................................................. 27 7.2.11 Fast Read (0Bh) ................................................................................................................. 28 7.2.12 Fast Read Dual Output (3Bh) ............................................................................................. 29 7.2.13 Fast Read Quad Output (6Bh) ............................................................................................ 30 7.2.14 Fast Read Dual I/O (BBh) ................................................................................................... 31 7.2.15 Fast Read Quad I/O (EBh) ................................................................................................. 33 7.2.16 Word Read Quad I/O (E7h) ................................................................................................ 35 7.2.17 Octal Word Read Quad I/O (E3h) ....................................................................................... 37 7.2.18 Set Burst with Wrap (77h) ................................................................................................... 39 7.2.19 Continuous Read Mode Bits (M7-0) .................................................................................... 40 7.2.20 Continuous Read Mode Reset (FFh or FFFFh) .................................................................. 40 7.2.21 Page Program (02h) ........................................................................................................... 41 7.2.22 Quad Input Page Program (32h) ......................................................................................... 42 7.2.23 Sector Erase (20h) .............................................................................................................. 42 7.2.24 32KB Block Erase (52h)...................................................................................................... 44 7.2.25 64KB Block Erase (D8h) ..................................................................................................... 45 7.2.26 Chip Erase (C7h / 60h) ....................................................................................................... 46 7.2.27 Erase / Program Suspend (75h) ......................................................................................... 47 7.2.28 Erase / Program Resume (7Ah).......................................................................................... 48 7.2.29 Power-down (B9h) .............................................................................................................. 49 7.2.30 Release Power-down / Device ID (ABh) ............................................................................. 50 7.2.31 Read Manufacturer / Device ID (90h) ................................................................................. 52 7.2.32 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 53 7.2.33 Read Manufacturer / Device ID Quad I/O (94h) .................................................................. 54 7.2.34 Read Unique ID Number (4Bh) ........................................................................................... 55 7.2.35 Read JEDEC ID (9Fh) ........................................................................................................ 56 7.2.36 Read SFDP Register (5Ah)................................................................................................. 57 7.2.37 Erase Security Registers (44h) ........................................................................................... 58 7.2.38 Program Security Registers (42h) ....................................................................................... 59 -3- Publication Release Date: January 26, 2015 Revision J 8. 9. 10. Read Security Registers (48h) ............................................................................................ 60 7.2.40 Enable Reset (66h) and Reset (99h) .................................................................................. 61 ELECTRICAL CHARACTERISTICS .............................................................................................. 62 8.1 Absolute Maximum Ratings (1) .......................................................................................... 62 8.2 Operating Ranges .............................................................................................................. 62 8.3 Power-Up Power-Down Timing and Requirements ........................................................... 63 8.4 DC Electrical Characteristics .............................................................................................. 64 8.5 AC Measurement Conditions ............................................................................................. 65 8.6 AC Electrical Characteristics .............................................................................................. 66 8.7 AC Electrical Characteristics (cont’d) ................................................................................. 67 8.8 Serial Output Timing ........................................................................................................... 68 8.9 Serial Input Timing.............................................................................................................. 68 8.10 /HOLD Timing ..................................................................................................................... 68 8.11 /WP Timing ......................................................................................................................... 68 PACKAGE SPECIFICATION .......................................................................................................... 69 9.1 8-Pin SOIC 150-mil (Package Code SN) ........................................................................... 69 9.2 8-Pin SOIC 208-mil (Package Code SS) ........................................................................... 70 9.3 8-Pin PDIP 300-mil (Package Code DA)............................................................................ 71 9.4 8-Pad WSON 6x5mm (Package Code ZP) ........................................................................ 72 9.5 8-Pad USON 4x3-mm (Package Code UU) ....................................................................... 73 9.6 8-Pad USON 4x4-mm (Package Code UZ) ....................................................................... 74 9.7 16-Pin SOIC 300-mil (Package Code SF).......................................................................... 74 9.8 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array) ......................................... 76 9.9 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) ............................................ 76 ORDERING INFORMATION .......................................................................................................... 78 10.1 11. 7.2.39 Valid Part Numbers and Top Side Marking ........................................................................ 79 REVISION HISTORY ...................................................................................................................... 80 -4- 1. GENERAL DESCRIPTION The W25Q16DV (16M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. The W25Q16DV array is organized into 8,192 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q16DV has 512 erasable sectors and 32 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q16DV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES  Family of SpiFlash Memories – W25Q16DV: 16M-bit / 2M-byte (2,097,152) – 256-byte per programmable page – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – -40°C to +85°C operating range  Flexible Architecture with 4KB sectors – Uniform Sector/Block Erase (4/32/64K-bytes) – Program one to 256 bytes – Erase/Program Suspend & Resume  Advanced Security & Identification Features – Software and Hardware Write-Protect – Top/Bottom, 4KB complement array protection – Power Supply Lock-Down and OTP protection – 64-Bit Unique ID for each device – Discoverable Parameters (SFDP) Register – 3X256-Byte Security Registers with OTP locks – Volatile & Non-volatile Status Register Bits  Highest Performance Serial Flash – 104MHz Dual SPI / Quad SPI clocks – 208/416MHz equivalent Dual/Quad SPI – 52MB/S continuous data transfer rate – Up to 8X that of ordinary Serial Flash – More than 100,000 erase/program cycles – More than 20-year data retention  Efficient “Continuous Read Mode” – Low Instruction overhead – Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash  Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current,