W25Q256JVFIQ

W25Q256JV 3V 256M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI Publication Release Date: February 10, 2017 Revision E W25Q256JV Table of Contents 1. GENERAL DESCRIPTIONS ........................................................................................................ 5 2. FEA6B TURES5 3. 4. PACKAGE TYPES AND PIN CONFIGURATIONS ....................................................................... 6 3.1 Pad Configuration WSON 8x6-mm ................................................................................... 6 3.2 Pad Description WSON 8x6-mm ...................................................................................... 6 3.3 Pin Configuration SOIC 300-mil........................................................................................ 7 3.4 Pin Description SOIC 300-mil ........................................................................................... 7 3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ............................................... 8 3.6 Ball Description TFBGA 8x6-mm ...................................................................................... 8 PIN DESCRIPTIONS ................................................................................................................... 9 4.1 Chip Select (/CS) ............................................................................................................. 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 9 4.3 Serial Clock (CLK) ........................................................................................................... 9 4.4 Reset (/RESET) ............................................................................................................... 9 5. BLOCK DIAGRAM ..................................................................................................................... 10 6. FUNCTIONAL DESCRIPTIONS................................................................................................. 11 6.1 6.2 7. SPI Operations .............................................................................................................. 11 6.1.1 Standard SPI Instructions ..................................................................................................... 11 6.1.2 Dual SPI Instructions ............................................................................................................ 11 6.1.3 Quad SPI Instructions ........................................................................................................... 11 6.1.4 3-Byte / 4-Byte Address Modes ............................................................................................ 12 6.1.5 Software Reset & Hardware /RESET pin ............................................................................. 13 Write Protection ............................................................................................................. 14 STATUS AND CONFIGURATION REGISTERS ......................................................................... 15 7.1 Status Registers ............................................................................................................ 15 7.1.1 Erase/Write In Progress (BUSY) – Status Only................................................................. 15 7.1.2 Write Enable Latch (WEL) – Status Only .......................................................................... 15 7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) – Volatile/Non-Volatile Writable........................ 16 7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable ....................................... 16 7.1.5 Complement Protect (CMP) – Volatile/Non-Volatile Writable ............................................ 16 7.1.6 Status Register Protect (SRL) – Volatile/Non-Volatile Writable ......................................... 16 7.1.7 Erase/Program Suspend Status (SUS) – Status Only....................................................... 17 7.1.8 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable .......... 17 7.1.9 Quad Enable (QE) – Volatile/Non-Volatile Writable........................................................... 17 7.1.10 Current Address Mode (ADS) – Status Only ................................................................... 18 -1- W25Q256JV 7.2 8. 7.1.11 Power-Up Address Mode (ADP) – Non-Volatile Writable ................................................ 18 7.1.12 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable ...................................... 18 7.1.13 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable .......................... 19 7.1.14 Reserved Bits – Non Functional ...................................................................................... 19 7.1.15 W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 0) ............................. 20 7.1.16 W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 1) ............................. 21 7.1.17 W25Q256JV Individual Block Memory Protection (WPS=1) .............................................. 22 Extended Address Register – Volatile Writable Only ................................................... 23 INSTRUCTIONS ........................................................................................................................ 24 8.1 8.2 Device ID and Instruction Set Tables ............................................................................. 24 8.1.1 Manufacturer and Device Identification ................................................................................ 24 8.1.2 Instruction Set Table 1 (Standard/Dual/Quad SPI, 3-Byte Address Mode)(1) ....................... 25 8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions,3-Byte Address Mode)........................ 26 8.1.4 Instruction Set Table 3 (Standard SPI, 4-Byte Address Mode)(1).......................................... 27 8.1.5 Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode)....................... 28 Instruction Descriptions .................................................................................................. 30 8.2.1 Write Enable (06h)................................................................................................................ 30 8.2.2 Write Enable for Volatile Status Register (50h) .................................................................... 30 8.2.3 Write Disable (04h) ............................................................................................................... 31 Figure 7. Write Disable Instruction for SPI Mode .............................................................................. 31 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 31 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 32 8.2.6 Read Extended Address Register (C8h) .............................................................................. 34 8.2.7 Write Extended Address Register (C5h)............................................................................... 35 8.2.8 Enter 4-Byte Address Mode (B7h) ........................................................................................ 36 8.2.9 Exit 4-Byte Address Mode (E9h) .......................................................................................... 36 8.2.10 Read Data (03h) ................................................................................................................. 37 8.2.11 Read Data with 4-Byte Address (13h) ................................................................................ 38 8.2.12 Fast Read (0Bh) ................................................................................................................. 39 8.2.13 Fast Read with 4-Byte Address (0Ch) ................................................................................ 40 8.2.14 Fast Read Dual Output (3Bh) ............................................................................................. 41 8.2.15 Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 42 8.2.16 Fast Read Quad Output (6Bh)............................................................................................ 43 8.2.17 Fast Read Quad Output with 4-Byte Address (6Ch)........................................................... 44 8.2.18 Fast Read Dual I/O (BBh) ................................................................................................... 45 8.2.19 Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 46 8.2.20 Fast Read Quad I/O (EBh) ................................................................................................. 47 8.2.21 Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................ 48 8.2.22 Set Burst with Wrap (77h) .................................................................................................. 49 8.2.23 Page Program (02h) ........................................................................................................... 50 8.2.24 Page Program with 4-Byte Address (12h) .......................................................................... 51 8.2.25 Quad Input Page Program (32h) ........................................................................................ 52 -2- Publication Release Date: February 10, 2017 Revision E W25Q256JV 9. 8.2.26 Quad Input Page Program with 4-Byte Address (34h) ....................................................... 53 8.2.27 Sector Erase (20h) ............................................................................................................. 54 8.2.28 Sector Erase with 4-Byte Address (21h) ............................................................................. 55 8.2.29 32KB Block Erase (52h) ..................................................................................................... 56 8.2.30 64KB Block Erase (D8h) ..................................................................................................... 57 8.2.31 64KB Block Erase with 4-Byte Address (DCh) ................................................................... 58 8.2.32 Chip Erase (C7h / 60h) ....................................................................................................... 59 8.2.33 Erase / Program Suspend (75h) ......................................................................................... 60 8.2.34 Erase / Program Resume (7Ah) ......................................................................................... 61 8.2.35 Power-down (B9h) .............................................................................................................. 62 8.2.36 Release Power-down / Device ID (ABh) ............................................................................. 63 8.2.37 Read Manufacturer / Device ID (90h) ................................................................................. 64 8.2.38 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 65 8.2.39 Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 66 8.2.40 Read Unique ID Number (4Bh)........................................................................................... 67 8.2.41 Read JEDEC ID (9Fh) ........................................................................................................ 68 8.2.42 Read SFDP Register (5Ah) ................................................................................................ 69 8.2.43 Erase Security Registers (44h) ........................................................................................... 70 8.2.44 Program Security Registers (42h) ...................................................................................... 71 8.2.45 Read Security Registers (48h)............................................................................................ 72 8.2.46 Individual Block/Sector Lock (36h) ..................................................................................... 73 8.2.47 Individual Block/Sector Unlock (39h) .................................................................................. 74 8.2.48 Read Block/Sector Lock (3Dh) ........................................................................................... 75 8.2.49 Global Block/Sector Lock (7Eh) .......................................................................................... 76 8.2.50 Global Block/Sector Unlock (98h) ....................................................................................... 76 8.2.51 Enable Reset (66h) and Reset Device (99h) ...................................................................... 77 ELECTRICAL CHARACTERISTICS ........................................................................................... 78 9.1 Absolute Maximum Ratings (1) ...................................................................................... 78 9.2 Operating Ranges .......................................................................................................... 78 9.3 Power-up Power-down Timing and Requirements .......................................................... 79 9.4 DC Electrical Characteristics .......................................................................................... 80 9.5 AC Measurement Conditions .......................................................................................... 81 9.6 AC Electrical Characteristics(6) ....................................................................................... 82 9.7 AC Electrical Characteristics (cont’d) ........................................................................... 83 9.8 Serial Output Timing ...................................................................................................... 84 9.9 Serial Input Timing ......................................................................................................... 84 9.10 PACKAGE SPECIFICATIONs ........................................................................................ 85 9.11 8-Pad WSON 8x6-mm (Package Code E) ...................................................................... 85 9.12 16-Pin SOIC 300-mil (Package Code F) ......................................................................... 86 9.13 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array) ......................................... 87 -3- W25Q256JV 10. 9.14 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array) ............................................ 88 9.15 Ordering Information ...................................................................................................... 89 9.16 Valid Part Numbers and Top Side Marking ..................................................................... 90 REVISION HISTORY ................................................................................................................. 91 -4- Publication Release Date: February 10, 2017 Revision E W25Q256JV 1. GENERAL DESCRIPTIONS The W25Q256JV (256M-bit) Serial Flash memory provides a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption as low as 1µA for power-down. All devices are offered in space-saving packages. The W25Q256JV array is organized into 131,072 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q256JV has 8,192 erasable sectors and 512 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. The W25Q256JV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2, and I/O3. SPI clock frequencies of W25Q256JV of up to 133MHz are supported allowing equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64bit Unique Serial Number and three 256-bytes Security Registers. 2. FEATURES • New Family of SpiFlash Memories – W25Q256JV: 256M-bit / 32M-byte – Standard SPI: CLK, /CS, DI, DO – Dual SPI: CLK, /CS, IO0, IO1, – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – 3 or 4-Byte Addressing Mode – Software & Hardware Reset • Flexible Architecture with 4KB sectors – Uniform Sector/Block Erase (4K/32K/64K-Byte) – Program 1 to 256 byte per programmable page – Erase/Program Suspend & Resume • Advanced Security Features – Software Write-Protect – Power Supply Lock-Down – Special OTP protection – Top/Bottom, Complement array protection – Individual Block/Sector array protection – 64-Bit Unique ID for each device – Discoverable Parameters (SFDP) Register – 3X256-Bytes Security Registers with OTP locks – Volatile & Non-volatile Status Register Bits • Highest Performance Serial Flash – 133MHz Standard/Dual/Quad SPI clocks – 266/532MHz equivalent Dual/Quad SPI – 66MB/S continuous data transfer rate – Min. 100K Program-Erase cycles per sector – More than 20-year data retention • Efficient “Continuous Read” – Quad Peripheral Interface – Allows true XIP (execute in place) operation – Outperforms X16 Parallel Flash • Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply –