W25Q40CLZPIG

W25Q40CL 2.5/3/3.3V 4 M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS, DUAL AND QUAD SPI - 1 - Publication Release Date: October 31, 2014 Revision D1 W25Q40CL Table of Contents 1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 5 FEATURES ................................................................................................................................. 5 PIN CONFIGURATION SOIC 150-MIL, VSOP 150-MIL, TSSOP 173-MIL ................................ 6 PAD CONFIGURATION USON 2X3-MM ................................................................................... 6 PIN DESCRIPTION SOIC 150-MIL ............................................................................................ 6 5.1 Package Types ............................................................................................................... 7 5.2 Chip Select (/CS) ............................................................................................................ 7 5.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)............................... 7 5.4 Write Protect (/WP) ......................................................................................................... 7 5.5 HOLD (/HOLD)................................................................................................................ 7 5.6 Serial Clock (CLK) .......................................................................................................... 7 BLOCK DIAGRAM ...................................................................................................................... 8 FUNCTIONAL DESCRIPTION.................................................................................................... 9 7.1 SPI OPERATIONS ......................................................................................................... 9 7.1.1 7.1.2 7.1.3 7.1.4 7.2 WRITE PROTECTION .................................................................................................. 10 7.2.1 8. Write Protect Features.................................................................................................... 10 CONTROL AND STATUS REGISTERS ................................................................................... 11 8.1 STATUS REGISTER .................................................................................................... 11 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 9. Standard SPI Instructions ................................................................................................. 9 Dual SPI Instructions ........................................................................................................ 9 Quad SPI Instructions....................................................................................................... 9 Hold Function ................................................................................................................... 9 BUSY.............................................................................................................................. 11 Write Enable Latch (WEL) .............................................................................................. 11 Block Protect Bits (BP2, BP1, BP0) ................................................................................ 11 Top/Bottom Block Protect (TB) ....................................................................................... 11 Sector/Block Protect (SEC) ............................................................................................ 11 Complement Protect (CMP) ........................................................................................... 11 Status Register Protect (SRP1, SRP0)........................................................................... 12 Erase/Program Suspend Status (SUS) .......................................................................... 12 Security Register Lock Bits (LB3, LB2, LB1, LB0) .......................................................... 12 Quad Enable (QE) ........................................................................................................ 13 Status Register Memory Protection (CMP = 0)............................................................. 14 Status Register Memory Protection (CMP = 1)............................................................. 15 INSTRUCTIONS ....................................................................................................................... 16 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 Manufacturer and Device Identification .......................................................................... 16 Instruction Set Table 1 (Erase, Program Instructions) .................................................... 17 Instruction Set Table 2 (Read Instructions) .................................................................... 18 Instruction Set Table 3 (ID, Security Instructions) .......................................................... 19 Write Enable (06h).......................................................................................................... 20 Write Enable for Volatile Status Register (50h) .............................................................. 20 Write Disable (04h) ......................................................................................................... 21 Read Status Register-1 (05h) and Read Status Register-2 (35h) .................................. 21 - 2 - Publication Release Date: October 31, 2014 Revision D1 W25Q40CL 9.1.9 Write Status Register (01h) ............................................................................................ 22 9.1.10 Read Data (03h) ........................................................................................................... 23 9.1.11 Fast Read (0Bh) ........................................................................................................... 24 9.1.12 Fast Read Dual Output (3Bh) ....................................................................................... 25 9.1.13 Fast Read Quad Output (6Bh) ...................................................................................... 26 9.1.14 Fast Read Dual I/O (BBh)............................................................................................. 27 9.1.15 Fast Read Quad I/O (EBh) ........................................................................................... 29 9.1.16 Set Burst with Wrap (77h) ............................................................................................ 31 9.1.17 Continuous Read Mode Bits (M7-0) ............................................................................. 32 9.1.18 Continuous Read Mode Reset (FFh or FFFFh) ............................................................ 32 9.1.19 Page Program (02h) ..................................................................................................... 33 9.1.20 Quad Input Page Program (32h) .................................................................................. 34 9.1.21 Sector Erase (20h) ....................................................................................................... 35 9.1.22 32KB Block Erase (52h) ............................................................................................... 36 9.1.23 64KB Block Erase (D8h)............................................................................................... 37 9.1.24 Chip Erase (C7h / 60h) ................................................................................................. 38 9.1.25 Erase / Program Suspend (75h) ................................................................................... 39 9.1.26 Erase / Program Resume (7Ah) ................................................................................... 40 9.1.27 Power-down (B9h) ........................................................................................................ 41 9.1.28 Release Power-down / Device ID (ABh) ....................................................................... 42 9.1.29 Read Manufacturer / Device ID (90h) ........................................................................... 44 9.1.30 Read Manufacturer / Device ID Dual I/O (92h) ............................................................. 45 9.1.31 Read Manufacturer / Device ID Quad I/O (94h) ........................................................... 46 9.1.32 Read Unique ID Number (4Bh) .................................................................................... 47 9.1.33 Read JEDEC ID (9Fh) .................................................................................................. 48 9.1.34 Read SFDP Register (5Ah) .......................................................................................... 49 9.1.35 Erase Security Registers (44h) ..................................................................................... 50 9.1.36 Program Security Registers (42h) ................................................................................ 51 9.1.37 Read Security Registers (48h) ..................................................................................... 52 10. 11. ELECTRICAL CHARACTERISTICS ......................................................................................... 53 10.1 Absolute Maximum Ratings ........................................................................................ 53 10.2 Operating Ranges ......................................................................................................... 53 10.3 Power-up Timing and Write Inhibit Threshold .............................................................. 54 10.4 DC Electrical Characteristics ........................................................................................ 55 10.5 AC Measurement Conditions ........................................................................................ 56 10.6 AC Electrical Characteristics ........................................................................................ 57 AC Electrical Characteristics (cont’d) ........................................................................................ 58 10.7 Serial Output Timing ..................................................................................................... 59 10.8 Serial Input Timing ........................................................................................................ 59 10.9 Hold Timing ................................................................................................................... 59 10.10 WP Timing ................................................................................................................... 59 PACKAGE SPECIFICATION .................................................................................................... 60 11.1 8-Pin SOIC8 150-mil (Package Code SN) .................................................................... 60 11.2 8-Pin SOIC 208-mil (Package Code SS) ...................................................................... 61 11.3 8-Pad USON 2x3-mm (Package Code UX) .................................................................. 62 - 3 - Publication Release Date: October 31, 2014 Revision D1 W25Q40CL 12. 11.4 Ordering Information ..................................................................................................... 63 11.5 Valid Part Numbers and Top Side Marking .................................................................. 64 REVISION HISTORY ................................................................................................................ 65 - 4 - Publication Release Date: October 31, 2014 Revision D1 W25Q40CL 1. GENERAL DESCRIPTION The W25Q40CL (4M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single 2.3V to 3.6V power supply with current consumption as low as 1mA active and 1µA for power-down. All devices are offered in space-saving packages. The W25Q40CL arrays are organized into 2048 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. The W25Q40CL have 128 erasable sectors, 16 erasable 32KB blocks and 8 erasable 64KB blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q40CL support the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protect, with top, bottom or complement array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. 2. FEATURES  Family of SpiFlash Memories – W25Q40CL: 4M-bit/512K-byte (524,288) – 256-byte per programmable page – Uniform 4KB Sectors, 32KB & 64KB Blocks  Software and Hardware Write Protection – Write-Protect all or portion of memory – Enable/Disable protection with /WP pin – Top or bottom array protection  SPI with Single / Dual Outputs / I/O  Flexible Architecture with 4KB sectors – Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Uniform Sector/Block Erase (4/32/64-kbytes) – Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold – Program one to 256 bytes < 1ms – Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3 – Erase/Program Suspend & Resume – More than 100,000 erase/write cycles  Data Transfer up to 416M-bits / second – More than 20-year data retention – Clock operation to 104MHz. – 208/416MHz equivalent Dual/Quad SPI  Low Power, Wide Temperature Range – Auto-increment Read capability. – Single 2.3 to 3.6V supply – 1mA active current,