W25R128FV
3V 128M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI & RPMC
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
Table of Contents
1.
GENERAL DESCRIPTIONS ............................................................................................................. 5
2.
FEATURES ....................................................................................................................................... 5
3.
PACKAGE TYPES AND PIN CONFIGURATIONS........................................................................... 6
4.
3.1
Pin Configuration SOIC / VSOP 208-mil .............................................................................. 6
3.2
Pad Configuration WSON 6x5-mm / 8x6-mm ...................................................................... 6
3.3
Pin Description SOIC / VSOP 208-mil, WSON 6x5-mm / 8x6-mm ...................................... 6
3.4
Pin Configuration SOIC 300-mil ........................................................................................... 7
3.5
Pin Description SOIC 300-mil ............................................................................................... 7
3.6
Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8
3.7
Ball Description TFBGA 8x6-mm ......................................................................................... 8
3.8
Pin Configuration PDIP 300-mil ............................................................................................ 9
3.9
Pin Description PDIP 300-mil ............................................................................................... 9
PIN DESCRIPTIONS ...................................................................................................................... 10
4.1
Chip Select (/CS) ................................................................................................................ 10
4.2
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ................................... 10
4.3
Serial Clock (CLK) .............................................................................................................. 10
4.4
Reset (/RESET) .................................................................................................................. 10
5.
BLOCK DIAGRAM .......................................................................................................................... 11
6.
FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12
6.1
7.
SPI Operations ................................................................................................................... 12
6.1.1
Standard SPI Instructions ..................................................................................................... 12
6.1.2
Dual SPI Instructions ............................................................................................................ 12
6.1.3
Quad SPI Instructions ........................................................................................................... 12
6.1.4
Software Reset & Hardware /RESET pin .............................................................................. 12
6.2
RPMC Operations............................................................................................................... 13
6.3
Write Protection .................................................................................................................. 14
STATUS AND CONFIGURATION REGISTERS ............................................................................ 15
7.1
Status Registers ................................................................................................................. 15
7.1.1
Erase/Write In Progress (BUSY) – Status Only .................................................................... 15
7.1.2
Write Enable Latch (WEL) – Status Only ............................................................................. 15
7.1.3
Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable ................................... 15
7.1.4
Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable .......................................... 16
7.1.5
Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable .......................................... 16
7.1.6
Complement Protect (CMP) – Volatile/Non-Volatile Writable ............................................... 16
7.1.7
Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable .............................. 16
7.1.8
Erase/Program Suspend Status (SUS) – Status Only .......................................................... 17
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W25R128FV
8.
7.1.9
Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable ............. 17
7.1.10
Quad Enable (QE) – Factory set, unchangeable ................................................................ 17
7.1.11
Write Protect Selection (WPS) – Volatile/Non-Volatile Writable ........................................ 18
7.1.12
Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable ............................. 18
7.1.13
Reserved Bits – Non Functional ......................................................................................... 18
7.1.14
W25R128FV Status Register Memory Protection (WPS = 0, CMP = 0) ............................ 19
7.1.15
W25R128FV Status Register Memory Protection (WPS = 0, CMP = 1) ............................ 20
7.1.16
W25R128FV Individual Block Memory Protection (WPS = 1) ............................................ 21
INSTRUCTIONS ............................................................................................................................. 22
8.1
8.2
Device ID and Instruction Set Tables ................................................................................. 22
8.1.1
Manufacturer and Device Identification ................................................................................ 22
8.1.2
Instruction Set Table 1-1 (Standard/Dual/Quad SPI Instructions) ........................................ 23
8.1.3
Instruction Set Table 1-2 (Standard/Dual/Quad SPI Instructions) ........................................ 24
8.1.4
Instruction Set Table 2-1 (RPMC Input Instruction, OP1) ..................................................... 26
8.1.5
Instruction Set Table 2-2 (RPMC Output Instruction, OP2) .................................................. 26
Instruction Descriptions ...................................................................................................... 27
8.2.1
Write Enable (06h) ............................................................................................................... 27
8.2.2
Write Enable for Volatile Status Register (50h) .................................................................... 27
8.2.3
Write Disable (04h) ............................................................................................................... 28
8.2.4
Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) .............. 28
8.2.5
Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) .............. 29
8.2.6
Read Data (03h) ................................................................................................................... 31
8.2.7
Fast Read (0Bh) ................................................................................................................... 32
8.2.8
Fast Read Dual Output (3Bh) ............................................................................................... 33
8.2.9
Fast Read Quad Output (6Bh) .............................................................................................. 34
8.2.10
Fast Read Dual I/O (BBh) ................................................................................................... 35
8.2.11
Fast Read Quad I/O (EBh) ................................................................................................. 36
8.2.12
Set Burst with Wrap (77h) .................................................................................................. 37
8.2.13
Page Program (02h) ........................................................................................................... 38
8.2.14
Quad Input Page Program (32h) ........................................................................................ 39
8.2.15
Sector Erase (20h) ............................................................................................................. 40
8.2.16
32KB Block Erase (52h) ..................................................................................................... 41
8.2.17
64KB Block Erase (D8h) ..................................................................................................... 42
8.2.18
Chip Erase (C7h / 60h) ....................................................................................................... 43
8.2.19
Erase / Program Suspend (75h) ......................................................................................... 44
8.2.20
Erase / Program Resume (7Ah) ......................................................................................... 45
8.2.21
Power-down (B9h) .............................................................................................................. 46
8.2.22
Release Power-down / Device ID (ABh) ............................................................................. 47
8.2.23
Read Manufacturer / Device ID (90h) ................................................................................. 48
8.2.24
Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 49
8.2.25
Read Manufacturer / Device ID Quad I/O (94h) ................................................................. 50
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
9.
10.
11.
8.2.26
Read Unique ID Number (4Bh)........................................................................................... 51
8.2.27
Read JEDEC ID (9Fh) ........................................................................................................ 52
8.2.28
Read SFDP Register (5Ah) ................................................................................................ 53
8.2.29
Erase Security Registers (44h) ........................................................................................... 57
8.2.30
Program Security Registers (42h) ...................................................................................... 58
8.2.31
Read Security Registers (48h) ........................................................................................... 59
8.2.32
Individual Block/Sector Lock (36h) ..................................................................................... 60
8.2.33
Individual Block/Sector Unlock (39h) .................................................................................. 61
8.2.34
Read Block/Sector Lock (3Dh) ........................................................................................... 62
8.2.35
Global Block/Sector Lock (7Eh) .......................................................................................... 63
8.2.36
Global Block/Sector Unlock (98h) ....................................................................................... 63
8.2.37
Enable Reset (66h) and Reset Device (99h) ...................................................................... 64
8.2.38
Write Root Key Register (9Bh + 00h) ................................................................................. 65
8.2.39
Update HMAC Key (9Bh + 01h).......................................................................................... 66
8.2.40
Increment Monotonic Counter (9Bh + 02h) ........................................................................ 67
8.2.41
Request Monotonic Counter (9Bh + 03h) ........................................................................... 68
8.2.42
Reserved RPMC Commands (9Bh + 04h~FFh) ................................................................. 68
8.2.43
Read RPMC Status / Data (96h) ........................................................................................ 69
ELECTRICAL CHARACTERISTICS ............................................................................................... 70
9.1
Absolute Maximum Ratings ................................................................................................ 70
9.2
Operating Ranges............................................................................................................... 70
9.3
Power-Up Power-Down Timing and Requirements ............................................................ 71
9.4
DC Electrical Characteristics .............................................................................................. 72
9.5
AC Measurement Conditions .............................................................................................. 73
9.6
AC Electrical Characteristics .............................................................................................. 74
9.7
AC Electrical Characteristics (cont’d) ................................................................................. 75
9.8
Serial Output Timing ........................................................................................................... 76
9.9
Serial Input Timing .............................................................................................................. 76
PACKAGE SPECIFICATIONS ........................................................................................................ 77
10.1
8-Pin SOIC 208-mil (Package Code S) .............................................................................. 77
10.2
8-Pin VSOP 208-mil (Package Code T) ............................................................................. 78
10.3
8-Pin PDIP 300-mil (Package Code A) ............................................................................... 79
10.4
8-Pad WSON 6x5-mm (Package Code P) ......................................................................... 80
10.5
8-Pad WSON 8x6-mm (Package Code E) ......................................................................... 81
10.6
16-Pin SOIC 300-mil (Package Code F) ............................................................................ 82
10.7
24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 ball array) ............................................ 83
10.8
24-Ball TFBGA 8x6-mm (Package Code C, 6x4 ball array) ............................................... 84
ORDERING INFORMATION .......................................................................................................... 85
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W25R128FV
11.1
12.
Valid Part Numbers and Top Side Marking ........................................................................ 86
REVISION HISTORY ...................................................................................................................... 87
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
1. GENERAL DESCRIPTIONS
The W25R128FV (128M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The W25 series offers flexibility and performance well beyond ordinary Serial
Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI
(XIP) and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with
current consumption as low as 4mA active. All devices are offered in space-saving packages.
The W25R128FV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock,
Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2, and I/O3. SPI clock frequencies of up to 104MHz are
supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x
4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can
outperform standard Asynchronous 8 and 16-bit Parallel Flash memories.
The device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64-bit Unique
Serial Number and three 256-bytes Security Registers.
The W25R series is also equipped with an enhanced security feature known as Replay Protection
Monotonic Counter (RPMC). Replay Protection provides a high level secured communication between the
flash device and the controller to reduce the system vulnerabilities to hardware attacks.
2. FEATURES
New Family of SpiFlash Memories
– W25R128FV: 128M-bit / 16M-byte
– Standard SPI: CLK, /CS, DI(IO0), DO(IO1)
– Dual SPI: CLK, /CS, IO0, IO1
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Software & Hardware Reset
Highest Performance Serial Flash
– 104MHz Single, Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/S continuous data transfer rate
– More than 100,000 erase/program cycles
– More than 20-year data retention
Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current
– -40°C to +85°C operating range
Flexible Architecture with 4KB sectors
– Uniform Sector/Block Erase (4K/32K/64K-Byte)
– Program 1 to 256 byte per programmable page
– Erase/Program Suspend & Resume
Advanced Security Features
– Software and Hardware Write-Protect
– Power Supply Lock-Down and OTP protection
– Top/Bottom, Complement array protection
– Individual Block/Sector array protection
– 64-Bit Unique ID for each device
– Discoverable Parameters (SFDP) Register
– 3X256-Bytes Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
Space Efficient Packaging
– 8-pin SOIC / VSOP 208-mil
– 8-pin PDIP 300-mil
– 8-pad WSON 6x5-mm / 8x6-mm
– 16-pin SOIC 300-mil (additional /RESET pin)
– 24-ball TFBGA 8x6-mm
– Contact Winbond for KGD and other options
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W25R128FV
3. PACKAGE TYPES AND PIN CONFIGURATIONS
3.1 Pin Configuration SOIC / VSOP 208-mil
Top View
/CS
1
8
VCC
IO1
2
7
IO3
IO2
3
6
CLK
GND
4
5
IO0
Figure 1a. W25R128FV Pin Assignments, 8-pin SOIC / VSOP 208-mil (Package Code S, T)
3.2 Pad Configuration WSON 6x5-mm / 8x6-mm
Top View
/CS
1
8
VCC
IO1
2
7
IO3
IO2
3
6
CLK
GND
4
5
IO0
Figure 1b. W25R128FV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code P, E)
3.3
Pin Description SOIC / VSOP 208-mil, WSON 6x5-mm / 8x6-mm
PIN NO.
PIN NAME
I/O
FUNCTION
1
/CS
I
2
IO1
I/O
Data Input Output 1(1)
3
IO2
I/O
Data Input Output 2(2)
4
GND
5
IO0
I/O
6
CLK
I
7
IO3
I/O
8
VCC
Chip Select Input
Ground
Data Input Output 0(1)
Serial Clock Input
Data Input Output 3(2)
Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions.
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
3.4
Pin Configuration SOIC 300-mil
Top View
IO3
1
16
CLK
VCC
2
15
IO0
/RESET
3
14
NC
NC
4
13
NC
NC
5
12
NC
NC
6
11
NC
/CS
7
10
GND
IO1
8
9
IO2
Figure 1c. W25R128FV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)
3.5
Pin Description SOIC 300-mil
PIN NO.
PIN NAME
I/O
I/O
FUNCTION
Data Input Output
3(2)
1
IO3
2
VCC
3
/RESET
4
N/C
No Connect
5
N/C
No Connect
6
N/C
No Connect
7
/CS
I
8
IO1
I/O
Data Input Output 1(1)
9
IO2
I/O
Data Input Output 2(2)
10
GND
Ground
11
N/C
No Connect
12
N/C
No Connect
13
N/C
No Connect
14
N/C
No Connect
15
IO0
I/O
16
CLK
I
Power Supply
I
Reset Input(3)
Chip Select Input
Data Input Output 0(1)
Serial Clock Input
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions.
3. The /RESET pin on SOIC-16 package is a dedicated hardware reset pin for SPI and RPMC operations. This pin can be treated
as “No Connect” in the system if the RESET function is not used.
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W25R128FV
3.6
Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Top View
Top View
A2
A3
A4
A5
A1
A2
A3
A4
NC
NC
NC
NC
NC
NC
NC
NC
B1
B2
B3
B4
B1
B2
B3
B4
B5
NC
CLK
GND
VCC
C4
NC
CLK
GND
VCC
NC
C1
C2
C3
C1
C2
C3
C4
C5
NC
/CS
NC
IO2
NC
/CS
NC
IO2
NC
D1
D2
D3
D4
D1
D2
D3
D4
D5
NC
IO1
IO0
IO3
NC
IO1
IO0
IO3
NC
E1
E2
E3
E4
NC
E1
E2
E3
E4
E5
NC
NC
NC
NC
NC
NC
NC
NC
F1
F2
F3
F4
NC
NC
NC
NC
Package Code B
Package Code C
Figure 1d. W25R128FV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B & C)
3.7
Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
I/O
FUNCTION
B2
CLK
I
B3
GND
Ground
B4
VCC
Power Supply
C2
/CS
I
C4
IO2
I/O
Data Input Output 2(2)
D2
IO1
I/O
Data Input Output 1(1)
D3
IO0
I/O
Data Input Output 0(1)
D4
IO3
I/O
Data Input Output 3(2)
Multiple
NC
Serial Clock Input
Chip Select Input
No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions.
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
3.8
Pin Configuration PDIP 300-mil
Top View
/CS
1
8
VCC
IO1
2
7
IO3
IO2
3
6
CLK
GND
4
5
IO0
Figure 1e. W25R128FV Pin Assignments, 8-pin PDIP (Package Code A)
3.9
Pin Description PDIP 300-mil
PIN NO.
PIN NAME
I/O
FUNCTION
1
/CS
I
2
IO1
I/O
Data Input Output 1(1)
3
IO2
I/O
Data Input Output 2(2)
4
GND
5
IO0
I/O
6
CLK
I
7
IO3
I/O
8
VCC
Chip Select Input
Ground
Data Input Output 0(1)
Serial Clock Input
Data Input Output 3(2)
Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions.
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W25R128FV
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
43a & 43b). If needed a pull-up resister on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25R128FV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
CLK.
4.3 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
4.4
Reset (/RESET)
The /RESET pin allows the device to be reset by the controller. On the 16-pin SOIC package, a dedicated
/RESET pin is provided to reset either SPI or RPMC operations for the entire device.
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
5. BLOCK DIAGRAM
RPMC Counters
SFDP Register
000000h
0000FFh
Security Register 1 - 3
003000h
002000h
001000h
0030FFh
0020FFh
0010FFh
Block Segmentation
xxFF00h
•
xxF000h
Sector 15 (4KB)
xxFFFFh
•
xxF0FFh
xxEF00h
•
xxE000h
Sector 14 (4KB)
xxEFFFh
•
xxE0FFh
xxDF00h
•
xxD000h
Sector 13 (4KB)
xxDFFFh
•
xxD0FFh
FFFF00h
•
Block 255 (64KB)
FF0000h
Sector 2 (4KB)
xx2FFFh
•
xx20FFh
xx1F00h
•
xx1000h
Sector 1 (4KB)
xx1FFFh
•
xx10FFh
xx0F00h
•
xx0000h
Sector 0 (4KB)
xx0FFFh
•
xx00FFh
Write Protect Logic and Row Decode
xx2F00h
•
xx2000h
80FF00h
•
Block 128 (64KB)
800000h
80FFFFh
•
8000FFh
7FFF00h
•
Block 127 (64KB)
7F0000h
7FFFFFh
•
7F00FFh
•
•
•
Write Control
Logic
Status
Register
40FF00h
•
400000h
Block 64 (64KB)
40FFFFh
•
4000FFh
3FFF00h
•
3F0000h
Block 63 (64KB)
3FFFFFh
•
3F00FFh
•
•
•
High Voltage
Generators
00FF00h
•
000000h
IO3
CLK
/CS
/RESET
SPI
Control Logic
&
RPMC
Security Logic
Page Address
Latch / Counter
Block 0 (64KB)
Beginning
Page Address
Ending
Page Address
Column Decode
And 256-Byte Page Buffer
Data
IO0
IO1
00FFFFh
•
0000FFh
Byte Address
Latch / Counter
Figure 2. W25R128FV Serial Flash Memory Block Diagram
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W25R128FV
•
•
•
•
•
•
IO2
FFFFFFh
•
FF00FFh
W25R128FV
6.
FUNCTIONAL DESCRIPTIONS
6.1 SPI Operations
6.1.1
Standard SPI Instructions
The W25R128FV is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.1.2
Dual SPI Instructions
The W25R128FV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the
device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are
ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speedcritical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins
become bidirectional I/O pins: IO0 and IO1.
6.1.3
Quad SPI Instructions
The W25R128FV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O
(E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of
ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and
random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus
(XIP).
6.1.4
Software Reset & Hardware /RESET pin
The W25R128FV can be reset to the initial power-on state by a software Reset sequence. This sequence
must include two consecutive commands: Enable Reset (66h) & Reset (99h). If the command sequence is
successfully accepted, the device will take approximately 30uS ( tRST) to reset. No command will be
accepted during the reset period.
For the SOIC-16 package, W25R128FV provides a dedicated hardware /RESET pin as illustrated in
Figure 1c. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the device to its
initial power-on state. Hardware /RESET pin has the highest priority among all the input signals. Drive
/RESET low for a minimum period of ~1us (tRESET*) will interrupt any on-going external/internal
operations, regardless the status of other SPI signals (/CS, CLK and IOs).
Note:
1. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us
minimum is recommended to ensure reliable operation.
2. There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 package. If the reset function is
not needed, this pin can be left floating in the system.
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
6.2
RPMC Operations
To prevent hardware vulnerability attack, Replay Protection provides a building block towards providing
Confidentiality and Integrity of read/write flash memory data. The W25R128FV is equipped with four 32-bit
Monotonic Counters and can be addressed individually by the 8-bit Counter_Address. These monotonic
counters are used by the SPI flash controllers to ensure the physical authenticity of the attached flash
devices.
RPMC operation is based on the HMAC-SHA-256 cryptographic algorithm. HMAC-SHA-256 is a type of
keyed hash algorithm that is constructed from the SHA-256 hash function and used as a Hash-based
Message Authentication Code (HMAC). The HMAC process mixes a secret key with the message data,
hashes the result with the hash function, mixes that hash value with the secret key again, and then applies
the hash function a second time. The output hash is 256 bits in length.
An HMAC can be used to determine whether a message sent over an insecure channel has been
tampered with, provided that the sender and receiver share a secret key. The sender computes the hash
value for the original data and sends both the original data and hash value as a single message. The
receiver recalculates the hash value on the received message and checks that the computed HMAC
matches the transmitted HMAC.
Any change to the data or the hash value results in a mismatch, because knowledge of the secret key is
required to change the message and reproduce the correct hash value. Therefore, if the original and
computed hash values match, the message is authenticated.
For detailed RPMC information, please refer to Intel’s RPMC specification on their web site. The web site
link is: http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=22646
- 13 -
W25R128FV
6.3
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25R128FV
provides several means to protect the data from inadvertent writes.
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Additional Individual Block/Sector Locks for array protection
Write Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Registers using Status Register*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25R128FV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of t PUW . This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at powerdown to prevent adverse command sequence. If needed a pull-up resistor on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP[2:0]) bits. These settings
allow a portion or the entire memory array to be configured as read only. See Status Register section for
further information. Additionally, the Power-down instruction offers an extra level of write protection as all
instructions are ignored except for the Release Power-down instruction.
The W25R128FV also provides another Write Protect method using the Individual Block Locks. Each
64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the
top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is
0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or
Program commands issued to the corresponding sector or block will be ignored. When the device is
powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from
Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector
or block.
The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When
WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of
the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
- 14 -
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
7.
STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for W25R128FV. The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the device
is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status,
Erase/Program Suspend status, output driver strength, power-up and current Address Mode. The Write
Status Register instruction can be used to configure the device write protection features, Quad SPI setting,
Security Register OTP locks, Hold/Reset functions, output driver strength and power-up Address Mode.
Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits
(SRP0, SRP1), the Write Enable instruction.
7.1
Status Registers
S7
S6
S5
S4
S3
S2
S1
S0
SRP0
SEC
TB
BP2
BP1
BP0
WEL
BUSY
Status Register Protect 0
(Volatile/Non-Volatile Writable)
Sector Protect Bit
(Volatile/Non-Volatile Writable)
Top/Bottom Protect Bit
(Volatile/Non-Volatile Writable)
Block Protect Bits
(Volatile/Non-Volatile Writable)
Write Enable Latch
(Status-Only)
Erase/Write In Progress
(Status-Only)
Figure 4a. Status Register-1
7.1.1
Erase/Write In Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW , tPP, tSE, tBE, and
tCE in AC Characteristics). When the program, erase or write status/security register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
7.1.2
Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase
Security Register and Program Security Register.
7.1.3
Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
- 15 -
W25R128FV
7.1.4
Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP0, SRP1 and WEL bits.
7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in the Status Register Memory Protection table. The default setting is SEC=0.
7.1.6
Complement Protect (CMP) – Volatile/Non-Volatile Writable
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For
instance, when CMP=0, a top 64KB block can be protected while the rest of the array is not; when
CMP=1, the top 64KB block will become unprotected while the rest of the array become read-only. Please
refer to the Status Register Memory Protection table for details. The default setting is CMP=0.
7.1.7
Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
Status
Register
SRP1
SRP0
Description
0
x
1
0
Power Supply
Lock-Down
Status Register is protected and cannot be written to again until
the next power-down, power-up cycle.(1)
1
1
One Time
Program(2)
Status Register is permanently protected and cannot be written
to.
The Status register can be written to after a Write Enable
instruction, WEL=1. [Factory Default]
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available upon special order. Please contact Winbond for details.
- 16 -
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
S15
S14
S13
S12
S11
S10
S9
S8
SUS
CMP
LB3
LB2
LB1
(R)
QE
SRP1
Suspend Status
(Status-Only)
Complement Protect
(Volatile/Non-Volatile Writable)
Security Register Lock Bits
(Volatile/Non-Volatile OTP Writable)
Reserved
Quad Enable
(Volatile/Non-Volatile Writable)
Status Register Protect 1
(Volatile/Non-Volatile Writable)
Figure 4b. Status Register-2
7.1.8
Erase/Program Suspend Status (SUS) – Status Only
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
7.1.9
Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
7.1.10
Quad Enable (QE) – Factory set, unchangeable
The Quad Enable (QE) bit is set to 1 by default in the factory, therefore the device supports Standard/Dual
SPI as well as Quad SPI after power on. This bit cannot be reset to 0.
- 17 -
W25R128FV
S23
(R)
S22
S21
DRV1 DRV0
S20
S19
S18
S17
S16
(R)
(R)
WPS
(R)
(R)
Reserved
Output Driver Strength
(Volatile/Non-Volatile Writable)
Reserved
Write Protect Selection
(Volatile/Non-Volatile Writable)
Reserved
Figure 4c. Status Register-3
7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will
use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When
WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The
default value for all Individual Block Lock bits is 1 upon device power on or after reset.
7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
0, 0
100%
0, 1
75%
1, 0
50%
1, 1
25% (default setting)
7.1.13 Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be
written as “0”, but there will not be any effects.
- 18 -
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
7.1.14
W25R128FV Status Register Memory Protection (WPS = 0, CMP = 0)
STATUS REGISTER(1)
W25R128FV (128M-BIT) MEMORY PROTECTION(3)
SEC
TB
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
X
X
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
252 thru 255
FC0000h – FFFFFFh
256KB
Upper 1/64
0
0
0
1
0
248 thru 255
F80000h – FFFFFFh
512KB
Upper 1/32
0
0
0
1
1
240 thru 255
F00000h – FFFFFFh
1MB
Upper 1/16
0
0
1
0
0
224 thru 255
E00000h – FFFFFFh
2MB
Upper 1/8
0
0
1
0
1
192 thru 255
C00000h – FFFFFFh
4MB
Upper 1/4
0
0
1
1
0
128 thru 255
800000h – FFFFFFh
8MB
Upper 1/2
0
1
0
0
1
0 thru 3
000000h – 03FFFFh
256KB
Lower 1/64
0
1
0
1
0
0 thru 7
000000h – 07FFFFh
512KB
Lower 1/32
0
1
0
1
1
0 thru 15
000000h – 0FFFFFh
1MB
Lower 1/16
0
1
1
0
0
0 thru 31
000000h – 1FFFFFh
2MB
Lower 1/8
0
1
1
0
1
0 thru 63
000000h – 3FFFFFh
4MB
Lower 1/4
0
1
1
1
0
0 thru 127
000000h – 7FFFFFh
8MB
Lower 1/2
X
X
1
1
1
0 thru 255
000000h – FFFFFFh
16MB
ALL
1
0
0
0
1
255
FFF000h – FFFFFFh
4KB
U - 1/4096
1
0
0
1
0
255
FFE000h – FFFFFFh
8KB
U - 1/2048
1
0
0
1
1
255
FFC000h – FFFFFFh
16KB
U - 1/1024
1
0
1
0
X
255
FF8000h – FFFFFFh
32KB
U - 1/512
1
1
0
0
1
0
000000h – 000FFFh
4KB
L - 1/4096
1
1
0
1
0
0
000000h – 001FFFh
8KB
L - 1/2048
1
1
0
1
1
0
000000h – 003FFFh
16KB
L - 1/1024
1
1
1
0
X
0
000000h – 007FFFh
32KB
L - 1/512
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored.
- 19 -
W25R128FV
7.1.15
W25R128FV Status Register Memory Protection (WPS = 0, CMP = 1)
STATUS REGISTER(1)
W25R128FV (128M-BIT) MEMORY PROTECTION(3)
SEC
TB
BP2
BP1
BP0
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
X
X
0
0
0
0 thru 255
000000h - FFFFFFh
16MB
ALL
0
0
0
0
1
0 thru 251
000000h - FBFFFFh
16,128KB
Lower 63/64
0
0
0
1
0
0 thru 247
000000h – F7FFFFh
15,872KB
Lower 31/32
0
0
0
1
1
0 thru 239
000000h - EFFFFFh
15MB
Lower 15/16
0
0
1
0
0
0 thru 223
000000h - DFFFFFh
14MB
Lower 7/8
0
0
1
0
1
0 thru 191
000000h - BFFFFFh
12MB
Lower 3/4
0
0
1
1
0
0 thru 127
000000h - 7FFFFFh
8MB
Lower 1/2
0
1
0
0
1
4 thru 255
040000h - FFFFFFh
16,128KB
Upper 63/64
0
1
0
1
0
8 thru 255
080000h - FFFFFFh
15,872KB
Upper 31/32
0
1
0
1
1
16 thru 255
100000h - FFFFFFh
15MB
Upper 15/16
0
1
1
0
0
32 thru 255
200000h - FFFFFFh
14MB
Upper 7/8
0
1
1
0
1
64 thru 255
400000h - FFFFFFh
12MB
Upper 3/4
0
1
1
1
0
128 thru 255
800000h - FFFFFFh
8MB
Upper 1/2
X
X
1
1
1
NONE
NONE
NONE
NONE
1
0
0
0
1
0 thru 255
000000h – FFEFFFh
16,380KB
L - 4095/4096
1
0
0
1
0
0 thru 255
000000h – FFDFFFh
16,376KB
L - 2047/2048
1
0
0
1
1
0 thru 255
000000h – FFBFFFh
16,368KB
L - 1023/1024
1
0
1
0
X
0 thru 255
000000h – FF7FFFh
16,352KB
L - 511/512
1
1
0
0
1
0 thru 255
001000h – FFFFFFh
16,380KB
U - 4095/4096
1
1
0
1
0
0 thru 255
002000h – FFFFFFh
16,376KB
U - 2047/2048
1
1
0
1
1
0 thru 255
004000h – FFFFFFh
16,368KB
U -1023/1024
1
1
1
0
X
0 thru 255
008000h – FFFFFFh
16,352KB
U - 511/512
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored.
- 20 -
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
W25R128FV Individual Block Memory Protection (WPS = 1)
Block 255
(64KB)
7.1.16
Sector 15 (4KB)
Sector 14 (4KB)
Sector 1 (4KB)
Sector 0 (4KB)
Individual Block Locks:
32 Sectors (Top/Bottom)
254 Blocks
Block 254 (64KB)
Individual Block Lock:
36h + Address
Individual Block Unlock:
39h + Address
Read Block Lock:
3Dh + Address
Global Block Lock:
7Eh
Block 0
(64KB)
Block 1 (64KB)
Global Block Unlock:
98h
Sector 15 (4KB)
Sector 14 (4KB)
Sector 1 (4KB)
Sector 0 (4KB)
Figure 5. Individual Block/Sector Locks
Notes:
1. Individual Block/Sector protection is only valid when WPS=1.
2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.
- 21 -
W25R128FV
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25R128FV consists of 47 basic instructions that are
fully controlled through the SPI bus (see Instruction Set Table1-1,2). Instructions are initiated with the
falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction
code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 6
through 42. All read instructions can be completed after any clocked bit. However, all instructions that
Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent
writes. Additionally, while the memory is being programmed or erased, or when the Status Register is
being written, all instructions except for Read Status Register will be ignored until the program or erase
cycle has completed.
8.1
8.1.1
Device ID and Instruction Set Tables
Manufacturer and Device Identification
MANUFACTURER ID
(MF7 - MF0)
Winbond Serial Flash
EFh
Device ID
(ID7 - ID0)
(ID15 - ID0)
Instruction
ABh, 90h, 92h, 94h
9Fh
W25R128FV
17h
4018h
- 22 -
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
Instruction Set Table 1-1 (Standard/Dual/Quad SPI Instructions)(1)
8.1.2
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Clock Number
(0 – 7)
(8 – 15)
(16 – 23)
(24 – 31)
(32 – 39)
(40 – 47)
(48 – 55)
Write Enable
06h
Volatile SR Write Enable
50h
Write Disable
04h
05h
(S7-S0)(2)
Write Status Register-1
01h
(S7-S0)(4)
Read Status Register-2
35h
(S15-S8)(2)
Write Status Register-2
31h
(S15-S8)
Read Status Register-3
15h
(S23-S16)(2)
11h
(S23-S16)
Read Status Register-1
(4)
Write Status Register-3
Chip Erase
C7h/60h
Erase / Program Suspend
75h
Erase / Program Resume
7Ah
Power-down
B9h
Release Power-down / ID
ABh
Dummy
Dummy
Dummy
(ID7-ID0)(2)
Manufacturer/Device ID
90h
Dummy
Dummy
00h
(MF7-MF0)
JEDEC ID
9Fh
(MF7-MF0)
(ID15-ID8)
(ID7-ID0)
Global Block Lock
7Eh
Global Block Unlock
98h
Enable Reset
66h
Reset Device
99h
- 23 -
(ID7-ID0)
W25R128FV
Instruction Set Table 1-2 (Standard/Dual/Quad SPI Instructions)(1)
8.1.3
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Clock Number
(0 – 7)
(8 – 15)
(16 – 23)
(24 – 31)
(32 – 39)
(40 – 47)
(UID63-UID0)
Read Unique ID
4Bh
Dummy
Dummy
Dummy
Dummy
Page Program
02h
A23-A16
A15-A8
A7-A0
D7-D0
D7-D0(3)
D7-D0, …
D7-D0, …(3)
(9)
Quad Page Program
32h
A23-A16
A15-A8
A7-A0
Sector Erase (4KB)
20h
A23-A16
A15-A8
A7-A0
Block Erase (32KB)
52h
A23-A16
A15-A8
A7-A0
Block Erase (64KB)
D8h
A23-A16
A15-A8
A7-A0
Read Data
03h
A23-A16
A15-A8
A7-A0
(D7-D0)
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Fast Read Dual Output
3Bh
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0, …)(7)
Fast Read Quad Output
6Bh
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0, …)(9)
Read SFDP Register
5Ah
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Erase Security Register(5)
44h
A23-A16
A15-A8
A7-A0
Program Security Register(5)
42h
A23-A16
A15-A8
A7-A0
D7-D0
D7-D0(3)
Read Security Register(5)
48h
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Individual Block Lock
36h
A23-A16
A15-A8
A7-A0
Individual Block Unlock
39h
A23-A16
A15-A8
A7-A0
Read Block Lock
3Dh
A23-A16
A15-A8
A7-A0
(L7-L0)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Clock Number
(0 – 7)
(8 – 11)
(12 – 15)
(16 – 19)
(20 – 23)
(24 – 27)
(28 – 31)
BBh
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Fast Read Dual I/O
Mftr./Device ID Dual I/O
92h
A23-A16
A15-A8
A7-A0
Dummy
(MF7-MF0)
(ID7-ID0)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Clock Number
(0 – 7)
(8, 9)
(10, 11)
(12, 13)
(14, 15)
(16, 17)
(18, 19)
(20, 21)
(22, 23)
Set Burst with Wrap
77h
Dummy
Dummy
Dummy
W8-W0
Fast Read Quad I/O
EBh
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
Dummy
(D7-D0)
(D7-D0)
Mftr./Device ID Quad I/O
94h
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
Dummy
(MF7-MF0)
(ID7-ID0)
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
Notes (For Instruction Set Table 1-1/2):
Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data
output from the device on either 1, 2 or 4 IO pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security
Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the
addressing will wrap to the beginning of the page and overwrite previously sent data.
4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5.
5. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format:
Set Burst with Wrap input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO0 = x, x, x, x, x, x, W4, x
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO1 = x, x, x, x, x, x, W5, x
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO2 = x, x, x, x, x, x, W6, x
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
IO3 = x, x, x, x, x, x, x, x
9. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
1.
- 25 -
W25R128FV
8.1.4
Instruction Set Table 2-1 (RPMC Input Instruction, OP1)(1)
INSTRUCTION
NAME
BYTE 0
BYTE 1
(CmdType)
BYTE 2
BYTE 3(2)
Write
Root Key Register
9Bh
00h
CounterAddr[7:0]
Reserved[7:0]
Byte 4 - 35
RootKey[255:0]
Byte 36 - 63
TruncatedSign[223:0]
Update
HMAC Key Register
9Bh
01h
CounterAddr[7:0]
Reserved[7:0]
Byte 4 - 7
KeyData[31:0]
Byte 8 - 39
Signature[255:0]
Increment
Monotonic Counter
9Bh
02h
CounterAddr[7:0]
Reserved[7:0]
Byte 4 - 7
CounterData[31:0]
Byte 8 - 39
Signature[255:0]
Request
Monotonic Counter
9Bh
03h
CounterAddr[7:0]
Reserved[7:0]
Byte 4 - 15
Tag[95:0]
Byte 16 - 47
Signature[255:0]
Reserved Commands
9Bh
04h ~ FFh
8.1.5
Reserved
Instruction Set Table 2-2 (RPMC Output Instruction, OP2)(1)
INSTRUCTION NAME
Read RPMC
Status / Data(3)(4)
BYTE 0
BYTE 1
BYTE 2
BYTE 3 - 14
BYTE 15 - 18
BYTE 19 - 50
96h
dummy
(RPMC Status[7:0])
(Tag[95:0])
(CounterData[31:0])
(Signature[255:0])
Notes (For Instruction Set Table 2-1/2):
1.
2.
3.
4.
All RPMC instructions are in Standard SPI format. Each Input/Output Byte requires 8 clocks.
The Reserved[7:0] field for RPMC OP1 must be all 0s (00000000’b).
The controller may terminate the Read RPMC Status/Data instruction at any time without going through the
entire data output sequence.
When BUSY=1, from Byte-3 and beyond, the device will output the RPMC_Status[7:0] value continuously
until /CS terminates the instruction. The device will not output Tag, CounterData & Signature fields when
BUSY=1. Once BUSY becomes 0, another OP2 command must be issued to read out the correct Tag,
CounterData & Signature fields.
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
8.2
8.2.1
Instruction Descriptions
Write Enable (06h)
The Write Enable instruction (Figure 6) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write
Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI)
pin on the rising edge of CLK, and then driving /CS high.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction (06h)
DI
(IO0)
High Impedance
DO
(IO1)
Figure 6. Write Enable Instruction
8.2.2
Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register nonvolatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable
for Volatile Status Register instruction (Figure 7) will not set the Write Enable Latch (WEL) bit, it is only
valid for the Write Status Register instruction to change the volatile Status Register bit values.
/CS
Mode 3
CLK
0
1
2
3
4
Mode 0
5
6
7
Mode 3
Mode 0
Instruction (50h)
DI
(IO0)
DO
(IO1)
High Impedance
Figure 7. Write Enable for Volatile Status Register Instruction
- 27 -
W25R128FV
8.2.3
Write Disable (04h)
The Write Disable instruction (Figure 8) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction (04h)
DI
(IO0)
High Impedance
DO
(IO1)
Figure 8. Write Disable Instruction
8.2.4
Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for Status
Register-2 or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits
are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown
in Figure 9. Refer to section 7.1 for Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (05h/35h/15h)
DI
(IO0)
High Impedance
DO
(IO1)
*
= MSB
Status Register-1/2/3 out
7
6
5
4
3
2
1
Status Register-1/2/3 out
0
*
7
6
5
4
3
2
1
0
7
*
Figure 9. Read Status Register Instruction
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
8.2.5
Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status
Register bits include: SRP0, SEC, TB, BP[2:0] in Status Register-1; CMP, LB[3:1], QE, SRP1 in Status
Register-2; HOLD/RST, DRV1, DRV0, WPS & ADP in Status Register-3. All other Status Register bit
locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are nonvolatile OTP bits, once it is set to 1, it cannot be cleared to 0.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction
code “01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 10a & 10b.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
However, SRP1 and LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these
bits. Upon power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values
will be lost, and the non-volatile Status Register bit values will be restored.
During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction
may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status
Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the
Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.
During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high,
the Status Register bits will be refreshed to the new values within the time period of t SHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
Refer to section 7.1 for Status Register descriptions.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
Mode 0
Instruction
(01h/31h/11h)
Register-1/2/3 in
DI
(IO0)
7
6
5
4
*
High Impedance
DO
(IO1)
Mode 3
* = MSB
Figure 10a. Write Status Register-1/2/3 Instruction
- 29 -
3
2
1
0
W25R128FV
The W25R128FV is also backward compatible to Winbond’s previous generations of serial flash
memories, in which the Status Register-1&2 can be written using a single “Write Status Register-1 (01h)”
command. To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after
the sixteenth bit of data that is clocked in as shown in Figure 10b. If /CS is driven high after the eighth
clock, the Write Status Register-1 (01h) instruction will only program the Status Register-1, the Status
Register-2 will not be affected (Previous generations will clear CMP and QE bits).
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Mode 0
Instruction (01h)
DI
(IO0)
Mode 3
Status Register 1 in
7
6
5
4
3
*
2
Status Register 2 in
1
0
15
14
13
12
11
10
9
8
*
High Impedance
DO
(IO1)
* = MSB
Figure 10b. Write Status Register-1/2 Instruction
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
8.2.6
Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous
stream of data. This means that the entire memory can be accessed with a single instruction as long as
the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in Figure 11. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of f R
(see AC Electrical Characteristics).
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
Mode 0
Instruction (03h)
24-Bit Address
DI
(IO0)
23
22
21
3
2
1
0
*
Data Out 1
High Impedance
DO
(IO1)
7
*
* = MSB
Figure 11. Read Data Instruction
- 31 -
6
5
4
3
2
1
0
7
W25R128FV
8.2.7
Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in Figure 12. The dummy clocks allow the devices
internal circuits additional time for setting up the initial address. During the dummy clocks the data value
on the DO pin is a “don’t care”.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
Mode 0
Instruction (0Bh)
24-Bit Address
DI
(IO0)
23
22
21
42
43
3
2
1
0
45
46
47
48
*
High Impedance
DO
(IO1)
* = MSB
/CS
31
32
33
34
35
36
37
38
39
40
41
44
49
50
51
52
53
54
55
CLK
Dummy Clocks
DI
(IO0)
DO
(IO1)
0
High Impedance
Data Out 1
7
6
5
4
3
Data Out 2
2
1
*
0
7
6
5
4
3
2
1
0
7
*
Figure 12. Fast Read Instruction
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Publication Release Date: November 30, 2017
- Revision C
W25R128FV
8.2.8
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to
RAM upon power-up or for applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in Figure 13. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks is
“don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
Mode 0
Instruction (3Bh)
24-Bit Address
DI
(IO0)
23
22
21
42
43
3
2
1
0
45
46
47
48
*
High Impedance
DO
(IO1)
* = MSB
/CS
31
32
33
34
35
36
37
38
39
40
41
44
49
50
51
52
53
54
55
CLK
IO0 switches from
Input to Output
Dummy Clocks
DI
(IO0)
DO
(IO1)
0
6
High Impedance
7
*
4
2
0
6
5
3
1
7
Data Out 1
*
4
2
0
6
5
3
1
7
Data Out 2
Figure 13. Fast Read Dual Output Instruction
- 33 -
*
4
2
0
6
5
3
1
7
Data Out 3
*
4
2
0
6
5
3
1
7
Data Out 4
W25R128FV
8.2.9
Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status
Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast
Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address
as shown in Figure 14. The dummy clocks allow the device's internal circuits additional time for setting up
the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
Mode 0
Instruction (6Bh)
24-Bit Address
IO0
23
High Impedance
IO1
22
21
42
43
3
2
1
45
46
47
0
*
High Impedance
IO2
High Impedance
IO3
* = MSB
/CS
31
32
33
34
35
36
37
38
39
40
41
44
CLK
IO0 switches from
Input to Output
Dummy Clocks
IO0
IO1
IO2
IO3
0
High Impedance
High Impedance
High Impedance
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
Byte 1
Byte 2
Byte 3
Byte 4
Figure 14. Fast Read Quad Output Instruction
- 34 -
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
8.2.10 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (BBh)
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
DO
(IO1)
23
21
19
17
15
13
11
9
7
5
3
1
7
5
3
1
*
* = MSB
*
/CS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
CLK
IOs switch from
Input to Output
DI
(IO0)
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
DO
(IO1)
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
*
Byte 1
*
Byte 2
*
Byte 3
*
Byte 4
Figure 15. Fast Read Dual I/O Instruction
- 35 -
W25R128FV
8.2.11 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO 0, IO1, IO2 and IO3 and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (EBh)
A23-16
A15-8
A7-0
M7-0
Dummy
IOs switch from
Input to Output
Dummy
IO0
20
16
12
8
4
0
4
0
4
0
4
0
4
IO1
21
17
13
9
5
1
5
1
5
1
5
1
5
IO2
22
18
14
10
6
2
6
2
6
2
6
2
6
IO3
23
19
15
11
7
3
7
3
7
3
7
3
7
Byte 1
Byte 2
Byte 3
Figure 16. Fast Read Quad I/O Instruction
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can
either enable or disable the “Wrap Around” feature for the following EBh commands. When “W rap
Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the
ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. Refer to section 8.2.12 for detail descriptions.
- 36 -
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
8.2.12 Set Burst with Wrap (77h)
In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read
Quad I/O” instruction to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain
applications can benefit from this feature and improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The
instruction sequence is shown in Figure 17. Wrap bit W7 and the lower nibble W3-0 are not used.
W4 = 0
W6, W5
0
0
1
1
W4 =1 (DEFAULT)
Wrap Around
Wrap Length
Wrap Around
Wrap Length
Yes
Yes
Yes
Yes
8-byte
16-byte
32-byte
64-byte
No
No
No
No
N/A
N/A
N/A
N/A
0
1
0
1
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” instruction
will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around”
function and return to normal read operation, another Set Burst with Wrap instruction should be issued to
set W4 = 1. The default value of W4 upon power on or after a software/hardware reset is 1.
/CS
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
Mode 3
Mode 0
don't
care
Instruction (77h)
don't
care
don't
care
Wrap Bit
IO0
X
X
X
X
X
X
w4
X
IO1
X
X
X
X
X
X
w5
X
IO2
X
X
X
X
X
X
w6
X
IO3
X
X
X
X
X
X
X
X
Figure 17. Set Burst with Wrap Instruction
- 37 -
W25R128FV
8.2.13
Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by
driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and
at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction
while data is being sent to the device. The Page Program instruction sequence is shown in Figure 18.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining
page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a
partial page) can be programmed without having any effect on other bytes within the same page. One
condition to perform a partial page program is that the number of clocks cannot exceed the remaining
page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the
page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register
is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
Mode 0
2
1
0
6
5
4
3
2
1
0
2079
3
2078
21
2077
22
*
2076
23
Data Byte 1
2075
24-Bit Address
2074
Instruction (02h)
DI
(IO0)
2073
CLK
7
*
* = MSB
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
2072
/CS
CLK
Mode 0
Data Byte 2
DI
(IO0)
Mode 3
0
7
*
6
5
4
3
Data Byte 3
2
1
0
7
6
5
4
3
Data Byte 256
2
1
0
*
7
6
5
4
3
2
1
0
*
Figure 18. Page Program Instruction
- 38 -
Publication Release Date: November 30, 2017
- Revision C
W25R128FV
8.2.14
Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can
improve performance for PROM Programmer and applications that have slow clock speeds
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