W27C4096P-15

Preliminary W27C4096 256K × 16 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27C4096 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 262144 × 16 bits that operates on a single 5 volt power supply. The W27C4096 provides an electrical chip erase function. FEATURES • High speed access time: • • • • 120/150 nS (max.) Read operating current: 30 mA (max.) Erase/Programming operating current 30 mA (max.) Standby current: 100 µA (max.) Single 5V power supply • +14V erase/+12V programming voltage • Fully static operation • All inputs and outputs directly TTL/CMOS compatible • Three-state outputs • Available packages: 40-pin 600 mil DIP, TSOP and 44-pin PLCC PIN CONFIGURATIONS VPP CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 GND Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 BLOCK DIAGRAM VDD A17 A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 Q0 CE OE CONTROL OUTPUT BUFFER . . Q15 40-pin DIP A0 . . A17 DECODER CORE ARRAY Q 1 3 6 Q12 Q11 Q10 Q9 Q8 GND NC Q7 Q6 Q5 Q4 7 8 9 10 11 12 13 14 15 16 17 18 Q 3 Q 1 4 5 Q 1 5 4 / C E V p p 2 N C 1 V C C A 1 7 A 1 6 42 A 1 5 41 A 1 4 40 39 38 37 36 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 VCC GND VPP 3 44 43 44-pin PLCC 35 34 33 32 31 30 29 PIN DESCRIPTION SYMBOL A0−A17 40 39 38 37 36 35 34 19 Q 2 20 21 Q 1 22 23 24 25 N C A 0 26 27 A 2 A 3 28 Q 0 / O E A 1 A 4 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program/Erase Supply Voltage Power Supply Ground No Connection A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC VPP CE Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-pin TSOP 33 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q0−Q15 CE OE VPP VCC GND NC -1- Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C4096 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE , if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C4096 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 = VPE (14V), A0 low, and all other address pins low and data input pins high. Erase Verify Mode After an erase operation, all of the words in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE high, and OE low. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), CE low, OE high, the address pins equal the desired address, and the input pins equal the desired inputs. Program Verify Mode All of the words in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each word is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE high, OE low and VCC = VCP (5V). Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , VPP = VPP/VPE (12V/14V), and VCC = 5V, erasing or programming of nontarget chips is inhibited, so that except for the CE and VPP, and VCC, the W27C4096 may have common inputs. -2- Preliminary W27C4096 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE high , VPP = 5V, and VCC = 5V. In standby mode, all outputs are in a high impedance state, independent of OE . Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C4096 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE . Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES (VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X = VIH or VIL) MODE CE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Erase Erase Verify Erase Inhibit Product Identifier-manufacturer Product Identifier-device VIL VIL VIH VCC ±0.3V VIL VIH VIH VIL VIH VIH VIL VIL OE VIL VIH X X VIH VIL X VIH VIL X VIL VIL A0 X X X X X X X VIL X X VIL VIH PINS A9 X X X X X X X VPE X X VHH VHH VCC VCC VCC VCC VCC VCP VCP VCP VCE VCE VCE VCC VCC VPP VCC VCC VCC VCC VPP VPP VPP VPE VPE VPE VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z DIH DOUT High Z 00DA (Hex) 000D (Hex) -3- Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Ambient Temperature with Power Applied Storage Temperature Voltage on all pins with Respect to Ground Except VPP, A9 and VCC pins Voltage on VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground Voltage on VCC Pin with Respect to Ground RATING -55 to +125 -65 to +125 -0.5 to VCC +0.5 -0.5 to +14.5 -0.5 to +14.5 -0.5 to +7 UNIT °C °C V V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (TA = 25° C ±5° C, VCC = 5.0V ± 5%, VHH = 14V) PARAMETER SYM. CONDITIONS MIN. LIMITS TYP. 14 14 5.0 MAX. 10 30 30 0.8 5.5 0.45 14.25 14.25 5.5 UNIT µA mA mA V V V V V V Input Load Current VCC Erase Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Erase Voltage VPP Erase Voltage VCC Supply Voltage (Erase) ILI ICP IPP VIL VIH VOL VOH VID VPE VCE VIN = VIL or VIH CE = VIL CE = VIL IOL = 2.1 mA IOH = -0.4 mA - -10 -0.3 2.4 2.4 13.75 13.75 4.5 Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. CAPACITANCE (VCC = 5V, TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT CONDITIONS VIN = 0V VOUT = 0V MAX. 6 12 UNIT pF pF -4- Preliminary W27C4096 AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0.45V to 2.4V 10 nS 0.8V/2.0V CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA CONDITIONS AC Test Load and Waveform +1.3V (IN914) 3.3K ohm DOUT 100 pF (Including Jig and Scope) Input Test Points 2.4V 0.45V 2.0V 0.8V Output Test Points 2.0V 0.8V -5- Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 READ OPERATION DC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 50° C) PARAMETER SYM. CONDITIONS MIN. LIMITS TYP. 5 MAX. 5 10 1.0 100 30 10 0.8 VCC +0.5 0.4 VCC UNIT µA µA mA µA mA µA V V V V V Input Load Current Output Leakage Current VCC Standby Current ILI ILO ISB ISB1 VIN = 0V to VCC VOUT = 0V to VCC CE = VIH CE = VCC ±0.2V CE = VIL IOUT = 0 mA, f = 5 MHz VPP = VCC IOL = 2.1 mA IOH = -0.4 mA - -5 -10 -0.3 2.2 2.4 VCC -0.7 VCC Operating Current VPP Operating Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Operating Voltage ICC IPP VIL VIH VOL VOH VPP READ OPERATION AC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 50° C) PARAMETER SYM. W27C4096-12 MIN. MAX. 120 120 50 30 - W27C4096-15 MIN. 150 0 MAX. 150 150 70 30 - UNIT Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time OE High to High-Z Output Output Hold from Address Change TRC TCE TACC TOE TDF TOH 120 0 nS nS nS nS nS nS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -6- Preliminary W27C4096 DC PROGRAMMING CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER Input Load Current VCC Program Current VPP Program Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Silicon I.D. Voltage VPP Program Voltage VCC Supply Voltage (Program) SYM. ILI ICP IPP VIL VIH VOL VOH VID VPP VCP CONDITIONS MIN. VIN = VIL or VIH CE = VIL CE = VIL IOL = 2.1 mA IOH = -0.4 mA -10 -0.3 2.4 2.4 11.5 11.75 4.5 LIMITS TYP. 12.0 12.0 5.0 MAX. 10 30 30 0.8 5.5 0.45 12.5 12.25 5.5 UNIT µA mA mA V V V V V V V AC PROGRAMMING/ERASE CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER VPP Setup Time Address Setup Time Data Setup Time CE Program Pulse Width CE Erase Pulse Width Data Hold Time OE Setup Time Data Valid from OE OE High to Output High Z Address Hold Time Address Hold Time after CE High (Erase) SYM. MIN. TVPS TAS TDS TPWP TPWE TDH TOES TOEV TDFP TAH TAHC 2.0 2.0 2.0 95 95 2.0 2.0 0 0 2.0 LIMITS TYP. 100 100 MAX. 105 105 150 130 - UNIT µS µS µS µS mS µS µS nS nS µS µS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -7- Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 TIMING WAVEFORMS AC Read Waveform VIH Address VIL VIH CE VIL Address Valid TCE VIH OE VIL T ACC Outputs High Z Valid Output High Z TOE TOH TDF Erase Waveform Read Manufacturer Read Device Chip Erase A9 = 14.0V Erase Verify Blank Check Read Verify SID SID A9 = 12.0V A0= VIH Others = V IL A0 = VIL Others = VIL VIL TACC 00DA VIH Address Others = V IL Address Stable TAS TARC Data All One TDS TAHC TDFP DOUT TAH 5V TVPS DOUT Address Stable Address Stable TACC DOUT TACC Data 000D 14.0V 5.0V VPP VIH CE VIL TOE VIH OE VIL TOEV TOE TPWE TOES TOE TCE -8- Preliminary W27C4096 Timing Waveforms, continued Programming Waveform Program VIH Address VIL TAS Address Stable Program Verify Address Stable TDFP Read Verify Address Valid TACC DOUT DOUT Data Data In Stable DOUT T DS 12.0V VPP 5.0V VIH CE VIL VIH OE VIL TPWP TDH TAH 5V TVPS TOE TOES TOEV -9- Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 SMART PROGRAMMING ALGORITHM Start Address = First Location Vcc = 5V Vpp = 12V X=0 Program One 100 µS Pulse Increment X Yes X = 25? No Fail Verify One Word Pass Increment Address No Last Address? Yes Vcc = 5V Vpp = 5V Verify One Word Pass Fail Compare All Words to Original Data Pass Pass Device Fail Fail Device - 10 - Preliminary W27C4096 SMART ERASE ALGORITHM Start X=0 Vcc = 5V Vpp = 14V A9 = 14V; A0 = V IL Chip Erase 100 mS Pulse Address = First Location Increment X No Erase Verify Pass Increment Address No Last Address? Yes Vcc = 5V Vpp = 5V Fail X = 20? Yes Compare All Words to FFFF (HEX) Pass Pass Device Fail Fail Device - 11 - Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 ORDERING INFORMATION PART NO. ACCESS TIME (nS) 120 120 120 150 150 150 POWER SUPPLY CURRENT MAX. (mA) 30 30 30 30 30 30 STANDBY VCC CURRENT MAX. (µ A) 100 100 100 100 100 100 PACKAGE W27C4096-12 W27C4096T-12 W27C4096P-12 W27C4096-15 W27C4096T-15 W27C4096P-15 Notes: 600 mil DIP 40-pin TSOP 44-pin PLCC 600 mil DIP 40-pin TSOP 44-pin PLCC 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 12 - Preliminary W27C4096 PACKAGE DIMENSIONS 40-pin PDIP Dimension in inches Dimension in mm Symbol Min. Nom. Max. 0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15 0.670 0.090 Min. Nom. Max. 5.33 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 52.20 14.99 13.72 2.29 3.05 0 16.00 16.51 15.24 13.84 2.54 3.30 4.06 0.56 1.37 0.36 52.58 15.49 13.97 2.79 3.56 15 17.02 2.29 D 40 21 A A1 A2 B B1 c D E E1 e1 L a E1 eA S 1 S 20 E c A A2 L B B1 e1 A1 Base Plane Seating Plane eA Notes: 1. Dimensions D Max & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. a 40-pin TSOP HD Dimension in Inches Dimension in mm Min. Nom. Max. 1.20 0.05 0.95 0.17 0.10 1.00 0.22 0.15 18.4 10 20.0 0.50 0.50 0.60 0.8 0.004 3 5 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.20 18.5 10.10 20.2 D Symbol Min. Nom. Max. 0.047 c 1 A A1 A2 b c D E HD e L L1 Y 0.002 0.037 0.039 0.006 0.041 M e E 0.007 0.009 0.011 0.004 0.006 0.008 0.72 0.10(0.004) b 0.724 0.728 18.3 9.90 19.8 0.390 0.394 0.398 0.780 0.787 0.795 0.020 0.020 0.024 0.028 0.031 0.000 0 A θ L L1 A2 A1 Y θ Controlling dimension: Millimeters - 13 - Publication Release Date: March 1999 Revision A1 Preliminary W27C4096 Package Dimensions, continued 44-pin PLCC HD D 6 1 44 40 Dimension in inches Dimension in mm Symbol 7 39 Min. Nom. Max. 0.185 0.020 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 Min. 0.51 3.68 0.66 0.41 0.20 Nom. Max. 4.70 3.81 0.71 0.46 0.25 3.94 0.81 0.56 0.36 16.71 16.71 16.00 16.00 E HE GE 17 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Notes: 0.648 0.653 0.658 16.46 16.59 0.648 0.653 0.658 16.46 16.59 0.050 BSC 1.27 0.590 0.610 0.630 14.99 15.49 0.590 0.610 0.630 14.99 15.49 0.680 0.690 0.700 17.27 0.680 0.690 0.700 17.27 0.090 0.100 0.110 0.004 2.29 BSC 17.53 17.78 17.53 17.78 2.54 2.79 0.10 L A2 A θ Seating Plane e GD b b1 A1 y 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. - 14 - Preliminary W27C4096 VERSION HISTORY VERSION A1 DATE Mar. 1999 PAGE Initial Issued DESCRIPTION Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 15 - Publication Release Date: March 1999 Revision A1