W27C512P-70

W27C512 64K × 8 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27C512 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65536 × 8 bits that operates on a single 5 volt power supply. The W27C512 provides an electrical chip erase function. FEATURES • High speed access time: • • • • 45/70/90/120 nS (max.) Read operating current: 30 mA (max.) Erase/Programming operating current 30 mA (max.) Standby current: 1 mA (max.) Single 5V power supply • +14V erase/+12V programming voltage • Fully static operation • All inputs and outputs directly TTL/CMOS compatible • Three-state outputs • Available packages: 28-pin 600 mil DIP, 330 mil 32-pin PLCC PIN CONFIGURATIONS BLOCK DIAGRAM CE OE/VPP OUTPUT BUFFER A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin DIP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A14 A13 A8 A9 A11 OE/Vpp A10 CE Q7 Q6 Q5 Q4 Q3 CONTROL Q0 . . Q7 A0 . DECODER CORE ARRAY . A15 VCC GND AA VAA A1 1NC11 72 5CC43 43213 2 5 6 7 8 32-pin 9 PLCC 10 11 12 1 1 1 1 1 13 4 5 6 7 8 33 1 0 29 28 27 26 25 24 23 1 2 22 9 0 21 PIN DESCRIPTION SYMBOL A8 A9 A11 NC OE/Vpp A10 CE Q7 Q6 DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable, Program/Erase Supply Voltage Power Supply Ground No Connection A6 A5 A4 A3 A2 A1 A0 NC Q0 A0−A15 Q0−Q7 CE OE /VPP Q QGN QQQ 1 2NC 34 5 D VCC GND NC -1- Publication Release Date: November 1999 Revision A4 W27C512 FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C512 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE /VPP controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE /VPP, if T ACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C512 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when OE /VPP is raised to VPE (14V), VCC = VCE (5V), A9 = VPE (14V), A0 low, and all other address pins low and data input pins high. Pulsing CE low starts the erase operation. Erase Verify Mode After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if VCC = VCE (3.75V), CE low, and OE /VPP low. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when OE /VPP is raised to VPP (12V), VCC = VCP (5V), the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation. Program Verify Mode All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if OE /VPP low and CE low. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the CE and OE /VPP pins, the W27C512 may have common inputs. -2- W27C512 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE /VPP. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C512 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations An EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE . Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES (VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL) MODE CE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Erase Erase Verify Erase Inhibit Product Identifier-manufacturer Product Identifier-device VIL VIL VIH VCC ±0.3V VIL VIL VIH VIL VIL VIH VIL VIL OE /VPP VIL VIH X X VPP VIL VPP VPE VIL VPE VIL VIL PINS A0 X X X X X X X VIL X X VIL VIH A9 X X X X X X X VPE X X VHH VHH VCC VCC VCC VCC VCC VCP VCC VCP VCE 3.75 VCE VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z DIH DOUT High Z DA (Hex) 08 (Hex) -3- Publication Release Date: November 1999 Revision A4 W27C512 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Operation Temperature Storage Temperature Voltage on all Pins with Respect to Ground Except OE /VPP, A9 and VCC Pins Voltage on OE /VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground Voltage VCC Pin with Respect to Ground RATING 0 to +70 -65 to +125 -0.5 to VCC +0.5 -0.5 to +14.5 -0.5 to +14.5 -0.5 to +7 UNIT °C °C V V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (TA = 25° C ±5° C, VCC = 5.0V ±5%) PARAMETER SYM. CONDITIONS MIN. LIMITS TYP. 14 14 5.0 3.75 MAX. 10 30 30 0.8 5.5 0.45 14.25 14.25 5.25 4.0 UNIT µA mA mA V V V V V V V Input Load Current VCC Erase Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Erase Voltage VPP Erase Voltage VCC Supply Voltage (Erase) VCC Supply Voltage (Erase Verify) ILI ICP IPP VIL VIH VOL VOH VID VPE VCE VCE VIN = VIL or VIH CE = VIL, OE /VPP = VPE CE = VIL, OE /VPP = VPE IOL = 2.1 mA IOH = -0.4 mA - -10 -0.3 2.4 2.4 13.75 13.75 4.75 3.5 Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -4- W27C512 CAPACITANCE (VCC = 5V, TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT CONDITIONS VIN = 0V VOUT = 0V MAX. 6 12 UNIT pF pF AC CHARACTERISTICS AC Test Conditions PARAMETER 45/70 nS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0 to 3.0V 5 nS 1.5V/1.5V CL = 30 pF, IOH/IOL = -0.4 mA/2.1 mA 10 nS 0.8V/2.0V CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA CONDITIONS 90/120 nS 0.45V to 2.4V AC Test Load and Waveforms +1.3V (IN914) 3.3K ohm DOUT 100 pF for 90/120 nS (Including Jig and Scope) 30 pF for 45/70 nS (Including Jig and Scope) Input Test Points 2.4V Output Test Points 2.0V 0.8V 2.0V 0.8V For 90/120 nS 0.45V Input Test Point 3.0V Output Test Point 1.5V 1.5V For 45/70 nS 0V -5- Publication Release Date: November 1999 Revision A4 W27C512 READ OPERATION DC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 70° C) PARAMETER Input Load Current Output Leakage Current Standby VCC Current (TTL input) Standby VCC Current (CMOS input) VCC Operating Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage SYM. ILI ILO ISB ISB1 ICC VIL VIH VOL VOH CONDITIONS MIN. VIN = 0V to VCC VOUT = 0V to VCC CE = VIH CE = VCC ±0.3V CE = VIL IOUT = 0 mA, f = 5 MHz IOL = 2.1 mA IOH = -0.4 mA -5 -10 -0.3 2.2 2.4 LIMITS TYP. 5 - UNIT MAX. 5 10 1.0 100 30 0.8 VCC +0.5 0.45 µA µA mA µA mA V V V V READ OPERATION AC CHARACTERISTICS (VCC = 5.0V ±5%, TA = 0 to 70° C) PARAMETER SYM. W27C512-45 MIN. MAX. 45 45 20 20 - W27C512-70 MIN. 70 0 MAX. 70 70 30 30 - W27C512-90 MIN. 90 0 MAX. 90 90 40 30 - W27C512-12 MIN. 120 0 MAX. 120 120 55 30 - UNIT Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time OE /VPP High to High-Z Output TRC TCE TACC TOE TDF TOH 45 0 nS nS nS nS nS nS Output Hold from Address Change Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. DC PROGRAMMING CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER Input Load Current VCC Program Current VPP Program Current SYM. ILI ICP IPP CONDITIONS MIN. VIN = VIL or VIH CE = VIL, OE /VPP = VPP CE = VIL, OE /VPP = VPP -10 - LIMITS TYP. MAX. 10 30 UNIT µA mA - - 30 mA -6- W27C512 DC Programming Characteristics, continued PARAMETER Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Silicon I.D. Voltage VPP Program Voltage VCC Supply Voltage (Program) SYM. VIL CONDITIONS MIN. IOL = 2.1 mA IOH = -0.4 mA -0.3 2.4 2.4 11.5 11.75 4.75 LIMITS TYP. 12.0 12.0 5.0 MAX. 0.8 5.5 0.45 12.5 12.25 5.25 UNIT V V V V V V V VIH VOL VOH VID VPP VCP AC PROGRAMMING/ERASE CHARACTERISTICS (VCC = 5.0V ±5%, TA = 25° C ±5° C) PARAMETER SYM. MIN. TPRT TDS TPWP TPWE TDH TOES TOEH TDV1 TDV2 TDFP TAS TAH TAHC TVS TVR TACV TOEV 50 2.0 95 95 2.0 2.0 2.0 25 25 0 2.0 0 2.0 2.0 2.0 - LIMITS TYP. 100 100 MAX. 105 105 1 1 130 250 150 UNIT nS µS µS mS µS µS µS µS µS nS µS µS µS µS µS nS nS OE /VPP Pulse Rise Time Data Setup Time CE Program Pulse Width CE Erase Pulse Width Data Hold Time OE /VPP Setup Time OE /VPP Hold Time Data Valid from CE Data Valid from Address Change CE High to Output High Z Address Setup Time Address Hold Time Address Hold Time after CE High (Erase) OE /VPP Valid after CE High OE /VPP Recovery Time Address Access Time During Erase Verify (VCC = 3.75V) Output Enable Access Time during Erase Verify (VCC = 3.75V) Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -7- Publication Release Date: November 1999 Revision A4 W27C512 TIMING WAVEFORMS AC Read Waveform V IH Address V IL V IH CE V IL V IH OE/Vpp V IL High Z Outputs TACC TOE TOH Valid Output High Z TCE TDF Address Valid Erase Waveform Read Company SID A9 = 12.0V Others = VIL Read Device SID Chip Erase A9 = 14.0V Erase Verify Blank Check Read Verify Address V IH V IL A0 = VI TACC L A0 = VIH Others = VIL Others = VIL Address Valid Address Valid Address Valid Address Valid TACC T AS T AHC TACV =250 nS D OUT T ACV =250 nS D OUT T ACC D OUT Data 5V DA 08 TDS Data All One T DH Vcc T VCS 3.75V 14.0V TOE V IH TOE TOES T OEV = 150 nS V IH TOEH TCE T PRT TVS Always = VIL V IH T OE OE/Vpp V IL V IH CE VIL TPWE TVR -8- W27C512 Timing Waveforms, continued Programming Waveform Program Program Verify Read Verify V IH Address V IL Address Stable T AH Address Stable TAS Data In Stable T DH TDS Address Stable TAH Address Valid TOH TDFP Address Valid T AS V IH Data V IL Data In Stable Data Out TDH TACC TDV1 TDV2 Data Out T OH TDS 12.0V OE/Vpp V IH TOES TPRT T PWP TOEH V IL V IL TVR T OE CE V IH V IL V IL CE should not be toggled during program verify period TCE -9- Publication Release Date: November 1999 Revision A4 W27C512 SMART PROGRAMMING ALGORITHM 1 Start Address = First Location Vcc = 5.0V OE/Vpp = 12V Program One 100 µS Pulse Increment Address No Last Address? Yes Address = First Location Increment Address No Last Address? Pass X=0 Verify Byte Fail Increment X Program One 100 µS Pulse Yes No X = 25 ? Vcc = 5.0V OE/Vpp = VIL Yes Compare All Bytes to Original Data Pass Device Passed Fail Device Failed - 10 - W27C512 SMART PROGRAMMING ALGORITHM 2 Start Address = First Location Vcc = 5.0V X=0 Program One 100 µS Pulse OE/VPP = 12V Increment X Yes X = 25? No Fail Verify One Byte OE/VPP = VIL Verify One Byte OE/VPP = VIL Fail Pass Increment Address Pass No Last Address ? Yes Compare All Bytes to Original Data Pass Device Passed Fail Device Failed - 11 - Publication Release Date: November 1999 Revision A4 W27C512 SMART ERASE ALGORITHM Start X=0 Vcc = 5V OE/Vpp = 14V A9 = 14V; A0 = VIL Chip Erase 100 mS Pulse Address = First Location Increment X Vcc = 3.75V OE/Vpp = V IL No Erase Verify Pass Yes Increment Address No Last Address? Yes Vcc = 5V OE/Vpp = VIL Fail X = 20 ? Compare All Bytes to FFs (HEX) Pass Pass Device Fail Fail Device - 12 - W27C512 ORDERING INFORMATION PART NO. ACCESS TIME (nS) 45 70 90 120 45 70 90 120 OPERATING CURRENT MAX. (mA) 30 30 30 30 30 30 30 30 STANDBY CURRENT MAX. (µ A) 100 100 100 100 100 100 100 100 PACKAGE W27C512-45 W27C512-70 W27C512-90 W27C512-12 W27C512P-45 W27C512P-70 W27C512P-90 W27C512P-12 Notes: 600 mil DIP 600 mil DIP 600 mil DIP 600 mil DIP 32-pin PLCC 32-pin PLCC 32-pin PLCC 32-pin PLCC 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 13 - Publication Release Date: November 1999 Revision A4 W27C512 PACKAGE DIMENSIONS 28-pin P-DIP Dimension in Inches Dimension in mm Symbol Min. Nom. Max. 0.210 0.010 0.150 0.016 0.058 0.008 0.155 0.018 0.060 0.010 1.460 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.064 0.014 1.470 0.610 0.550 0.110 0.140 15 0.670 0.090 Min. Nom. Max. 5.33 0.25 3.81 0.41 1.47 0.20 3.94 0.46 1.52 0.25 37.08 14.99 13.72 2.29 3.05 0 16.00 16.51 15.24 13.84 2.54 3.30 4.06 0.56 1.63 0.36 37.34 15.49 13.97 2.79 3.56 15 17.02 2.29 D 28 15 A A1 A2 B B1 c D E E1 e1 L a E1 eA S Notes: 1 14 S E c A A2 A1 Base Plane Seating Plane L B B1 e1 a eA 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 32-pin PLCC HE E 4 1 32 30 Dimension in Inches Dimension in mm Symbol 5 29 Min. Nom. 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 Max. 0.140 Min. Nom. 0.50 Max. 3.56 GD D HD 13 21 14 20 c A A1 A2 b1 b c D E e GD GE HD HE L y θ Notes: 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0° 10° 0° 10° L A2 A θ Seating Plane e b b1 GE A1 y 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection spec. - 14 - W27C512 VERSION HISTORY VERSION A1 A2 DATE Mar. 1998 Sep. 1998 6 4,6 A3 Aug. 1999 PAGE Initial Issued Correct Imput High Voltage (VIH) from 2.0 (min) to 2.2 (max) Correct VCC from 5.0 ±10% to 5.0 ±5% Modify function description (VIL and VIH): VIL → Low; VIH → High A4 Nov. 1999 6 Typo correction DESCRIPTION 1, 5, 6, 13 Add 45 nS bining 2, 3 Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 15 - Publication Release Date: November 1999 Revision A4