W27E520W-90

W27E520 64K × 8 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27E520 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65,536 × 8 bits. It includes latches for the lower 8 address lines to multiplex with the 8 data lines. To cooperate with the MCU, this device could save the external TTL component, also cost and space. It requires only one supply in the range of 4.5V to 5.5V in normal read mode. The W27E520 provides an electrical chip erase function. It will be a great convenient when you need to change/update the contents in the device. FEATURES • High speed access time: 70/90 nS (max.) • Read operating current: 20 mA (max.) • Erase/Programming operating current • High Reliability CMOS Technology 30 mA (max.) • Standby current: 100 µA (max.) • Unregulated battery power supply range, 4.5V to 5.5V • +13V erase and programming voltage • • • • − 2K V ESD Protection − 200 mA Latchup Immunity Fully static operation All inputs and outputs directly TTL/CMOS compatible Three-state outputs Available packages: 20-pin TSSOP and 20-pin SOP PIN CONFIGURATIONS A10 A12 A14 ALE VDD OE/VPP A15 A13 A11 A9 1 2 3 4 5 6 7 8 9 10 20 19 18 17 BLOCK DIAGRAM A8 AD1 AD3 AD5 AD7 GND AD6 AD4 AD2 AD0 VDD GND A15 - A8 AD7 - AD0 L A T C H E S ALE OE / VPP CONTROL OUTPUT BUFFER TSSOP 16 Top View 15 14 13 12 DECODER MEMORY ARRAY 11 OE/VPP A15 A13 A11 A9 AD0 AD2 AD4 AD6 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 VDD ALE A14 A12 A10 A8 AD1 AD3 AD5 AD7 PIN DESCRIPTION SYMBOL AD0−AD7 A8−A15 ALE OE /VPP VDD GND DESCRIPTION Address/Data Inputs/Outputs Address Inputs Address Latch Enable Output Enable, Program/Erase Supply Voltage Power Supply Ground SOP 16 Top View 15 14 13 12 11 -1- Publication Release Date: September 2000 Revision A2 W27E520 FUNCTIONAL DESCRIPTION Read Mode Unlike conventional UVEPROMs, which has CE and OE two control functions, the W27E520 has one OE /VPP and one ALE (address_latch_enable) control functions. The ALE makes lower address A[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be used to output data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed. OE /VPP controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from ALE to output (TCE), and data are available at the outputs TOE after the falling edge of OE /VPP, if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27E520 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. There are two ways to enter Erase mode. One is to raise OE /VPP to VPE (13V), VDD = VDE (6.5V), A9 = VHH (13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed low or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by programming two consecutive commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is 50uS, while the other is 100mS. Please refer to the Smart Erase Algorithm 1 & 2. Erase Verify Mode The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the device can force the device enter Normal Read Mode again. Program Mode Programming is the only way to change cell data from "1" to "0." The program mode is entered when OE /VPP is raised to VPP (13V), VDD = VDP (6.5V), the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing ALE high starts the programming operation. Program Verify Mode The device will enter the Program Verify Mode automatically after Program Mode. Only power down the device can force the device enter Normal Read Mode again. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the ALE and OE /VPP pins, the W27E520 may have common inputs. Standby Mode The standby mode significantly reduces VDD current. This mode is entered when ALE and OE /VPP keep high. In standby mode, all outputs are in a high impedance state. -2- W27E520 System Considerations An EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (IDD), and transient current peaks produced by the falling and rising edges of ALE Transient current magnitudes depend on the device output's capacitive and inductive loading. Proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its VDD and GND. This high frequency, low inherent-inductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between VDD and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES (VPP = 13V, VPE = 13V, VHH = 12V, VDP = 6.5V, VDE = 6.5V, VDD = 5.0V, VDI = 5.0V, X = VIH or VIL) MODE ALE Address Latch Enable Read Output Disable Standby Program Erase 1 Erase 2 VIH VIL VIL /VIH VIH VIH VIH VIH OE /VPP VIH VIL VIH VIH VPP VPE VPE PIN OTHER ADDRESS AIN AIN X X AIN A8&A11 = VIL, A9 = VPE, A10 = VIH, Others = X First command: Addr. = 5555 (hex) Second command: Addr. = 2AAA (hex) VDD VDD VDD VDD VDD VDP VDE VDE VDE VDI VDI AD[7:0] A[7:0] DOUT High Z A[7:0] DIN X AA(hex) 10(hex) DA(Hex) 1F(Hex) Product Identifiermanufacturer Product Identifier-device VIL VIL VIL VIL A8 = VIL, A9 = VHH, Others = X A8 = VIH, A9 = VHH, Others = X -3- Publication Release Date: September 2000 Revision A2 W27E520 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Ambient Temperature with Power Applied Storage Temperature Voltage on all Pins with Respect to Ground Except OE /VPP, A9 and VDD Pins Voltage on OE /VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground Voltage VDD Pin with Respect to Ground RATING -55 to +125 -65 to +150 -2.0 to +7.0 -2.0 to +7.0 -2.0 to +7.0 -2.0 to +14.0 UNIT °C °C V V V V Notes: 1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 nS. Maximum output pin voltage is VDD +0.75V DC which may overshoot to +7.0V for pulses of less than 20 nS. DC Erase Characteristics (TA = 25° C ±5° C, VDD = 6.5V ±0.25V) PARAMETER Input Load Current VDD Erase Current SYM. ILI ICP CONDITIONS MIN. VIN = VIL or VIH ALE = VIH, OE /VPP = VPE A8 & A11 = VIL, A9 = VPE, A10 = VIH, Others = X ALE = VIH, OE /VPP = VPE A8 & A11 = VIL, A9 = VPE, A10 = VIH, Others = X IOL = 2.1 mA IOH = -0.4 mA VDD = 5V ±10% -10 - LIMITS TYP. MAX. 10 30 UNIT µA mA VPP Erase Current IPP - - 30 mA Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 SID Voltage A9 Erase Voltage VPP Erase Voltage VDD Supply Voltage (Erase & Erase Verify) VIL VIH VOL VOH VHH VPE VPE VDE -0.3 2.4 2.4 11.5 12.75 12.75 6.25 12 13 13 6.5 0.8 VDD+0.3 0.45 12.5 13.25 13.25 6.75 V V V V V V V Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP. -4- W27E520 CAPACITANCE (VDD = 4.5V to 5.5V, TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT VIN = 0V VOUT = 0V MAX. 6 12 UNIT pF pF AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V/3V 10 nS 1.5V/1.5V CL = 100 pF, IOH/IOL = -0.4 mA/2.1 mA CONDITIONS AC Test Load and Waveforms +1.3V (IN914) 3.3K ohm DOUT 100 pF (Including Jig and Scope) Input Test Points 3V 1.5V Output Test Points 1.5V 0V -5- Publication Release Date: September 2000 Revision A2 W27E520 READ OPERATION DC CHARACTERISTICS (VDD = 4.5V to 5.5V, TA = 0 to 70° C) PARAMETER SYM. CONDITIONS MIN. LIMITS TYP. MAX. 5 5 100 UNIT µA µA µA Input Load Current Output Leakage Current Standby VDD Current (CMOS input) VDD Operating Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage ILI ILO ISB VIN = 0V to VDD VOUT = 0V to VDD ALE = VDD ±0.3V, OE /VPP = VDD ±0.3V All others inputs = GND/ VDD ±0.3V ALE = VIL, IOUT = 0 mA f = 5 MHz IOL = 2.1 mA IOH = -0.4 mA -5 -5 - IDD VIL VIH VOL VOH -0.6 2.0 2.4 - 20 0.8 VDD +0.3 0.4 - mA V V V V READ OPERATION AC CHARACTERISTICS (VDD = 4.5V to 5.5V, TA = 0 to 70° C) PARAMETER SYM. W27E520-70 MIN. MAX. 70 70 35 25 - W27E520-90 MIN. 45 15 15 0 MAX. 90 90 35 25 - UNIT Address Latch Enable Access Time Address Latch Enable Width Address Access Time Address Setup Time Address Hold Time Output Enable Access Time OE /VPP High to High-Z Output TCE TALE TACC TAS TAH TOE TDF TOH 45 15 15 0 nS nS nS nS nS nS nS nS Output Hold from Address Change Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP. -6- W27E520 DC PROGRAMMING CHARACTERISTICS (VDD = 6.5V ±0.25V, TA = 25° C ±5° C) PARAMETER Input Load Current VDD Program Current VPP Program Current Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Silicon I.D. Voltage VPP Program Voltage VDD Supply Voltage (Program) SYM. ILI ICP IPP VIL VIH VOL VOH VHH VPP VDP CONDITIONS VIN = VIL or VIH ALE = VIH, OE /VPP = VPP ALE = VIH, OE /VPP = VPP LIMITS MIN. -10 -0.3 2.4 2.4 11.5 12.75 6.25 TYP. 12.0 13.0 6.5 MAX. 10 30 30 0.8 VDD+0.5 0.45 12.5 13.25 6.75 UNIT µA mA mA V V V V V V V IOL = 2.1 mA IOH = -0.4 mA VDD = 5V ±10% - AC PROGRAMMING/ERASE CHARACTERISTICS (VDD = 6.5V ±0.25V, TA = 25° C ±5° C) PARAMETER OE /VPP Pulse Rise Time Address Latch Enable Width ALE Program Pulse Width SYM. TPRT TALE TPPW TEPW TEPW1 TEPW2 TLAS TLAH TAS TAH TOES TOEH TDS TDH TEOE TPOE TDFP TVS TVR MIN. 50 500 47.5 95 47.5 95 100 100 2.0 0 2.0 2.0 2.0 2.0 0 2.0 2.0 LIMITS TYP. 50 100 50 100 - UNIT MAX. 52.5 105 52.5 105 150 150 130 nS nS µS mS µS mS nS nS µS µS µS µS µS µS nS nS nS µS µS ALE Erase Pulse Width ALE Erase Pulse Width 1 ALE Erase Pulse Width 2 Latched Address Setup Time Latched Address Hold Time Address Setup Time Address Hold Time OE /VPP Setup Time OE /VPP Hold Time Data Setup Time Data H old Time Data Valid from Data Valid from OE /VPP Low during Erase Verify OE /VPP Low during Program Verify OE /VPP High to Output High Z OE /VPP High Voltage Delay After ALE Low OE /VPP Recovery Time Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP. -7- Publication Release Date: September 2000 Revision A2 W27E520 TIMING WAVEFORMS AC Read Waveform VIH A8-A15 VIL TALE ALE VIH VIL VIH OE/Vpp VIL AD0-AD7 High Z TAS Address TACC TAH TCE TOE Address Valid TDF TOH High Z Data Programming Waveform PROGRAM VIH V IL TRPT TAS Address Stable PROGRAM (VERIFY) TAH A[15:8] 13V VIH V IL OE/Vpp TOES TOEH T VS TVR TALE TDH Add TPOE TDFP Data out ALE VIH V IL TALE TPPW TLAH Add T DS Data in TLAS AD[7:0] VIH V IL -8- W27E520 Timing Waveforms, continued Erase Waveform 1 Read Company SID Read Device SID Chip Erase VDD = 6.5V A9 = 13.0V Others = V or VIH IL A8, A11 = V IL A10 = V IH Erase (Verify) VDD = 6.5V VDD = 5.0V A9 = 12.0V V IH V IL V IH AD[7:0] V IL DA 1F TPRT Others = VIL or VIH A8 = VIL A8 = VIH A[15:8] Address Valid Add TVR DOUT 13.0V V IH OE/Vpp V IL V IH ALE V IL TEOE TOEH TOES TEPW Erase Waveform 2 Read Company SID Read Device SID Chip Erase Command 1 VDD =6.5V TAS A[15:8] = 55 A[15:8] = 2A Command 2 VDD =6.5V Erase Verify VDD =6.5V A[15:8] V IH V IL VDD =5.0V A9=12.0 V Others=V IL or VIH A8=VIL A8=V IH Address Valid TRPT OE/Vpp V IH V IL TVS TPRT V IH V IL TOES V IH AD[7:0] V IL DA TLAS 1F 55 TOES TOEH TEOE TALE TLAH TEPW1 TDS AA TEPW2 TDH AA 10 Add DOUT Note: First command Address = 5555(hex) with Data = AA(hex) Second command Address = 2AAA(hex) with Data = 10(hex) -9- Publication Release Date: September 2000 Revision A2 W27E520 SMART PROGRAMMING ALGORITHM 1 Start Address = First Location VDD = 6.5V OE/Vpp = 13V Program One 50 µS Pulse Increment Address No Last Address ? Yes Address = First Location Increment Address No Last Address ? Pass X=0 Verify Byte Fail Increment X Yes Power Down Program One 50 µS Pulse No X = 25 ? VDD = 5.0V OE/Vpp = VIL Yes Compare All Bytes to Original Data Pass Device Passed Fail Device Failed - 10 - W27E520 SMART PROGRAMMING ALGORITHM 2 Start Address = First Location VDD = 6.5V X=0 Program One 50 µS Pulse OE/Vpp = 13V Increment X X = 25? No Fail Verify One Byte OE/Vpp = V IL Verify One Byte OE/Vpp = V IL Yes Fail Pass Increment Address Pass No Last Address ? Yes Power Down VDD =5.0V Compare All Bytes to Original Data Pass Device Passed Fail Device Failed - 11 - Publication Release Date: September 2000 Revision A2 W27E520 SMART ERASE ALGORITHM 1 Start X=0 VDD= 6.5V OE/Vpp = 13V A9 = 13V; A8&A11 = V IL A10 = V IH Chip Erase 100 mS Pulse Address = First Location Increment X VDD = 6.5V OE/Vpp = VIL No Erase Verify Pass Yes Increment Address No Last Address? Yes Power Down Fail X = 20? VDD = 5.0V OE/Vpp = VIL Compare All Bytes to FFs (HEX) Pass Pass Device Fail Fail Device - 12 - W27E520 SMART ERASE ALGORITHM 2 Start X=0 VDD = 6.5V OE/Vpp = 13V Program One 50µ S Pulse with Address = 5555(Hex) Data = AA(Hex) Program One 100 mS Pulse with Address = 2AAA(Hex) Data = 10(Hex) Increment X VDD = 6.5V OE/Vpp = VIL No Erase Verify Pass Yes Increment Address No Last Address? Yes Power Down Fail X = 20? VDD = 5.0V OE/Vpp = VIL Compare All Bytes to FFs (HEX) Pass Pass Device Fail Fail Device - 13 - Publication Release Date: September 2000 Revision A2 W27E520 ORDERING INFORMATION PART NO. ACCESS TIME (nS) 70 90 70 90 OPERATING CURRENT MAX. (mA) 20 20 20 20 STANDBY CURRENT MAX. (µ A) 100 100 100 100 PACKAGE W27E520W-70* W27E520W-90* W27E520S-70* W27E520S-90* Notes: 173mil TSSOP 173mil TSSOP 300mil SOP 300mil SOP 1. The Part No is preliminary and might be changed after project is consoled. 2. Winbond reserves the right to make changes to its products without prior notice. 3. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 14 - W27E520 PACKAGE DIMENSIONS 20-pin TSSOP c b L Dimension in Inches Dimension in mm Symbol Min. Nom. Max. 0.043 Min. Nom. Max. 1.10 0.15 0.70 6.60 6.50 4.48 0.30 0.18 0.256 BSC E1 E A A1 L D E E1 b c e θ 0.002 0.020 0.252 0.246 0.169 0.007 0.003 0.65 BSC 0 0.006 0.05 0.028 0.50 0.260 6.40 0.256 0.176 6.25 4.30 e D A A1 θ 0.012 0.18 0.007 0.09 8 0 8 20-pin SOP c b L Dimension in Inches Dimension in mm Symbol Min. 0.092 0.003 0.015 0.497 0.393 0.291 0.013 0.009 Nom. Max. 0.105 Min. 2.34 Nom. Max. 2.67 0.305 0.889 13.0 10.7 7.60 0.508 0.330 E1 E A A1 L D E E1 b c e θ 0.012 0.076 0.035 0.381 0.513 12.6 0.420 0.299 9.98 7.39 e D A A1 θ 0.020 0.330 0.013 0.229 1.27 BSC 8 0 0.50 BSC 0 8 - 15 - Publication Release Date: September 2000 Revision A2 W27E520 VERSION HISTORY VERSION A1 A2 DATE Jun. 2000 Sep. 2000 PAGE 9 3 Initial Issued Correct Erase Waveform Modify Address Latch Enable Mode: X -> Ain; Modify Output Disable Mode: VIL -> VIL/VIH; Modify Standby Mode: Ain -> X; Typo Correction 1 Modify Feature description: LVTTL -> TTL DESCRIPTION Headquarters Headquarters Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min -Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change withou t notice. - 16 -