W27L010S-90

Preliminary W27L010 128K × 8 ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read Only Memory organized as 131072 × 8 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode. The W27L010 provides an electrical chip erase function. FEATURES • • • • • High speed access time: 90/120 nS (max.) Read operating current: 10 mA (max.) Erase/Programming operating current: 30 mA (max.) Standby current: 20 µA (max.) Low voltage power supply range, 3.0V to 3.6V • • • • • +14V erase/+12V programming voltage Fully static operation All inputs and outputs directly TTL/CMOS compatible Three-state outputs Available packages: 32-pin 600 mil DIP, 450 mil SOP and PLCC PIN CONFIGURATIONS Vpp A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin DIP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 / VVP pcGN p c MC 1 33 21 Vcc PGM NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3 BLOCK DIAGRAM PGM CE OE CONTROL OUTPUT BUFFER Q0 . . Q7 A0 . DECODER . A16 CORE ARRAY VCC GND VPP PIN DESCRIPTION SYMBOL A0−A16 Q0−Q7 CE OE PGM VPP VCC GND NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program Enable Program/Erase Supply Voltage Power Supply Ground No Connection AAA 111 256 A7 A6 A5 A4 A3 A2 A1 A0 Q0 4 5 6 7 8 9 10 11 12 1 13 4 3 0 29 28 27 26 32-pin PLCC 25 24 23 1 1 1 1 1 2 22 5 6 7 8 9 0 21 32 A14 A13 A8 A9 A11 OE A10 CE Q7 Q QGQ QQQ 1 2N3 456 D -1- Publication Release Date: February 1999 Revision A1 Preliminary W27L010 FUNCTIONAL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27L010 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE , if TACC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27L010 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 = VHH (14V), A0 low, and all other address pins low and data input pins high. Pulsing PGM low starts the erase operation. Erase Verify Mode After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE low, and OE low, PGM high. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), CE low , OE hig, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing PGM low starts the programming operation. Program Verify Mode All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE low, OE low, and PGM high. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , erasing or programming of non-target chips is inhibited, so that except for the CE , the W27L010 may have common inputs. -2- Preliminary W27L010 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE and PGM . Two-line Output Control Since EPROMs are often used in large memory arrays, the W27L010 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (Isb), active current levels (Icc), and transient current peaks produced by the falling and rising edges of CE . Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its Vcc and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. TABLE OF OPERATING MODES VCC = 3.3V, VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X=VIH or VIL MODE CE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Erase Erase Verify Erase Inhibit Product IdentifierManufacturer Product Identifier-device VIL VIL VIH VCC ±0.3V VIL VIL VIH VIL VIL VIH VIL VIL OE VIL VIH X X VIH VIL X VIH VIL X VIL VIL PINS PGM X X X X VIL VIH X VIL VIH X X X A0 X X X X X X X VIL X X VIL VIH A9 X X X X X X X VPE X X VHH VHH VCC VCC VCC VCC VCC VCP VCP VCP VCP VCP VCP VCC VCC VPP VCC VCC VCC VCC VPP VPP VPP VPE VPE VPE VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z FF (Hex) DOUT High Z DA (Hex) 01 (Hex) -3- Publication Release Date: February 1999 Revision A1 Preliminary W27L010 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Operation Temperature Storage Temperature Voltage on all Pins with Respect to Ground Except VCC, VPP and A9 Pins Voltage on VCC Pin with Respect to Ground Voltage on VPP Pin with Respect to Ground Voltage on A9 Pin with Respect to Ground RATING 0 to +70 -65 to +125 -0.5 to VCC +0.5 -0.5 to +7 -0.5 to +14.5 -0.5 to +14.5 UNIT °C °C V V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (TA = 25° C ±5° C, VCC = 5.0V ±10%, VHH = 14V) PARAMETER SYM. CONDITIONS MIN. LIMITS TYP. MAX. 10 30 UNIT µA mA Input Load Current VCC Erase Current ILI ICP VIN = VIL or VIH CE = VIL, OE = VIH, PGM = VIL, A9 = VHH -10 - VPP Erase Current IPP CE = VIL, OE = VIH, PGM = VIL, A9 = VHH - - 30 mA Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Erase Voltage VPP Erase Voltage VCC Supply Voltage (Erase) VIL VIH VOL VOH VID VPE VCE IOL = 2.1 mA IOH = -0.4 mA - -0.3 2.4 2.4 13.25 13.25 4.5 14.0 14.0 5.0 0.8 5.5 0.45 14.25 14.25 5.5 V V V V V V V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -4- Preliminary W27L010 CAPACITANCE (VCC = 3.0V to 3.6V , TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT CONDITIONS VIN = 0V VOUT = 0V MAX. 6 12 UNIT pF pF AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0.45V to 2.4V 10 nS 0.8V/2.0V CL = 100 pF, IOH/IOL = -0.1 mA/1.6 mA CONDITIONS AC Test Load and Waveforms +1.3V (IN914) 3.3K ohm D OUT 100 pF (Including Jig and Scope) Input Test Points 2.4V 0.45V 2.0V 0.8V Output Test Points 2.0V 0.8V -5- Publication Release Date: February 1999 Revision A1 Preliminary W27L010 READ OPERATION DC CHARACTERISTICS (VCC = 3.0V to 3.6V, TA = 0 to 70° C) PARAMETER SYM. CONDITIONS MIN. LIMITS TYP. MAX. 5 10 200 20 10 UNIT Input Load Current Output Leakage Current Standby VCC Current (TTL input) Standby VCC Current (CMOS input) VCC Operating Current ILI ILO ISB ISB1 ICC VIN = 0V to VCC VOUT = 0V to VCC CE = VIH CE = VCC ±0.2V CE = VIL IOUT = 0 mA f = 5 MHz VPP = VCC IOL = 1.6 mA IOH = -0.1 mA - -5 -10 - µA µA µA µA mA VPP Operating Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Operating Voltage IPP VIL VIH VOL VOH VPP -0.3 2.0 2.4 VCC -0.7 - 10 0.6 VCC +0.5 0.4 VCC µA V V V V V READ OPERATION AC CHARACTERISTICS (VCC = 3.0V to 3.6V, TA = 0 to 70° C) PARAMETER SYM. W27L010-90 MAX. MIN. 90 90 40 25 - W27L010-12 MAX. 120 0 MIN. 120 120 55 30 - UNIT Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time OE High to High-Z Output Output Hold from Address Change TRC TCE TACC TOE TDF TOH 90 0 nS nS nS nS nS nS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -6- Preliminary W27L010 DC PROGRAMMING CHARACTERISTICS (VCC = 5.0V ±10%, TA = 25° C ±5° C) PARAMETER Input Load Current VCC Program Current SYM. ILI ICP CONDITIONS MIN. VIN = VIL or VIH CE = VIL, OE = VIH, PGM = VIL - LIMITS TYP. MAX. 10 30 UNIT µA mA VPP Program Current IPP CE = VIL, OE = VIH, PGM = VIL IOL = 2.1 mA IOH = -0.4 mA - - - 30 mA Input Low Voltage Input High Voltage Output Low Voltage (Verify) Output High Voltage (Verify) A9 Silicon I.D. Voltage VPP Program Voltage VCC Supply Voltage (Program) VIL VIH VOL VOH VID VPP VCP -0.3 2.4 2.4 11.5 11.75 4.5 12.0 12.0 5.0 0.8 5.5 0.45 12.5 12.25 5.5 V V V V V V V AC PROGRAMMING/ERASE CHARACTERISTICS (VCC = 5.0V ±10%, TA = 25° C ±5° C) PARAMETER VPP Setup Time Address Setup Time Data Setup Time PGM Program Pulse Width PGM Erase Pulse Width Data Hold Time OE Setup Time Data Valid from OE OE High to Output High Z Address Hold Time after PGM High Address Hold Time (Erase) CE Setup Time SYM. MIN. TVPS TAS TDS TPWP TPWE TDH TOES TOEV TDFP TAH TAHE TCES 2.0 2.0 2.0 95 95 2.0 2.0 0 0 2.0 2.0 LIMITS TYP. 100 100 MAX. 105 105 150 130 - UNIT µS µS µS µS mS µS µS nS nS µS µS µS Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. -7- Publication Release Date: February 1999 Revision A1 Preliminary W27L010 TIMING WAVEFORMS AC Read Waveform VIH Address VIL VIH CE VIL Address Valid TCE VIH OE VIL TACC Outputs High Z Valid Output High Z TOE TDF TOH Erase Waveform Read Manufacturer Read Device Chip Erase A9 = 14.0V Others = V IL Address Stable TAS 01 TDS 14.0V 5.0V TVPS V PP VIH CE VIL TOE VIH OE VIL TPWE TOEV TOE TOES TOE TCE 2.7V TAHC Data All One TDH TDFP DOUT T AH 3.3V DOUT Address Stable Address Stable TACC DOUT Erase Verify Blank Check Read Verify SID SID A9 = 12.0V Others = VIL A0 = V IL VIL TAS DA A0=V IH Others=V IL VIH Address TAS Data TCES PGM -8- Preliminary W27L010 Timing Waveforms, Continued Programming Waveform Program VIH Address VIL TAS Address Stable Program Verify Read Verify Address Stable Address Valid TDFP TACC DOUT DOUT Data Data In Stable DOUT TDS 12.0V VPP 5.0V VIH CE VIL VIH OE VIL VIH PGM VIL TPWP TDH TAH 5V TVPS TCES TOE TOES TOEV -9- Publication Release Date: February 1999 Revision A1 Preliminary W27L010 SMART PROGRAMMING ALGORITHM Start Address = First Location Vcc = 5V Vpp = 12V X=0 Program One 100 µS Pulse Increment X Yes X = 25? No Fail Verify One Byte Pass Increment Address No Last Address? Yes Vcc = 3.3V Vpp = 3.3V Verify One Byte Pass Fail Compare All Bytes to Original Data Pass Pass Device Fail Fail Device - 10 - Preliminary W27L010 SMART ERASE ALGORITHM Start X=0 Vcc = 5V Vpp = 14V A9 = 14V; A0 = V IL Chip Erase 100 mS Pulse Address = First Location Increment X Vcc = 2.7V Vpp = 2.7V No Erase Verify Pass Yes Increment Address No Last Address? Yes Vcc = 3.3V Vpp = 3.3V Fail X = 20? Compare All Bytes to FFs (HEX) Pass Pass Device Fail Fail Device - 11 - Publication Release Date: February 1999 Revision A1 Preliminary W27L010 ORDERING INFORMATION PART NO. ACCESS TIME (nS) 90 120 90 120 90 120 POWER SUPPLY CURRENT MAX. (mA) 8 8 8 8 8 8 STANDBY VCC CURRENT MAX. (µ A) 20 20 20 20 20 20 PACKAGE W27L010-90 W27L010-12 W27L010S-90 W27L010S-12 W27L010P-90 W27L010P-12 Notes: 600 mil DIP 600 mil DIP 450 mil SOP 450 mil SOP 32-pin PLCC 32-pin PLCC 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. PACKAGE DIMENSIONS 32-pin P-DIP Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. 0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15 0.670 0.085 14.99 13.84 2.29 3.05 0 16.00 16.51 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 41.91 15.24 13.97 2.54 3.30 4.06 0.56 1.37 0.36 42.16 15.49 14.10 2.79 3.56 15 17.02 2.16 5.33 D 32 17 E1 A A1 A2 B B1 c D E E1 e1 L a 1 16 eA S E c Notes: 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. S A A2 L B B1 A1 Base Plane Seating Plane e1 a eA - 12 - Preliminary W27L010 Package Dimensions, Continued 32-pin SO Wide Body Dimension in mm Dimension in Inches Symbol 32 17 Min. 0.004 0.101 0.014 0.006 Nom. Max. 0.118 Min. 0.10 Nom. Max. 3.00 e1 E HE θ L Detail F 1 16 b A A1 A2 b c D E e HE L LE S y θ Notes: 0.106 0.016 0.008 0.805 0.111 0.020 0.012 0.817 0.450 0.056 0.556 0.039 0.063 0.036 0.004 2.57 0.36 0.15 2.69 0.41 0.20 20.45 2.82 0.51 0.31 20.75 11.43 1.42 14.38 0.99 1.60 0.91 0.10 0.440 0.044 0.546 0.023 0.047 0.445 0.050 0.556 0.031 0.055 11.18 1.12 13.87 0.58 1.19 11.30 1.27 14.12 0.79 1.40 0 10 0 10 D e1 c A2 A S y e A1 LE 1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec. See Detail F Seating Plane 32-Lead PLCC HE E 4 1 32 30 Symbol 5 29 Dimension in Inches Dimension in mm Min. 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 Nom. Max. 0.140 Min. 0.50 Nom. Max. 3.56 GD D HD 13 21 14 20 c A A1 A2 b1 b c D E e GD GE HD HE L y θ Notes: 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0° 10° 0° 10° L A2 A θ Seating Plane e b b1 GE A1 y 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. - 13 - Publication Release Date: February 1999 Revision A1 Preliminary W27L010 VERSION HISTORY VERSION A1 DATE Feb. 1999 PAGE Initial Issued DESCRIPTION Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792647 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006 Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. - 14 -