W29C020C-70B

W29C020C 256K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29C020C is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29C020C results in fast write (erase/program) operations with extremely low current consumption compared to other comparable 5volt flash memory products. The device can also be written (erased and programmed) by using standard EPROM programmers. FEATURES • Single 5-volt write (erase and program) • • Software and hardware data protection Low power consumption − Active current: 25 mA (typ.) − Standby current: 20 µA (typ.) operations • Fast page-write operations − 128 bytes per page − Page write (erase/program) cycle: 10 mS (max.) − Effective byte-write (erase/program) cycle time: 39 µS − Optional software-protected data write • Fast chip-erase operation: 50 mS • Two 8 KB boot blocks with lockout • Whole chip cycling: 10K (typ.) • Read access time: 70/90/120 nS • Twenty-year data retention • Automatic write (erase/program) timing with internal VPP generation • End of write (erase/program) detection − Toggle bit − Data polling • Latched address and data • All inputs and outputs directly TTL compatible • JEDEC standard byte-wide pinouts • Available packages: 32-pin 600 mil DIP, 32-pin TSOP, and 32-pin PLCC -1- Publication Release Date: April 2000 Revision A2 W29C020C PIN CONFIGURATIONS BLOCK DIAGRAM VDD NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 VDD WE A17 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS CE OE WE CONTROL OUTPUT BUFFER DQ0 . . DQ7 32-pin DIP 26 25 24 23 22 21 20 19 18 17 A0 . . . DECODER 8K Byte Boot Block (Optional) CORE ARRAY 8K Byte Boot Block (Optional) A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 AA 11 56 3 2 N C V/ DW DE A 1 7 A17 1 32 31 30 29 28 27 A14 A13 A8 A9 A11 OE A10 CE DQ7 32-pin PLCC 26 25 24 23 22 21 14 15 16 17 18 19 20 PIN DESCRIPTION SYMBOL A0−A17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 DDGD QQNQ 12D3 DDD QQQ 456 PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection A11 A9 A8 A13 A14 A17 WE VDD NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 DQ0−DQ7 CE OE WE VDD GND NC 32-pin TSOP -2- W29C020C FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29C020C is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the read cycle timing waveforms for further details. Page Write Mode The W29C020C is written (erased/programmed) on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page. The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE , whichever occurs last. The data are latched by the rising edge of either CE or WE , whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 µS after the initial byte-load cycle, the W29C020C will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal write (erase/program) cycle will start if no additional byte is loaded into the page buffer A7 to A17 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal write cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal write cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a three-byte command sequence (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29C020C is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte command sequence cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command Publication Release Date: April 2000 Revision A2 -3- W29C020C sequence is required. For information about specific codes, see the Command Codes for Software Data Protection in the Table of Operating Modes. For information about timing waveforms, see the timing diagrams below. Hardware Data Protection The integrity of the data stored in the W29C020C is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The write operation is inhibited when VDD is less than 2.5V. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD reaches its sense level, the device will automatically timeout for 5 mS before any write (erase/program) operation. Chip Erase Modes The entire device can be erased by using a six-byte software command code. See the Software Chip Erase Timing Diagram. Boot Block Operation There are two boot blocks (8K bytes each) in this device, which can be used to store boot code. One of them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory. The first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command sequence. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function will be disabled. In order to detect whether the boot block feature is set on the two 8K blocks, users can perform a six-byte command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "00002 hex" (for the first 8K bytes) or "3FFF2 hex" (for the last 8K bytes). If the output data is "FF hex," the boot block programming lockout feature is activated; if the output data is "FE hex," the lockout feature is deactivated and the block can be programmed. To return to normal operation, perform a three-byte command sequence to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. Data Polling (DQ7)- Write Status Detection The W29C020C includes a data polling feature to indicate the end of a write cycle. When the W29C020C is in the internal write cycle, any attempt to read DQ7 from the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed. DQ7 will show the true data. See the OE Polling Timing Diagram. -4- W29C020C Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W29C020C provides another method for determining the end of a write cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. See Toggle Bit Timing Diagram. Product Identification The product ID operation outputs the manufacturer code and device code. The programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed through software or by hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001 hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. TABLE OF OPERATING MODES Operating Mode Selection Operating Range: 0 to 70° C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V MODE CE Read Write Standby Write Inhibit VIL VIL VIH X X Output Disable 5-Volt Software Chip Erase Product ID X VIL VIL VIL OE VIL VIH X VIL X VIH VIH VIL VIL WE VIH VIL X X VIH X VIL VIH VIH AIN AIN X X X X AIN PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z DIN Manufacturer Code DA (Hex) Device Code 45 (Hex) DQ. A0 = VIL; A1−A17 = VIL; A9 = VHH A0 = VIH; A1−A17 = VIL; A9 = VHH -5- Publication Release Date: April 2000 Revision A2 W29C020C Command Codes for Software Data Protection BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write - TO ENABLE PROTECTION ADDRESS 5555H 2AAAH 5555H DATA AAH 55H A0H TO DISABLE PROTECTION ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 20H Software Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AA to address 5555 Software Data Protection Disable Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data A0 to address 5555 Load data 80 to address 5555 (Optional page-load operation) Sequentially load up to 128 bytes of page data Load data AA to address 5555 Pause 10 mS Load data 55 to address 2AAA Exit Load data 20 to address 5555 Pause 10 mS Exit Notes for software program code: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -6- W29C020C Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Software Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -7- Publication Release Date: April 2000 Revision A2 W29C020C Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE ALTERNATE PRODUCT (7) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 5555 2AAA 5555 Pause 10 µS DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 10 µS DATA AAH 55H 80H AAH 55H 60H SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT ADDRESS 5555H 2AAAH 5555H Pause 10 µS DATA AAH 55H F0H - Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 (2) Read address = 00000 data = DA Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit (1) Load data 55 to address 2AAA Load data AA to address 5555 Load data 80 to address 5555 (2) Read address = 00001 data = 45 Load data 55 to address 2AAA Load data AA to address 5555 (4) Read address = 00002 data = FF/FE Load data F0 to address 5555 Load data 55 to address 2AAA (5) Read address = 3FFF2 data = FF/FE Pause 10 µ S Load data 60 to address 5555 (6) Normal Mode Pause 10 µ S Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7 −DQ0 (Hex); Address Format: A14−A0 (Hex) (2) A1−A16 = VIL; manufacture code is read for A0 = V IL; device code is read for A0 = VIH . (3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond to first 8K/last 8K) lockout detection mode if power down. (4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is inactivated and the block can be programmed. (6) The device returns to standard operation mode. (7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used. -8- W29C020C Command Codes for Boot Block Lockout Enable BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ON FIRST 8K ADDRESS BOOT BLOCK ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H 00000H Pause 10 µ S DATA AAH 55H 80H AAH 55H 40H 00H BOOT BLOCK LOCKOUT FEATURE SET ON LAST 8K ADDRESS BOOT BLOCK ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H 3FFFFH Pause 10 µS DATA AAH 55H 80H AAH 55H 40H FFH 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set on First 8K Address Boot Block Load data AA to address 5555 Boot Block Lockout Feature Set on Last 8K Address Boot Block Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data 80 to address 5555 Load data 80 to address 5555 Load data AA to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data 40 to address 5555 Load data 40 to address 5555 Load data 00 to address 00000 Load data FF to address 3FFFF Pause 10 mS Pause 10 mS Notes for boot block lockout enable: 1. Data Format: DQ7−DQ0 (Hex) 2. Address Format: A14−A0 (Hex) 3. If you have any questions about this commend sequence, please contact the local distributor or Winbond Electronics Corp. -9- Publication Release Date: April 2000 Revision A2 W29C020C DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Except A9 Transient Voltage (