W29EE011P90B

W29EE011 128K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29EE011 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29EE011 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES • • Single 5-volt program and erase operations Fast page-write operations − 128 bytes per page − Page program cycle: 10 mS (max.) − Effective byte-program cycle time: 39 µS − Optional software-protected data write • Low power consumption − Active current: 25 mA (typ.) − Standby current: 20 µA (typ.) • • Automatic program timing with internal VPP generation End of program detection − Toggle bit − Data polling • • • • • Fast chip-erase operation: 50 mS Read access time: 90/150 nS Page program/erase cycles: 1K/10K Ten-year data retention Software and hardware data protection • • • • Latched address and data TTL compatible I/O JEDEC standard byte-wide pinouts Available packages: 32-pin 600 mil DIP, TSOP, and PLCC -1- Publication Release Date: July 1999 Revision A12 W29EE011 PIN CONFIGURATIONS BLOCK DIAGRAM NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 VDD WE NC A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS CE OE WE CONTROL OUTPUT BUFFER DQ0 . . 32-pin DIP 26 25 24 23 22 21 20 19 18 17 DQ7 A0 . . DECODER CORE ARRAY A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 AA 11 56 3 2 N C V/ DWN DEC A16 29 28 27 A14 A13 A8 A9 A11 OE A10 CE DQ7 1 32 31 30 32-pin PLCC 26 25 24 23 22 21 14 15 16 17 18 19 20 PIN DESCRIPTION SYMBOL A0−A16 32 31 30 29 28 27 DDGD QQNQ 12D3 DDD QQQ 456 PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection A11 A9 A8 A13 A14 NC WE VDD NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin TSOP 26 25 24 23 22 21 20 19 18 17 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 DQ0−DQ7 CE OE WE VDD GND NC -2- W29EE011 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29EE011 is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29EE011 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FFh" during programming of the page. The write operation is initiated by forcing CE and W E low and OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either CE or W E , whichever occurs last. The data are latched by the rising edge of either CE or WE , whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 µS, after the initial byte-load cycle, the W29EE011 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer within 300 µS (TBLCO) from the last byte-load cycle, i.e., there is no subsequent WE high-to-low transition after the last rising edge of W E . A7 to A16 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29EE011 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram. Publication Release Date: July 1999 Revision A12 -3- W29EE011 Hardware Data Protection The integrity of the data stored in the W29EE011 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 3.8V. (3) Write Inhibit Mode: Forcing OE low, CE high, or W E high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. Data Polling (DQ7)-Write Status Detection The W29EE011 includes a data polling feature to indicate the end of a programming cycle. When the W29EE011 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. Toggle Bit (DQ6)-Write Status Detection In addition to data polling, the W29EE011 provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the device code (C1h). The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing CE and OE low, W E high, and raising A9 to 12 volts. -4- W29EE011 TABLE OF OPERATING MODES Operating Mode Selection Operating Range = 0 to 70°C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V MODE CE OE WE PINS ADDRESS AIN AIN X X X X AIN A0 = VIL; A1-A16 = VIL; A9 = VHH A0 = VIH; A1-A16 = VIL; A9 = VHH Dout Din High Z High Z/DOUT High Z/DOUT High Z DIN Manufacturer Code DA (Hex) Device Code C1 (Hex) DQ. Read Write Standby Write Inhibit Output Disable 5-Volt Software Chip Erase Product ID VIL VIL VIH X X X VIL VIL VIL VIL VIH X VIL X VIH VIH VIL VIL VIH VIL X X VIH X VIL VIH VIH -5- Publication Release Date: July 1999 Revision A12 W29EE011 Command Codes for Software Data Protection BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION ADDRESS 5555H 2AAAH 5555H DATA AAH 55H A0H TO DISABLE PROTECTION ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 20H Sofware Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AA to address 5555 Software Data Protection Disable Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data A0 to address 5555 (Optional page load operation) Load data 80 to address 5555 Sequentially load up to 128 bytes of page data Load data AA to address 5555 Pause 10 mS Load data 55 to address 2AAA Exit Load data 20 to address 5555 Pause 10 mS Exit Notes for software program code: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -6- W29EE011 Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Sofware Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -7- Publication Release Date: July 1999 Revision A12 W29EE011 Command Codes for Product Identification BYTE SEQUENCE SOFTWARE PRODUCT IDENTIFICATION ENTRY ADDRESS DATA 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H Pause 10 µS SOFTWARE PRODUCT IDENTIFICATION EXIT ADDRESS DATA 5555H AAH 2AAAH 55H 5555H F0H Pause 10 µS 0 1 2 3 4 5 Write Write Write Write Write Write Software Product Identification Acquisition Flow Product Identification Entry(1) Load data AA to address 5555 Product Identification Mode(2, 3) Product Identification Exit(1) Load data 55 to address 2AAA Load data AA to address 5555 Load data 80 to address 5555 Read address = 0 data = DA Load data 55 to address 2AAA Load data AA to address 5555 Load data FO to address 5555 Load data 55 to address 2AAA Read address = 1 data = C1 S Pause 10 µm Load data 60 to address 5555 (4) Normal Mode Pause 10 µ S Notes for software product identification: (1) Data format: DQ7−DQ0 (Hex); address format: A14−A0 (Hex). (2) A1−A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns to standard operation mode. -8- W29EE011 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential except OE Transient Voltage (< 20 nS ) on Any Pin to Ground Potential Voltage on OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V °C °C V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER Power Supply Current SYM. ICC TEST CONDITIONS MIN. CE = OE = VIL, W E = VIH, all I/Os open Address inputs = VIL/VIH, at f = 5 MHz CE = VIH, all I/Os open Other inputs = VIL/VIH LIMITS TYP. MAX. 50 - UNIT mA Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage ISB1 ISB2 ILI ILO VIL VIH -0.3 2.0 2.4 2 20 - 3 100 1 10 0.8 VDD +0.5 0.45 - mA µA µA µA V V V V CE = VDD -0.3V, all I/Os open Other inputs = VDD -0.3V/GND VIN = GND to VDD VIN = GND to VDD - VOL IOL = 2.1 mA VOH IOH = -0.4 mA Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU.READ TPU.WRITE TYPICAL 100 5 UNIT µS mS -9- Publication Release Date: July 1999 Revision A12 W29EE011 CAPACITANCE (VDD = 5.0V, TA = 25° C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL CI/O CIN CONDITIONS VI/O = 0V VIN = 0V MAX. 12 6 UNIT pF pF AC CHARACTERISTICS AC Test Conditions (VDD = 5V ±10%) PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3V < 5 nS 1.5V/1.5V CONDITIONS 1 TTL Gate and CL = 30 pF for 70 nS and 100 pF for others. AC Test Load and Waveforms +5V 1.8K ohm DOUT 100 pF for 90/120/150 nS 30 pF for 70 nS (Including Jig and Scope) 1.3K ohm Input 3V 1.5V 0V Output 1.5V Test Point Test Point - 10 - W29EE011 Read Cycle Timing Parameters (VCC = 5.0V ±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. W29EE011-90 W29EE011-15 UNIT MIN. Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output MAX. 90 90 45 45 45 - MIN. 150 0 0 0 MAX. 150 150 70 45 45 nS nS nS nS nS nS nS nS nS TRC TCE TAA TOE TCLZ TOLZ TCHZ TOHZ TOH 90 0 0 0 Output Hold from Address Change Byte/Page-write Cycle Timing Parameters PARAMETER Write Cycle (Erase and Program) Address Setup Time Address Hold Time WE and CE Setup Time WE and CE Hold Time OE High Setup Time OE High Hold Time CE Pulse Width WE Pulse Width WE High Width Data Setup Time Data Hold Time Byte Load Cycle Time Byte Load Cycle Time-out SYMBOL TWC TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBLC TBLCO MIN. 0 50 0 0 10 10 70 70 150 50 10 0.22 300 TYP. MAX. 10 200 UNIT mS nS nS nS nS nS nS nS nS nS nS nS µS µS Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 11 - Publication Release Date: July 1999 Revision A12 W29EE011 Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. W29EE011-90 W29EE011-15 UNIT MIN. OE to Data Polling Output Delay CE to Data Polling Output Delay OE to Toggle Bit Output Delay CE to Toggle Bit Output Delay MAX. 45 90 45 90 MIN. - MAX. 70 150 70 150 nS nS nS nS TOEP TCEP TOET TCET - TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A16-0 CE TCE OE TOE WE VIH TOLZ T OHZ TCLZ High-Z TOH Data Valid TAA TCHZ High-Z Data Valid DQ7-0 - 12 - W29EE011 Timing Waveforms, continued WE Controlled Write Cycle Timing Diagram TBLCO TAS Address A16-0 TAH T WC CE TCS TOES TCH T OEH OE TWP TWPH WE TDS DQ7-0 Data Valid TDH Internal write starts CE Controlled Write Cycle Timing Diagram TAS TBLCO T AH TWC Address A16-0 TCPH T CP CE T OES OE WE T DS DQ7-0 High Z Data Valid T OEH T DH Internal Write Starts - 13 - Publication Release Date: July 1999 Revision A12 W29EE011 Timing Waveforms, continued Page Write Cycle Timing Diagram TWC Address A16-0 DQ7-0 CE OE TWP WE Byte 0 T WPH TBLC TBLCO Byte 1 Byte 2 Byte N-1 Internal Write Start Byte N DATA Polling Timing Diagram Address A16-0 WE TCEP CE TOEH OE TOEP DQ7-0 X X T WC X X TOES - 14 - W29EE011 Timing Waveforms, continued Toggle Bit Timing Diagram Address A16-0 WE CE TOEH OE TOES DQ6 TWC Page Write Timing Diagram Software Data Protection Mode Three-byte sequence for software data protection mode Address A16-0 5555 2AAA 5555 Byte/page load cycle starts TWC DQ6 AA 55 A0 CE OE WE TWP TWPH TBLC TBLCO SW0 SW1 SW2 Byte 0 Byte N-1 Byte N (last byte) Internal write starts - 15 - Publication Release Date: July 1999 Revision A12 W29EE011 Timing Waveforms, continued Reset Software Data Protection Timing Diagram Six-byte sequence for resetting software data protection mode Address A16-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ7-0 CE AA 55 80 AA 55 20 OE WE TWP TWPH SW0 TBLC TBLCO SW1 SW2 SW3 SW4 SW5 Internal programming starts 5 Volt-only Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A16-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ7-0 AA 55 80 AA 55 10 CE OE WE TWP TWPH SW0 TBLC TBLCO SW1 SW2 SW3 SW4 SW5 Internal programming starts - 16 - W29EE011 ORDERING INFORMATION PART NO. W29EE011-90 W29EE011-15 W29EE011T-90 W29EE011T-15 W29EE011P-90 W29EE011P-15 W29EE01190B W29EE01115B W29EE011T90B W29EE011T15B W29EE011P90B W29EE011P15B ACCESS TIME (nS) 90 150 90 150 90 150 90 150 90 150 90 150 POWER SUPPLY CURRENT MAX. (mA) 50 50 50 50 50 50 50 50 50 50 50 50 STANDBY VDD CURRENT MAX. (µA) 100 100 100 100 100 100 100 100 100 100 100 100 PACKAGE 600 mil DIP 600 mil DIP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 600 mil DIP 600 mil DIP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC CYCLING 1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 17 - Publication Release Date: July 1999 Revision A12 W29EE011 PACKAGE DIMENSIONS 32-pin P-DIP Dimension in inches Dimension in mm Symbol Min. Nom. Max. 0.210 0.010 0.150 0.016 0.048 0.155 0.018 0.050 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15 Min. Nom. Max. 5.33 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 4.06 0.56 1.37 0.36 D 32 17 E1 A A1 A2 B B1 c D E E1 e1 L a 0.008 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130 41.91 42.16 14.99 15.24 13.84 2.29 3.05 0 16.51 15.49 13.97 14.10 2.54 3.30 2.79 3.56 15 17.02 2.16 1 16 eA S Notes: E c 0.670 16.00 0.085 S A A2 L B B1 A1 Base Plane Seating Plane e1 a eA 1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1. include mold mismatch and are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec. 32-pin PLCC Dimension in Inches Dimension in mm Symbol HE E 4 1 32 30 Min. Nom. 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.51 0 0.410 0.590 0.49 0 0.090 Max. 0.140 Min. Nom. 0.50 Max. 3.56 5 29 GD D HD A A1 A2 b1 b c D E e GD GE HD HE L y θ Notes: 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.9 5 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0° 10° 0° 10° 13 21 14 20 c L A2 A 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc. θ Seating Plane e b b1 GE A1 y - 18 - W29EE011 Package Dimensions, continued 32-pin TSOP HD Symbol Dimension in Inches Min. Nom. Max. 0.047 0.002 0.037 0.007 0.005 0.720 0.311 0.780 Dimension in mm Min. Nom. Max. 1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20 D c A A1 A2 __ __ __ 0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031 0.006 0.041 0.009 0.007 0.728 0.319 0.795 __ 0.05 0.95 0.17 0.12 18.30 7.90 19.80 __ __ 1.00 0.20 0.15 18.40 8.00 20.00 0.50 0.50 0.80 M e E b c D 0.10(0.004) b E HD e L L A A2 θ L L1 A1 1 __ 0.016 __ 0.024 __ 0.40 __ 0.60 __ 0.000 1 __ 0.004 5 __ 0.00 1 __ 0.10 5 Y __ 3 __ 3 θ Y Note: Controlling dimension: Millimeters - 19 - Publication Release Date: July 1999 Revision A12 W29EE011 VERSION HISTORY VERSION A9 DATE Feb. 1998 PAGE 6 7 8 1, 17 A10 A11 A12 Jun. 1998 Aug. 1998 Jul. 1999 1, 10, 11, 12, 17 1, 2, 17, 19 1, 17 1, 11, 12, 17 1, 17, 18 Add pause 10 mS Add pause 50 mS Correct the time 10 mS to 10 µS Add cycing 100 item Add 70 nS bining Add TSOP package Change endurance cycles as 1K/10K Delete 70,120 nS bining Delete SOP package DESCRIPTION Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 20 -