W29GL256P
256M-BIT
3.0-VOLT PARALLEL FLASH MEMORY WITH
PAGE MODE
W29GL256P
Table of Contents
1
2
3
4
5
6
7
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES ................................................................................................................................. 1
PIN CONFIGURATION ............................................................................................................... 2
BLOCK DIAGRAM ...................................................................................................................... 3
PIN DESCRIPTION ..................................................................................................................... 3
ARRAY ARCHITECTURE........................................................................................................... 4
6.1
Sector Address Table ..................................................................................................... 4
FUNCTIONAL DESCRIPTION.................................................................................................... 5
7.1
Device Bus Operation ..................................................................................................... 5
7.2
Instruction Definitions...................................................................................................... 6
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
7.2.19
7.2.20
7.2.21
7.2.22
7.2.23
7.3
Enhanced Sector Protect/Un-protect ............................................................................ 16
7.3.1
7.3.2
7.4
Lock Register .................................................................................................................. 17
Individual (Non-Volatile) Protection Mode ....................................................................... 18
Security Sector Flash Memory Region ......................................................................... 21
7.4.1
7.4.2
7.5
7.6
Reading Array Data .......................................................................................................... 6
Page Mode Read .............................................................................................................. 7
Device Reset Operation .................................................................................................... 8
Standby Mode ................................................................................................................... 8
Output Disable Mode ........................................................................................................ 8
Write Operation ................................................................................................................. 8
Byte/Word Selection ......................................................................................................... 9
Automatic Programming of the Memory Array .................................................................. 9
Erasing the Memory Array .............................................................................................. 10
Erase Suspend/Resume ............................................................................................... 11
Sector Erase Resume ................................................................................................... 11
Program Suspend/Resume ........................................................................................... 12
Program Resume .......................................................................................................... 12
Write Buffer Programming Operation ............................................................................ 12
Buffer Write Abort ......................................................................................................... 13
Accelerated Programming Operation ............................................................................ 13
Automatic Select Bus Operation ................................................................................... 13
Automatic Select Operations......................................................................................... 14
Automatic Select Instruction Sequence ........................................................................ 14
Enhanced Variable IO (EVIO) Control .......................................................................... 15
Hardware Data Protection Options ............................................................................... 15
Inherent Data Protection ............................................................................................... 15
Power Supply Decoupling ............................................................................................. 15
Factory Locked: Security Sector Programmed and Protected at factory ......................... 21
Customer Lockable: Security Sector Not Programmed or Protected .............................. 21
Instruction Definition Tables ......................................................................................... 22
Common Flash Memory Interface (CFI) Mode ............................................................. 26
7.6.1
Query Instruction and Common Flash memory Interface (CFI) Mode ............................. 26
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ELECTRICAL CHARACTERISTICS ......................................................................................... 30
8.1
Absolute Maximum Stress Ratings ............................................................................... 30
8.2
Operating Temperature and Voltage ............................................................................ 30
8.3
DC Characteristics ........................................................................................................ 31
8.4
Switching Test Circuits.................................................................................................. 32
8.4.1
8.5
AC Characteristics ........................................................................................................ 33
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.6
10
11
Instruction Write Operation ............................................................................................. 34
Read / Reset Operation .................................................................................................. 35
Erase/Program Operation ............................................................................................... 37
Write Operation Status .................................................................................................... 46
WORD/BYTE CONFIGURATION (#BYTE)..................................................................... 50
DEEP POWER DOWN MODE........................................................................................ 52
WRITE BUFFER PROGRAM.......................................................................................... 52
Recommended Operating Conditions........................................................................... 53
8.6.1
9
Switching Test Waveform ............................................................................................... 32
At Device Power-up ........................................................................................................ 53
8.7
Erase and Programming Performance ......................................................................... 54
8.8
Data Retention .............................................................................................................. 54
8.9
Latch-up Characteristics ............................................................................................... 54
8.10 Pin Capacitance ............................................................................................................ 54
PACKAGE DIMENSIONS ......................................................................................................... 55
9.1
TSOP 56-pin 14x20mm ................................................................................................ 55
9.2
Low-Profile Fine-Pitch Ball Grid Array, 64-ball 11x13mm (LFBA64) ............................ 56
ORDERING INFORMATION..................................................................................................... 57
10.1 Ordering Part Number Definitions................................................................................. 57
10.2 Valid Part Numbers and Top Side Marking .................................................................. 58
HISTORY .................................................................................................................................. 59
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List of Figures
Figure 3-1
Figure 3-2
Figure 4-1
Figure 7-1
Figure 7-2
Figure 7-3
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 8-11
Figure 8-12
Figure 8-13
Figure 8-14
Figure 8-15
Figure 8-16
Figure 8-17
Figure 8-18
Figure 8-19
Figure 8-20
Figure 8-21
Figure 8-22
Figure 8-23
Figure 8-24
Figure 8-25
Figure 8-26
Figure 8-27
Figure 9-1
Figure 10-1
LFBGA64 TOP VIEW...................................................................................................... 2
56-PIN STANDARD TSOP (TOP VIEW) ........................................................................ 2
Block Diagram................................................................................................................. 3
Enhanced Sector Protect/Un-protect IPB Program Algorithm ...................................... 16
Lock Register Program Algorithm ................................................................................. 17
IPB Program Algorithm ................................................................................................. 19
Maximum Negative Overshoot ..................................................................................... 30
Maximum Positive Overshoot ....................................................................................... 30
Switch Test Circuit ........................................................................................................ 32
Switching Test Waveform ............................................................................................. 32
Instruction Write Operation Waveform.......................................................................... 34
Read Timing Waveform ................................................................................................ 35
#RESET Timing Waveform ........................................................................................... 36
Automatic Chip Erase Timing Waveform ...................................................................... 37
Automatic Chip Erase Algorithm Flowchart .................................................................. 38
Automatic Sector Erase Timing Waveform ................................................................... 39
Automatic Sector Erase Algorithm Flowchart ............................................................... 40
Erase Suspend/Resume Flowchart .............................................................................. 41
Automatic Program Timing Waveform .......................................................................... 42
Accelerated Program Timing Waveform ....................................................................... 42
CE# Controlled Write Timing Waveform ....................................................................... 43
Automatic Programming Algorithm Flowchart .............................................................. 44
Silicon ID Read Timing Waveform ................................................................................ 45
Data# Polling Timing Waveform (During Automatic Algorithms) .................................. 46
Status Polling for Word Programming/Erase ................................................................ 47
Status Polling for Write Buffer Program Flowchart ....................................................... 48
Toggling Bit Timing Waveform (During Automatic Algorithms) .................................... 49
Toggle Bit Algorithm...................................................................................................... 50
#BYTE Timing Waveform For Read operations ........................................................... 51
Page Read Timing Waveform ....................................................................................... 51
Deep Power Down mode Waveform ............................................................................ 52
Write Buffer Program Flowchart ................................................................................... 52
AC Timing at Device Power-Up Reference to #RESET ............................................... 53
TSOP 56-pin 14x20mm ................................................................................................ 55
Ordering Part Numbering .............................................................................................. 57
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List of Tables
Table 5-1
Table 6-1
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Table 7-16
Table 7-17
Table 7-18
Table 7-19
Table 7-20
Table 7-21
Table 7-22
Table 8-1
Table 8-2
Table 8-3
Table 8-4
Table 8-5
Table 8-6
Table 8-7
Table 8-8
Table 8-9
Table 8-10
Table 8-11
Table 8-12
Table 8-13
Table 10-1
Table 11-1
Pin Description ................................................................................................................ 3
Sector Address ............................................................................................................... 4
Device Bus Operation ..................................................................................................... 5
Device Bus Operation (continue) .................................................................................... 5
Polling During Embedded Program Operation ............................................................... 9
Polling During Embedded Sector Erase Operation ...................................................... 10
Polling During Embedded Chip Erase Operation ......................................................... 11
Polling During Embedded Erase Suspend ................................................................... 11
Polling During Embedded Program Suspend ............................................................... 12
Polling Buffer Write Abort Flag ..................................................................................... 13
Auto Select for MFR/Device ID/Secure Silicon/Sector Protect Read ........................... 14
Lock Register Bits ......................................................................................................... 17
Sector Protection Status Table ..................................................................................... 20
Factory Locked: Security Sector ................................................................................... 21
ID Reads, Sector Verify, and Security Sector Entry/Exit .............................................. 22
Program, Write Buffer, CFI, Erase and Suspend ......................................................... 23
Deep Power Down ........................................................................................................ 23
Lock Register and Global Non-Volatile ......................................................................... 24
IPB Functions............................................................................................................... 24
Volatile DPB Functions ................................................................................................. 25
CFI Mode: ID Data Values ............................................................................................ 26
CFI Mode: System Interface Data Values .................................................................... 27
CFI Mode: Device Geometry Data Values.................................................................... 28
CFI mode: Primary Vendor-Specific Extended Query Data Values ............................. 29
Absolute Maximum Stress Ratings ............................................................................... 30
Operating Temperature and Voltage ............................................................................ 30
DC Characteristics ........................................................................................................ 31
Test Specification.......................................................................................................... 32
AC Characteristics ........................................................................................................ 34
AC Characteristics #RESET and RY/#BY .................................................................... 35
AC Characteristics Word/Byte Configuration (#BYTE) ................................................. 50
AC Characteristics for Deep Power Down .................................................................... 52
AC Characteristics at Device Power Up ....................................................................... 53
AC Characteristics for Erase and Programming Performance ..................................... 54
Data Retention .............................................................................................................. 54
Latch-up Characteristics ............................................................................................... 54
Pin Capacitance ............................................................................................................ 54
Valid Part Numbers and Markings ................................................................................ 58
Revision History ............................................................................................................ 59
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W29GL256P
GENERAL DESCRIPTION
The W29GL256P Parallel Flash memory provides a storage solution for embedded system applications
that require better performance, lower power consumption and higher density. The device has a random
access speed of 90ns and a fast page access speed of 25ns, as well as significantly faster program and
erase time than the products available on the market today. The W29GL256P also offers special
features such as Compatible Manufacturer ID that makes the device industry standard compatible
without the need to change firmware.
1
FEATURES
64k-Word/128k-Byte uniform sector
architecture
– Total 256 uniform sectors
Deep power down mode
Industrial temperature range
Faster Erase and Program time
– Erase is 1.5x faster than industry
standard
– Program is 2x faster than industry
standard
– Allows for improved production
throughput and faster field updates
32-Word/64-Byte write buffer
– Reduces total program time for
multiple-word updates
8-Word/16-Byte page read buffer
Secured Silicon Sector area
– Programmed and locked by the
customer or during production
– 128-word/256-byte sector for
permanent, safe identification using an
8-word/16-byte random electronic
serial number
CFI (Common Flash Interface) support
Single 3V Read/Program/Erase (2.7 3.6V)
Enhanced Variable IO control
– All input levels (address, control, and
DQ) and output levels are determined
by voltage on the EVIO input. EVIO
ranges from 1.65 to VCC
Enhanced Sector Protect using
Dynamic and Individual mechanisms
Polling/Toggling methods are used to
detect the status of program and erase
operation
#WP/ACC Input
– Accelerates programming time (when
VHH is applied) for greater throughput
during system production
– Protects first or last sector regardless
of sector protection settings
Suspend and resume commands used
for program and erase operations
More than 100,000 erase/program
cycles
Hardware reset input (#RESET) resets
device
More than 20-year data retention
Software and Hardware write
protection
– Write-Protect all or a portion of
memory
– Enable/Disable protection with #WP
pin
– Top or bottom array protection
Ready/#Busy output (RY/#BY) detects
completion of program or erase cycle
Packages
– 56-pin TSOP
– 64-ball LFBGA
Low power consumption
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W29GL256P
2
PIN CONFIGURATION
Figure 2-1
Figure 2-2
LFBGA64 TOP VIEW
56-PIN STANDARD TSOP (TOP VIEW)
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W29GL256P
3 BLOCK DIAGRAM
Figure 3-1
Block Diagram
4 PIN DESCRIPTION
SYMBOL
PIN NAME
A0-A23
Address Inputs
DQ0-DQ14 Data Inputs/Outputs
DQ15/A-1 Word mode DQ15 is Data Input/Output
Byte mode A-1 is Address Input
#CE
Chip Enable
#OE
Output Enable
#WE
Write Enable
#WP/ACC Hardware Write Protect/ Acceleration Pin
#BYTE
Byte Enable
#RESET
Hardware Reset
RY/#BY
Ready/Busy Status
VCC
Power Supply
EVIO
Enhanced Variable IO Supply
VSS
Ground
NC
No Connection
Table 4-1
Pin Description
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W29GL256P
5
5.1
ARRAY ARCHITECTURE
Sector Address Table
Sector Address
Sector Size
A23-A16
(KByte/KWord)
SA00
0000000
128/64
SA01
0000001
128/64
.
.
.
.
.
.
.
.
.
SA254
11111110
128/64
SA255
11111111
128/64
Table 5-1
Sector Address
X8
Start / Finish
000000h
01FFFFh
020000h
03FFFFh
.
.
.
.
.
.
1FC0000h 1FDFFFFh
1FE0000h 1FFFFFFh
Sector
X16
Start / Finish
000000h 00FFFFh
010000h 01FFFFh
.
.
.
.
.
.
FE0000h FEFFFFh
FF0000h FFFFFFh
Note: The address range [A23:A-1] in byte mode (#BYTE = VIL) or [A23:A0] in word mode (#BYTE = VIH)
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6
FUNCTIONAL DESCRIPTION
6.1
Device Bus Operation
Mode Select #Reset
#CE
#WE #OE Address
Device
L
X
X
Reset
Standby
VCC±0.3V VCC±0.3V X
Mode
Output
H
L
H
Disable
Read Mode
H
L
H
Write
H
L
L
Accelerated
H
L
L
Program
Table 6-1
Device Bus Operation
Notes:
1.
2.
3.
4.
(4)
Data I/O
DQ[7:0]
X
X
High-Z
X
X
High-Z
H
X
High-Z
L
H
AIN
AIN
DOUT
DIN
H
AIN
DIN
#BYTE
VIH #WP/ACC
VIL
Data I/O DQ[15:8]
HighHigh-Z
L/H
Z
HighHigh-Z
H
Z
HighHigh-Z
L/H
Z
DOUT
L/H
DQ[14:8]=HighDIN Note(1,2)
Z
DQ15=A-1
DIN
VHH
The first or last sector was protected if #WP/ACC=VIL.
When #WP/ACC = VIH, the protection conditions of the outmost sector depends on previous protection conditions.
Refer to the enhanced protect feature.
DQ[15:0] are input (DIN) or output (DOUT) pins according to the requests of instruction sequence, sector protection,
or data polling algorithm.
In Word Mode (Byte#=VIH), the addresses are A23 to A0. In Byte Mode (Byte#=VIL), the addresses are A23 to A-1
(DQ15),.
Description
Control Inputs A23
#CE #WE #OE ~12
A11
~10
A9
A8
A5
A6
~7
~4
DQ[15:8]
A3
DQ
A1 A0
~2
[7:0] BYTE WORD
L
H
L
X
X
VHH
X
L
X
L
L
L
EF
X
00
Cycle 1
L
H
L
X
X
VHH
X
L
X
L
L
H
7E
X
22
Cycle 2
L
H
L
X
X
VHH
X
L
X
H
H
L
22
X
22
Cycle 3
L
H
L
X
X
VHH
X
L
X
H
H
H
01
X
22
Sector Lock Status
Verification(1)
L
H
L
SA
X
VHH
X
L
X
L
H
L 01/00
X
X
Secure Sector (H) (2)
L
H
L
X
X
VHH
X
L
X
L
H
H 99/19
X
X
Secure Sector (L) (2)
L
H
L
X
X
VHH
X
L
X
L
H
H 89/09
X
X
Device ID
Read Silicon ID
Manufacturer Code
Table 6-2
Notes:
1.
2.
Device Bus Operation (continue)
Sector unprotected code:00h. Sector protected code:01h.
Factory locked code: #WP protects high address sector: 99h. #WP protects low address sector: 89h. Factory unlocked
code: #WP protects high address sector: 19h. #WP protects low address sector: 09h
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W29GL256P
6.2
Instruction Definitions
The device operation can be initiated by writing specific address and data commands or sequences into
the instruction register. The device will be reset to reading array data when writing incorrect address
and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
waveforms.
6.2.1
Reading Array Data
The default state after power up or a reset operation is the Read mode.
To execute a read operation, the chip is enabled by setting #CE and #OE active and #WE high. At the
same time, the required address or status register location is provided on the address lines. The system
reads the addressed location contents on the Data IO pins after the tCE and tOE timing requirements
have been met. Output data will not be accessible on the Data IO pins if either the device or it’s outputs
are not enabled by #CE or #OE being High, and the outputs will remain in a tri-state condition.
When the device completes an embedded memory operation (i.e., Program, automatic Chip Erase or
Sector Erase) successfully, it will return to the Read mode and from any address in the memory array
the data can be read. However, If the embedded operation fails to complete, by verifying the status
register bit DQ5 (exceeds time limit flag) going high during the operations, at this time system should
execute a Reset operation causing the device to return to Read mode.
Some operating states require a reset operation to return to Read mode such as:
Time-out condition during a program or erase failed condition, indicated by the status register
bit DQ5 going High during the operation. Failure during either of these states will prevent the
device from automatically returning to Read mode.
During device Auto Select mode or CFI mode, a reset operation is required to terminate their
operation.
In the above two situations, the device will not return to the Read mode unless a reset operation is
executed (either hardware reset or software reset instruction) or the system will not be able to read array
data.
The device will enter Erase-Suspended Read mode if the device receives an Erase Suspend instruction
while in the Sector Erase state. The erase operation will pause (after a time delay not exceeding 20µs)
prior to entering Erase-Suspend Read mode. At this time data can be programmed or read from any
sector that is not being erased. Another way to verify device status is to read the addresses inside the
sectors being erased. This will only provide the contents of the status register.
Program operation during Erase-Suspend Read mode of valid sector(s) will automatically return to the
Erase-Suspend Read mode upon successful completion of the program operation.
An Erase Resume instruction must be executed to exit the Erase-Suspended Read mode, at which time
suspended erase operations will resume. Erase operation will resume where it left off and continue until
successful completion unless another Erase Suspend instruction is received.
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W29GL256P
6.2.2
Page Mode Read
The Page Mode Read has page sizes of 16 bytes or 8 words. The higher addresses A[23:3] accesses
the desired page. To access a particular word or byte in a page, it is selected by A[2:0] for word mode
and A[2:0,A-1] for byte mode. Page mode can be turned on by keeping “page-read address” constant
and changing the “intra-read page” addresses. The page access time is tAA or tCE, followed by tPA for
the page read time. When #CE toggles, access time is tAA or tCE.
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6.2.3
Device Reset Operation
Pulling the #RESET pin Low for a period equal to or greater than tRP will return the device to Read mode.
If the device is performing a program or erase operation, the reset operation will take at most a period
of tREADY1 before the device returns to Read mode. The RY/#BY pin will remain Low (Busy Status) until
the device returns to Read mode.
Note, the device draws larger current if the #RESET pin is held at voltages greater that GND+0.3V and
less than or equal to VIL. When the #RESET pin is held a GND±0.3V, the device only consumes Reset
(ICC5) current.
It is recommended to tie the system reset signal to the #RESET pin of the flash memory. This allows
the device to be reset with the system and puts it in a state where the system can immediately begin
reading boot code from it.
Executing the Reset instruction will reset the device back to the Read mode in the following situations:
During an erase instruction sequence, before the full instruction set is completed.
Sector erase time-out period
Erase failed, while DQ5 is High.
During program instruction sequence, before the full instruction set is completed, including the
erase-suspended program instruction.
Program failed, while DQ5 is High as well as the erase-suspended program failure.
Auto-select mode
CFI mode
The user must issue a reset instruction to reset the device back to the Read mode when the
device is in Auto-Select mode or CFI mode, or when there is a program or erase failure (DQ5
is High).
When the device is performing a Programming (not program fail) or Erasing (Not erase fail)
function, the device will ignore reset commands.
6.2.4
Standby Mode
Standby mode is entered when both #RESET and #CE are driven to VCC ±300mV (inactive state). At
this time output pins are placed in the high impedance state regardless of the state of the #WE or #OE
pins and the device will draw minimal standby current (ICC4). If the device is deselected during erase or
program operation, the device will draw active current until the operation is completed.
6.2.5
Output Disable Mode
The #OE pin controls the state of the Data IO pins. If #OE is driven High (VIH), all Data IO pins will
remain at high impedance and if driven Low, the Data IO pins will drive data ( #OE has no affect on the
RY/BY# output pin).
6.2.6
Write Operation
To execute a write operation, Chip Enable (#CE) pin is driven Low and the Output Enable (#OE) is
pulled high to disable the Data IO pins to a high impedance state. The desired address and data should
be present on the appropriate pins. Addresses are latched on the falling edge of either #WE or #CE and
Data is latched on the rising edge or either #CE or #WE. To see an example, please refer to timing
diagrams in Figure 8-5 and Figure 8-15. If an invalid write instruction, not defined in this datasheet is
written to the device, it may put the device in an undefined state.
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W29GL256P
6.2.7
Byte/Word Selection
To choose between the Byte or Word mode, the #BYTE input pin is used to select how the data is
input/output on the Data IO pins and the organization of the array data. If the #BYTE pin is driven High,
Word mode will be selected and all 16 Data IO pins will be active. If the #BYTE is pulled Low, Byte mode
will be active and only Data IO DQ[7:0] will be active. The remaining Data IO pins (DQ[14:8]) will be in
a high impedance state and DQ15 becomes the A-1 address input pin.
6.2.8
Automatic Programming of the Memory Array
To program the memory array in Byte or Word mode, refer to the Instruction Definition Tables for correct
cycle defined instructions that include the 2 unlocking instruction cycles, the A0h program cycle
instruction and subsequent cycles containing the specified address location and the byte or word desired
data content, followed by the start of the embedded algorithm to automatically program the array.
Once the program instruction sequence has been executed, the internal state machine commences
execution of the algorithms and timing necessary for programming and cell verification. Included in this
operation is generating suitable program pulses, checking cell threshold voltage (VT) margins, and if any
cells do not pass verification or have acceptable margins, repetitive program pulse sequence will be
cycled again. The internal process mechanisms will protect cells that do pass margin and verification
tests from being over-programmed by prohibiting further program pulses to passing cells as failing cells
continue to be run through the internal programming sequence until the pass.
This feature allows the user to only perform the auto-programming sequence once and the device state
machine takes care of the program and verification process.
Array bits during programming can only change a bit status of “1” (erase state) to a “0” (programmed
state). It is not possible to do the reverse with a programming operation. This can only be done by first
performing an erase operation. Keep in mind, the internal write verification only checks and detects
errors in cases where a “1” is not successfully programmed to “0”.
During the embedded programming algorithm process any commands written to the device will be
ignored, except hardware reset or a program suspend instruction. Hardware reset will terminate the
program operation after a period of time, not to exceed 10µs. If in the case a Program Suspend was
executed, the device will enter the program suspend read mode. When the embedded program
algorithm is completed or the program is terminated by a hardware reset, the device will return to Read
mode.
The user can check for completion by reading the following bits in the status register, once the
embedded program operation has started:
Status
DQ7
DQ6
DQ5
In progress
DQ7#
Toggling
0
Exceeded time
DQ7#
Toggling
1
limit
Table 6-3
Polling During Embedded Program Operation
Note:
1.
DQ1
0
N/A
RY/#BY1
0
0
RY/#BY is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
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W29GL256P
6.2.9
Erasing the Memory Array
Sector Erase and Chip Erase are the two possible types of erase operations executed on the memory
array. Sector Erase operation erases one or more selected sectors and this can be simultaneous. Chip
Erase operation erases the entire memory array, except for any protected sectors.
6.2.9.1
Sector Erase
The sector erase operation returns all selected sectors in memory to the “1” state, effectively clearing
all data. This action requires six instruction cycles to commence the erase operation. The unlock
sequence is the first two cycles, followed by the configuration cycle, the fourth and fifth are also ”unlock
cycles”, and the Sector Erase instruction is the sixth cycle. An internal 50µs time-out counter is started
once the sector erase instruction sequence has been completed. During this time, additional sector
addresses and Sector Erase commands may be issued, thus allowing for multiple sectors to be selected
and erased simultaneously. Once the 50µs time-out counter has reached its limit, no additional
command instructions will be accepted and the embedded sector erase algorithm will commence.
Note, that the 50µs time-out counter restarts after every sector erase instruction sequence. The device
will abort and return to Read mode, if any instruction other than Sector Erase or Erase Suspend is
attempted during the time-out period.
Once the embedded sector erase algorithm begins, all instructions except Erase Suspend or Hardware
Reset will be ignored. The hardware reset will abort the erase operation and return the device to the
Read mode.
The embedded sector erase algorithm status can be verified by the following:
Status
DQ7
DQ6
DQ5
DQ31
Time-out period
0
Toggling
0
0
In progress
0
Toggling
0
1
Exceeded time limit
0
Toggling
1
1
Table 6-4
Polling During Embedded Sector Erase Operation
Note:
1.
2.
3.
4.
DQ2
Toggling
Toggling
Toggling
RY/#BY2
0
0
0
The DQ3 status bit is the 50µs time-out indicator. When DQ3=0, the 50µs time-out counter has not yet reached zero
and the new Sector Erase instruction maybe issued to specify the address of another sector to be erased. When DQ3=1,
the 50µs time-out counter has expired and the Sector Erase operation has already begun. Erase Suspend is the only
valid instruction that maybe issued once the embedded erase operation is underway.
RY/#BY is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
When an attempt is made to erase only protected sector(s), the erase operation will abort thus preventing any data
changes in the protected sector(s). DQ7 will output “0” and DQ6 will toggle briefly (100µs or less) before aborting and
returning the device to Read mode. If unprotected sectors are also specified, however, they will be erased normally and
the protected sector(s) will remain unchanged.
DQ2 is a localized indicator showing a specified sector is undergoing erase operation or not. DQ2 toggles when user
reads at the addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend
mode).
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6.2.9.2
Chip Erase
The Chip Erase operation returns all memory locations containing a bit state of “0” to the “1” state,
effectively clearing all data. This action requires six instruction cycles to commence the erase operation.
The unlock sequence is the first two cycles, followed by the configuration cycle, the fourth and fifth are
also ”unlock cycles”, and the sixth cycle initiates the chip erase operation.
Once the chip erase algorithm begins, no other instruction will be accepted. However, if a hardware
reset is executed or the operating voltage is below acceptable levels, the chip erase operation will be
terminated and automatically returns to Read mode.
The embedded chip erase algorithm status can be verified by the following:
Status
DQ7
DQ6
DQ5
In progress
0
Toggling
0
Exceeded time limit
0
Toggling
1
Table 6-5
Polling During Embedded Chip Erase Operation
Note:
1.
6.2.10
DQ2
Toggling
Toggling
RY/#BY1
0
0
RY/#BY is an open drain pin and should be connected to VCC through a high value pull-up resistor.
Erase Suspend/Resume
If there is a sector erase operation in progress, an Erase Suspend instruction is the only valid instruction
that may be issued. Once the Erase Suspend instruction is executed during the 50µs time-out period
following a Sector Erase instruction, the time-out period will terminate right away and the device will
enter Erase-Suspend Read mode. If an Erase Suspend instruction is executed after the sector erase
operation has started, the device will not enter Erase-Suspended Read mode until approximately 20µs
(5µs typical) time has elapsed. To determine the device has entered the Erase-Suspend Read mode,
use DQ6, DQ7 and RY/#BY status to verify the state of the device.
Once the device has entered Erase-Suspended Read mode, it is possible to read or program any
sector(s) except those being erased by the erase operation. Only the contents of the status register is
present when attempting to read a sector that has been scheduled to erase or be programmed when in
the suspend mode. A resume instruction must be executed and recommend checking DQ6 toggle bit
status, before issuing another erase instruction.
The status register bits can be verified to determine the current status of the device:
Status
DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/#BY
Erase suspend read in erase suspended sector
1 No toggle 0 N/A Toggle N/A
1
Erase suspend read in non-erase suspended sector
Data Data Data Data Data Data
1
Erase suspend program in non-erase suspended sector DQ7# Toggle 0 N/A N/A N/A
0
Table 6-6
Polling During Embedded Erase Suspend
Instruction sets such as read silicon ID, sector protect verify, program, CFI query and erase resume can
also be executed during Erase-Suspend mode, except sector and chip erase.
6.2.11 Sector Erase Resume
Only in the Erase-Suspended Read mode can the Sector Erase Resume instruction be a valid command.
Once erase resumes, another Erase Suspend instruction can be executed, but allow a 400µs interval
between Erase Resume and the next Erase Suspend instruction.
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6.2.12 Program Suspend/Resume
Once a program operation is in progress, a Program Suspend is the only valid instruction that maybe
executed. Verifying if the device has entered the Program-Suspend Read mode after executing the
Program-Suspend instruction, can be done by checking the RY/#BY and DQ6. Programming should
halt within 15µs maximum (5µs typical).
Any sector(s) can be read except those being program suspended. Trying to read a sector being
program suspended is invalid. Before another program operation can be executed, a Resume instruction
must be performed and DQ6 toggling bit status has to be verified. Use the status register bits shown in
the following table to determine the current state of the device:
Status
DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/#BY
Program suspend read in program suspended sector
Invalid
1
Program suspend read in non-program suspended sector Data Data Data Data Data Data
1
Table 6-7
Polling During Embedded Program Suspend
Instruction sets such as read silicon ID, sector protect verify, program, CFI query can also be executed
during Program/Erase-Suspend mode.
6.2.13 Program Resume
The program Resume instruction is valid only when the device is in Program-Suspended mode. Once
the program resumes, another Program Suspend instruction can be executed. Insure there is at least a
5µs interval between Program Resume and the next Suspend instruction.
6.2.14 Write Buffer Programming Operation
Write Buffer Programming Operation, programs 64bytes or 32words in a two step programming
operation. To begin execution of the Write Buffer Programming, start with the first two unlock cycles, the
third cycle writes the programming Sector Address destination followed by the Write Buffer Load
Instruction (25h). The fourth cycle repeats the Sector Address, while the write data is the number of
intended word locations to be written minus one. (Example, if the number of word locations to be written
is 9, then the value would be 8h.) The 5th cycle is the first starting address/data set. This will be the first
pair to be programmed and consequentially, sets the “write-buffer-page” address. Repeat Cycle 5 format
for each additional address/data sets to be written to the buffer. Keep in mind all sets must remain
within the write buffer page address range. If not, operation will ABORT.
The “write-buffer-page” is selected by choosing address A[23:5].
The second step will be to program the contents of the write buffer page. This is done with one cycle,
containing the sector address that was used in step one and the “Write to Buffer Program Confirm”
instruction (29h).
Standard suspend/resume commands can be used during the operation of the write-buffer. Also, once
the write buffer programming operation is finished, it’ll return to the normal READ mode.
Write buffer programming can be conducted in any sequence. However the CFI functions, autoselect,
Secured Silicon sector are not functional when program operation is in progress. Multiple write buffer
programming operations on the same write buffer address range without intervention erase is accessible.
Any bit in a write buffer address range cannot be programmed from 0 back to 1.
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6.2.15 Buffer Write Abort
Write Buffer Programming Sequence will ABORT, if the following condition takes place:
The word count minus one loaded is bigger than the page buffer size (32) during, “Number of
Locations to Program.”
Sector Address written is not the same as the one specified during the Write-Buffer-Load
instruction.
If the Address/Data set is not inside the Write Buffer Page range which was set during cycle 5’s
first initial write-buffer-page select address/data set.
No “Program Confirm Instruction” after the assigned number of “data load” cycles.
After Write Buffer Abort, the status register will be DQ1=1, DQ7 = DATA# (last address loaded),
DQ6=toggle, DQ5=0. This status represents a Write Buffer Programming Operation was ABORTED. A
Write-to-Buffer-Abort Reset instruction sequence has to be written to reset the device back to the read
array mode.
DQ1 is the bit for Buffer Write Abort. When DQ1=1, the device will abort from buffer write operation and
go back to read status register shown in the following table:
Status
DQ7
Buffer Write Busy
DQ7#
Buffer Write Abort
DQ7#
Buffer Write Exceeded Time Limit
DQ7#
Table 6-8
Polling Buffer Write Abort Flag
DQ6
Toggle
Toggle
Toggle
DQ5
0
0
1
DQ3
N/A
N/A
N/A
DQ2
N/A
N/A
N/A
DQ1
0
1
0
RY/#BY
0
0
0
6.2.16 Accelerated Programming Operation
The device will enter the Accelerated Programming mode by applying high voltage (VHH) to the
#WP/ACC pin. Accelerated Programming mode allows the system to skip the normal unlock sequences
instruction and program byte/word locations directly. The current drawn from the #WP/ACC pin during
accelerated programming is no more that IACC1. Important Note: Do not exceed 10 accelerated
programs per sector. (#WP/ACC should not be held at VHH for any other function except for
programming or damage to the device may occur.)
6.2.17 Automatic Select Bus Operation
There are basically two methods to access Automatic Selection Operations; Automatic Select
Instructions through software commands and High Voltage applied to A9. See Automatic Select
Instruction Sequence later on in this section for details of equivalent instruction operations that do not
require the use of VHH. The following five bus operations require A9 to be raised to VHH.
6.2.17.1
Sector Lock Status Verification
To verify the protected state of any sector using bus operations, execute a Read Operation with VHH
applied to A9, the sector address present on address pins A[23:12], address pins A6, A3, A2, and A0
held Low, and address pins A1 held High. If DQ0 is Low, the sector is considered not protected, and if
DQ0 is High, the sector is considered to be protected.
6.2.17.2
Read Silicon Manufacturer ID Code
Winbond’s 29GL-P/29GL-S families of Parallel Flash memories feature an Industry Standard compatible
Manufacturer ID code of EFh. To verify the Silicon Manufacturer ID code, execute a Read Operation
with VHH applied to the A9 pin and address pins A6, A3, A2, A1 and A0 are held Low. The ID code can
then be read on data bits DQ[7:0].
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6.2.17.3
Read Silicon Device ID Code
To verify the Silicon Device ID Codes, execute a Read Operation with VHH applied to the A9 pin and
address pins A6, A3, A2, A1, and A0 have several bit combinations to return the Winbond Device ID
codes of 7Eh, 22h or 01h, which is shown on the data bits DQ[7:0]. See Table 7-2.
6.2.17.4
Read Indicator Bit DQ7 for Security Sector High and Low Address
To verify that the Security Sector has been factory locked, execute a Read Operation with VHH applied
to A9, address pins A6, A3, and A2 are held Low, and address pins A1 and A0 are held High. If the
Security Sector has been factory locked, the code 99h(Highest Address Sector) or 89h(Lowest Address
Sector) will be shown on the data bits DQ[7:0]. Otherwise, the factory unlocked code of 19h(H)/09(L)
will be shown.
6.2.18 Automatic Select Operations
The Automatic Select instruction show in Table 7-13 can be executed if the device is in one of the
following modes; Read, Program Suspended, Erase-Suspended Read, or CFI. At which time the user
can issue (two unlock cycles followed by the Automatic Select instruction 90h) to enter Automatic Select
mode. Once in the Automatic Select mode, the user can query the Manufacturer ID, Device ID, Security
Sector locked status, or Sector protected status multiple times without executing the unlock cycles and
a Automatic Select instruction (90h) again.
Once in Automatic Select mode, executing a Reset instruction (F0h) will return the device back to the
valid mode from which it left when the Automatic Select mode was first executed.
Another way previously mentioned to enter Automatic Select mode is to use one of the bus operation
shown Table 7-2 in Device Bus Operation. Once the high voltage (VHH) is removed from the A9 pin, the
device will return back to the valid mode from which it left when the Automatic Select mode was first
executed.
6.2.19
Automatic Select Instruction Sequence
Accessing the manufacturer ID, device ID, and verifying whether or not secured silicon is locked and
whether or not a sector protected is the purpose of Automatic Select mode. There are four instruction
cycles that comprise the Automatic Select mode. The first two cycles are write unlock commands,
followed by the Automatic Select instruction (90h). The fourth cycle is a read cycle, and the user may
read at any address any number of times without entering another instruction sequence. To exit the
Automatic Select mode and back to read array, the Reset instruction is necessary. No other instructions
are allowed except the Reset Instruction once Automatic Select mode has been selected. Refer to the
following table for more detailed information.
Address
X00
X00
X01/0E/0F
X02/1C/1E
Data (hex)
Representation
Word
EF
Manufacturer ID
Byte
EF
Word
227E/2222/2201
Device ID W29GL256P
Byte
7E/22/01
99/19(H)
Word
X03
Factory locked/unlocked
89//09(L)
Secure Silicon
99/19(H)
Byte
X06
Factory locked/unlocked
89/09(L)
Word (Sector address) X02
00/01
Unprotected/protected
Sector Protect Verify
Byte Sector address) X04
00/01
Unprotected/protected
Table 6-9
Auto Select for MFR/Device ID/Secure Silicon/Sector Protect Read
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6.2.20
Enhanced Variable IO (EVIO) Control
The Enhanced Variable IO (EVIO) control allows the host system to set the voltage levels that the device
generates and tolerates on all inputs and outputs (address, control, and DQ signals). EVIO range is 1.65
to VCC.
For example, a EVIO of 1.65-3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving
signals to and from other 1.8 or 3 V devices on the same data bus.
6.2.21 Hardware Data Protection Options
Hardware Data Protection is the second of the two main sector protections offered by the W29GL256.
6.2.21.1
#WP/ACC Option
By setting the #WP/ACC pin to VIL, the highest or lowest sector (device specific) is protected from all
erase/program operations. If #WP/ACC is set High, the highest and Lowest sector revert back to the
previous protected/unprotected state.
Note: The max input load current can increase, if #WP/ACC pin is at VIH when the device is put into
standby mode.
6.2.21.2
VCC Write Protect
This device will not accept any write instructions when VCC is less that VWPT (VCC Write Protect
Threshold). This prevents data from inadvertently being altered during power-up, power-down, a
temporary power loss or to the low level of VCC. If VCC is lower that VWPT, the device automatically
resets itself and will ignore write cycles until VCC is greater than VWPT. Once VCC rises above VWPT,
insure that the proper signals are on the control pins to avoid unexpected program or erase operations.
6.2.21.3
Write Pulse “Glitch” Protection
Pulses less than 5ns are viewed as glitches for control signals #CE, #WE, and #OE and will not be
considered for valid write cycles.
6.2.21.4
Power-up Write Inhibit
The device ignores the first instruction on the rising edge of #WE, if upon powering up the device, #WE
and #CE are set at VIL and #OE is set at VIH.
6.2.21.5
Logical Inhibit
A write cycle is ignored when either #CE is at VIH, #WE is at VIH, or #OE is at VIL. A valid write cycle
requires both #CE and #WE are at VIL with #OE at VIH.
6.2.22 Inherent Data Protection
The device built-in mechanism will reset to Read mode during power up to avoid accidental erasure or
programming.
6.2.22.1
Instruction Completion
Invalid instruction sets will result in the memory returning to read mode. Only upon a successful
completion of a valid instruction set will the device begin its erase or program operation..
6.2.22.2
Power-up Sequence
The device is placed in Read mode, during power-up sequence.
6.2.23 Power Supply Decoupling
To reduce noise effects, a 0.1µF capacitor is recommended to be connected between VCC and GND.
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6.3
Enhanced Sector Protect/Un-protect
This device is set from the factory in the Individual Protection mode of the Enhanced Sector Protect
scheme. The user can disable or enable the programming or erasing operation to any individual sector
or whole chip. The figure below helps describe an overview of these methods.
The device defaults to the Individual mode and all sectors are unprotected when shipped from the factory.
The following flow chart shows the detailed algorithm of Enhanced Sector Protect:
Start
Individual Protection
Mode
(Default)
IPB=0
Set IPB
Lock Bit
IPB lock Bit locked
All IPB not changeable
IPB=1
IPB Lock bit Unlocked
IPB is Changeable
Dynamic Write Protect bit
(DPB)
Sector Array
DPB=0 Sector Protect
DPB=1 Sector Unprotect
Figure 6-1
Individual Protect bit
(IPB)
IPB=0 Sector Protect
IPB=1 Sector Unprotect
DPB 0
SA 0
IPB 0
DPB 1
SA 1
IPB 1
DPB 2
SA 2
IPB 2
.
.
.
.
.
.
.
.
.
.
.
.
DPB + n
SA + n
IPB + n
Enhanced Sector Protect/Un-protect IPB Program Algorithm
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6.3.1
Lock Register
User can choose Secured Silicon Sector Protection Bit for security sector protection method via setting
the Lock Register bit, DQ0. Lock Register is a 16-bit one time programmable register. Once programmed
DQ0, will be locked in that mode permanently.
Once the Instruction Set Entry instruction sequence for the Lock Register Bits is issued, all sectors read
and write functions are disabled until Lock Register Exit sequence has been executed.
The memory sectors and extended memory sector protection is configured using the Lock Register.
Table 6-10
DQ[15:1]
Don’t Care
Lock Register Bits
DQ0
Secured Silicon Sector Protection Bit
Start
Write Data AAh, Address 555h
Lock Register instruction set entry
Write Data 55h, Address2AAh
Write Data 40h, Address 555h
Write Data A0h, Address don’t care
Lock Register data program
Write Program Data, Address don’t care
Data # Polling Algorithm
YES
Done
NO
NO
Pass
DQ5=1
YES
Exit lock Register instruction
Fail
Reset instruction
Figure 6-2
Lock Register Program Algorithm
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6.3.2
6.3.2.1
Individual (Non-Volatile) Protection Mode
Individual Protection Bits (IPB)
The Individual Protection Bit (IPB) is a nonvolatile bit, one bit per sector, with endurance equal to that
of the Flash memory array. Before erasing, IPB preprogramming and verification is managed by the
device, so no monitoring is necessary.
The Individual Protection Bits are set sector by sector by the IPB program instruction. Once a IPB is set
to “0”, the linked sector is protected, blocking any program and/or erase functions on that sector. The
IPB cannot be erased individually, but executing the “All IPB Erase” instruction will erase all IPB
simultaneously. Read and write functions are disabled when IPB programming is going on for all sectors
until this mode exits.
In case one of the protected sectors need to be unprotected, first, the IPB Lock Bit must be set to “1”
by performing one of the following: power-cycle the device or perform a hardware reset. Second, an “All
IPB Erase instruction needs to be performed. Third, Individual Protection Bits need to be set once again
to reflect the desired settings and finally, the IPB Lock Bit needs to be set once again which locks the
Individual Protection Bits and the device functions normally once again.
Executing an IPB Read instruction to the device is required to verify the programming state of the IPB
for any given sector. Refer to the IPB Program Algorithm flow chart below for details.
Note:
While IPB Lock Bit is set, Program and/or erase instructions will not be executed and times out
without programming and/or erasing the IPB.
For best protection results, it is recommended to execute the IPB Lock Bit Set instruction early
on in the boot code. Also, protect the boot code by holding WP#/ACC = VIL. Note that the IPB
and DPB bits perform the same when WP#/ACC = VHH, and when WP#/ACC =VIH.
While in the IPB command mode, read within that sector will bring the IPB status back for that
sector. All Read must be executed by the read mode.
Issuing the IPB Instruction Set Exit will reset the device to normal read mode enabling reads
and writes for the array.
6.3.2.2
Dynamic Protection Bits (DPB)
Dynamic Protection allows the software applications to easily protect sectors against unintentional
changes, although, the protection can be readily disabled when changes are needed.
All Dynamic Protection Bits (DPB) are individually linked to their associated sectors and these volatile
bits can be modified individually (set or cleared). The DPB provide protection schemes for only
unprotected sectors that have their associated IPB cleared. To change a DPB, the “DPB Instruction Set
Entry” must be executed first and then either the DPB Set (programmed to “0”) or DPB Clear (erased to
“1”) commands have to be executed. This places each sector in the protected or unprotected state
separately. To exit the DPB mode, execute the “DPB Instruction Set Exit” instruction.
Note:
When the parts are first shipped, the IPB are cleared (erased to “1”) and upon power up or reset,
the DPB can be set or cleared.
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IPB instruction set entry
Program IPB
Read DQ[7:0] twice
NO
DQ6=Toggle
?
YES
DQ5=1?
NO
Wait 500µs
YES
Read DQ[7:0] twice
NO
Read DQ[7:0] twice
DQ6=Toggle
?
YES
DQ0=
‘1’ (Erase) or
‘0’ (Program)
NO
YES
Pass
Program Fail Write Reset CMD
IPB instruction set Exit
Figure 6-3
Note:
1.
6.3.2.3
IPB Program Algorithm
IPB program/erase status polling flowchart: Check DQ6 toggle, when DQ6 stop toggle, the read status is 00h/01h (00h
for program and 01h for erase, otherwise the status is “fail’ and “exit”.
Individual Protection Bit Lock Bit
The Individual Protection Bit Lock Bit (IPBLK) is a global lock bit to control all IPB states. It is a singular
volatile bit. If the IPBLK is set (“0”), all IPB are locked and all sectors are protected or unprotected
according to their individual IPB. When IPBLK=1 (cleared), all IPB are unlocked and allowed to be set
or cleared.
To clear the IPB Lock Bit, a hardware reset or a power-up cycle must be executed.
.
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Sector Protection Status
Sector Status
DPB
IPBLK
IPB
clear
clear
clear
Unprotect, DPB and IPB are changeable
clear
clear
set
Protect, DPB and IPB are changeable
clear
set
clear
Unprotect, DPB is changeable
clear
set
set
Protect, DPB is changeable
set
clear
clear
Protect, DPB and IPB are changeable
set
clear
set
Protect, DPB and IPB are changeable
set
set
clear
Protect, DPB is changeable
set
set
set
Protect, DPB is changeable
Table 6-11
Sector Protection Status Table
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6.4
Security Sector Flash Memory Region
An extra memory space length of 128 words is used as the Security Sector Region which can be factory
locked or customer lockable. To enquire about the lock status of the device, the customer can issue a
Security Sector Protect Verify or Security Sector Factory Protect Verify using Automatic Select Address
03h and DQ7.
The security sector region is unprotected when shipped from factory and the security silicon indicator
bit (DQ7) is set to "0" for a customer lockable device. The security sector region is protected when
shipped from factory and the security silicon sector indicator bit is set to "1" for a factory-locked device.
6.4.1
Factory Locked: Security Sector Programmed and Protected at factory
In a factory locked device, the Security Sector is permanently locked prior to factory shipment The ESN
occupies addresses 00000h to 0000Fh in byte mode or 00000h to 00007h in word mode since the
device has a 16-byte (8-word) ESN(Electronic Serial Number) in the security region.
Security Silicon
Sector Address
Range
Standard Factory
Locked
000000h-000007h
ESN
000008h-00007Fh
Inaccessible
Table 6-12
6.4.2
Express Flash
Factory Locked
Customer Lockable
ESN or Determined by
Customer
Determined by
Customer
Determined by
Customer
Factory Locked: Security Sector
Customer Lockable: Security Sector Not Programmed or Protected
Important Notice; Once the security silicon sector is protected (Lock Register OTP DQ0 = “0”, Security
Sector indicator DQ7 bit=”0”), there is no way to unprotect the security silicon sector and the contents
of the memory region can no longer be programmed.
Once the security silicon is locked and verified, an Exit Security Sector Region instruction must be
executed to get back to the Read Array mode. A power cycle, or a hardware reset will also return the
device to read array mode.
This region can act as extra memory space when this security feature is not utilized. It is important to
note, the security sector region is a One Time Programmable (OTP) region. You can overwrite a WORD,
but you cannot change the state of a programmed cell.
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6.5
Instruction Definition Tables
1st Bus
Cycle
Instruction
2nd Bus
Cycle
3rd Bus
Cycle
ADD DATA ADD DATA ADD DATA
Read Mode
Silicon ID
Automatic Select
Data
BYTE
Data
Add
WORD XXX
Reset Mode
Device ID
Factory Protect
Verify
Sector Protect
Verify
Security Sector
Region
Exit Security Sector
Table 6-13
WORD Add
4th Bus Cycle
ADD
DATA
EF
5th Bus
Cycle
ADD DATA
6th Bus Cycle
ADD
DATA
F0
BYTE XXX
F0
WORD 555
AA
2AA
55
555
90
X00
BYTE AAA
AA
555
55
AAA
90
X00
EF
WORD 555
AA
2AA
55
555
90
X01
ID1
X0E
ID2
X0F
ID3
BYTE AAA
AA
555
55
AAA
90
X02
ID1
X1C
ID2
X1E
ID3
WORD 555
AA
2AA
55
555
90
X03
99/19(H)
89/09(L)
BYTE AAA
AA
555
55
AAA
90
X06
99/19(H)
89/09(L)
WORD 555
AA
2AA
55
555
90
(SA)X02
00/01
BYTE AAA
AA
555
55
AAA
90
(SA)X04
00/01
WORD 555
AA
2AA
55
555
88
BYTE AAA
AA
555
55
AAA
88
WORD 555
AA
2AA
55
555
90
XXX
00
BYTE AAA
AA
555
55
AAA
90
XXX
00
ID Reads, Sector Verify, and Security Sector Entry/Exit
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1st Bus
Cycle
Instruction
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA
Program
WORD 555
AA
2AA
55
555
A0
Add
Data
6th Bus Cycle
ADD
DATA
BYTE AAA
AA
555
55
AAA
A0
Add
Data
WORD 555
AA
2AA
55
SA
25
SA
N-1
WA
WD
WBL
WD
BYTE AAA
AA
555
55
SA
25
SA
N-1
WA
WD
WBL
WD
Write to Buffer Program
Abort Reset
WORD 555
AA
2AA
55
555
F0
BYTE AAA
AA
555
55
AAA
F0
Write to Buffer Program
Confirm
WORD SA
29
2AA
55
555
80
555
AA
2AA
55
555
10
Write to Buffer Program
Chip Erase
Sector Erase
CFI Read
Program/Erase Suspend
Program/Erase Resume
Table 6-14
SA
29
WORD 555
BYTE
AA
BYTE AAA
AA
555
55
AAA
80
AAA
AA
555
55
AAA
10
WORD 555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
BYTE AAA
AA
555
55
AAA
80
AAA
AA
555
55
SA
30
WORD
55
98
BYTE
AA
98
WORD XXX
B0
BYTE XXX
B0
WORD XXX
30
BYTE XXX
30
Program, Write Buffer, CFI, Erase and Suspend
WA=WRITE ADDRESS, WD=WRITE DATA, SA=SECTOR ADDRESS, N-1=WORD COUNT, WBL=WRITEBUFFER LOCATION, ID1/ID2/ID3: REFER TO Table 7-2 FOR
DETAIL ID.
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
ADD
DATA
ADD
DATA
ADD
DATA
ADD
ADD
WORD
555
AA
2AA
55
XXX
B9
555
55
XXX
B9
Deep Power
Down
Instruction
Table 6-15
DATA
DATA
ENTER
EXIT
BYTE
AAA
AA
WORD
XXX
AB
BYTE
XXX
AB
Deep Power Down
23
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
ADD
DATA
ADD
DATA
ADD
DATA
ADD
ADD
WORD
555
AA
2AA
55
555
40
AAA
40
Lock Register
Instruction
Lock Register
Instruction Set
Entry
Program
Read
AAA
AA
555
55
XXX
A0
XXX
DATA
XXX
DATA
BYTE
XXX
A0
WORD
XXX
DATA
BYTE
XXX
DATA
WORD
XXX
90
XXX
00
BYTE
XXX
90
XXX
00
IPB Instruction Set WORD
Entry
BYTE
555
AA
2AA
55
555
C0
AAA
AA
555
55
AAA
C0
WORD
XXX
A0
SA
00
BYTE
XXX
A0
SA
00
WORD
XXX
80
00
30
BYTE
XXX
80
00
30
WORD
SA
00/01
BYTE
SA
00/01
Lock Register
Instruction Exit
Global Non-Volatile
BYTE
WORD
IPB Program
All IPB Erase
IPB Status Read
Table 6-16
Global NonVolatile
DATA
Lock Register and Global Non-Volatile
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
ADD
DATA
ADD
DATA
ADD
DATA
ADD
ADD
WORD
XXX
90
XXX
00
BYTE
XXX
90
XXX
00
IPB Instruction Set WORD
Entry
BYTE
555
AA
2AA
55
555
50
AAA
AA
555
55
AAA
50
WORD
XXX
A0
XXX
00
BYTE
XXX
A0
XXX
00
WORD
XXX
00/01
BYTE
XXX
00/01
IPB Lock Instruction WORD
Set Exit
BYTE
XXX
90
XXX
00
XXX
90
XXX
00
Instruction
Global Volatile Freeze
DATA
DATA
DATA
IPB Instruction Set
Exit
IPB Lock Set
IPB Lock Status
Read
Table 6-17
IPB Functions
24
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
ADD
DATA
ADD
DATA
ADD
DATA
ADD
ADD
WORD
555
AA
2AA
55
555
E0
BYTE
AAA
AA
555
55
AAA
E0
WORD
XXX
A0
SA
00
Instruction
DPB Instruction Set
Entry
Volatile
DPB Set
DPB Clear
DPB Status READ
DPB Instruction Set
Exit
Table 6-18
Notes:
1.
2.
BYTE
XXX
A0
SA
00
WORD
XXX
A0
SA
01
BYTE
XXX
A0
SA
01
WORD
SA
00/01
BYTE
SA
00/01
WORD
XXX
90
XXX
00
BYTE
XXX
90
XXX
00
DATA
DATA
Volatile DPB Functions
It is not recommended to use any other code that is not in the instruction definition table which can potentially enter the
hidden mode.
For the IPB Lock and DPB Status Read "00" represents lock (protect), "01" represents unlock (unprotect).
25
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
6.6
Common Flash Memory Interface (CFI) Mode
6.6.1
Query Instruction and Common Flash memory Interface (CFI) Mode
Through Common Flash Interface (CFI) operations it is possible to access the operating characteristics,
structure and vendor specific information, such as identifying information, memory size, byte/word
configuration, operating voltages and timing information of this device. From the Read array mode
writing CFI Read instruction 98h to the address "55h"/"AAh" (Word/Byte, respectively), the device will
gain access to the CFI Query Mode. Once in the CFI mode data can be read using the addresses given
in Table 7-19 thru 7-22.
A reset instruction must be executed to exit CFI mode and the device will return to read array mode.
CFI mode: Identification Data Values (All Values in these tables are hexadecimal)
Description
Query-unique ASII string “QRY”
Primary vendor instruction set and control interface ID
code
Address for primary algorithm extended query table
Alternate vendor instruction set and control interface ID
code
Address for alternate algorithm extended query table
Table 6-19
Address
Address
(Word Mode) (Byte Mode)
10h
20h
11h
22h
12h
24h
13h
26h
14h
28h
15h
2Ah
16h
2Ch
17h
2Eh
18h
30h
19h
32h
1Ah
34h
Data
0051h
0052h
0059h
0006h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
CFI Mode: ID Data Values
26
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
CFI mode: System Interface Data Values
Address
Address
(Word Mode) (Byte Mode)
1Bh
36h
1Ch
38h
1Dh
3Ah
1Eh
3Ch
1Fh
3Eh
Description
VCC supply minimum program/erase voltage
VCC supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
Typical timeout per single word/byte write, 2n µs
Typical timeout for maximum-size buffer write, 2n µs
(00h, not support)
Typical timeout per individual block erase, 2n ms
Typical timeout for full chip erase, 2n ms (00h, not
support)
Maximum timeout for word/byte write, 2n times typical
Maximum timeout for buffer write, 2n times typical
Maximum timeout per individual block erase, 2n times
typical
Maximum timeout for chip erase, 2n times typical (00h,
not
support)
Table 6-20
CFI Mode: System Interface Data Values
27
Data
0027h
0036h
0000h
0000h
0003h
20h
40h
0004h
21h
42h
0009h
22h
44h
0011h
23h
24h
46h
48h
0003h
0005h
25h
4Ah
0003h
26h
4Ch
0002h
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
CFI mode: Device Geometry Data Values
Description
Device size = 2n in number of bytes
Flash device interface description (02=asynchronous
x8/x16)
Maximum number of bytes in buffer write = 2n (00h, not
support)
Number of erase regions within device (01h:uniform,
02h:boot)
Index for Erase Bank Area 1:
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256K-bytes
Index for Erase Bank Area 2
Index for Erase Bank Area 3
Index for Erase Bank Area 4
Table 6-21
Address
(Word Mode)
27h
28h
29h
2Ah
2Bh
Address
(Byte Mode)
4Eh
50h
52h
54h
56h
0019h
0002h
0000h
0006h
0000h
2Ch
58h
0001h
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
00FFh
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Data
CFI Mode: Device Geometry Data Values
28
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
CFI mode: Primary Vendor-Specific Extended Query Data Values
Address
Address
(Word Mode) (Byte Mode)
40h
80h
Query - Primary extended table, unique ASCII string, PRI
41h
82h
42h
84h
Major version number, ASCII
43h
86h
Minor version number, ASCII
44h
88h
Unlock recognizes address (0= recognize, 1= don't
45h
8Ah
recognize)
Erase suspend (2= to both read and program)
46h
8Ch
Sector protect (N= # of sectors/group)
47h
8Eh
Temporary sector unprotect (1=supported)
48h
90h
Sector protect/Chip unprotect scheme
49h
92h
Simultaneous R/W operation (0=not supported)
4Ah
94h
Burst mode (0=not supported)
4Bh
96h
Page mode (0=not supported, 01 = 4 word page, 02 = 8
4Ch
98h
word page)
Minimum ACC(acceleration) supply (0= not supported),
4Dh
9Ah
[D7:D4] for volt, [D3:D0] for 100mV
Maximum ACC(acceleration) supply (0= not supported),
4Eh
9Ch
[D7:D4] for volt, [D3:D0] for 100mV
WP# Protection
04=Uniform sectors bottom WP# protect
4Fh
9Eh
05=Uniform sectors top WP# protect
Program Suspend (0=not supported, 1=supported)
50h
A0h
Table 6-22
CFI mode: Primary Vendor-Specific Extended Query Data Values
Description
29
Data
0050h
0052h
0049h
0031h
0033h
001Ch
0002h
0001h
0000h
0008h
0000h
0000h
0002h
0095h
00A5h
00xxh
0001h
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
7
ELECTRICAL CHARACTERISTICS
7.1
Absolute Maximum Stress Ratings
Surrounding Temperature with Bias
Storage Temperature
VCC Voltage Range
EVIO Voltage Range
A9, #WP/ACC Voltage Range
Other Pins Voltage Range
Output Short Circuit Current (less than one second)
Table 7-1
Absolute Maximum Stress Ratings
7.2
-65°C to +125°C
-65°C to +150°C
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to +10.5V
-0.5V to VCC +0.5V
200 mA
Operating Temperature and Voltage
Industrial Grade Surrounding Temperature (TA)
Full VCC Range Supply Voltage
EVIO Range Supply Voltage(1)
Table 7-2
Operating Temperature and Voltage
NOTE:
1.
2.
3.
4.
5.
-40°C to +85°C
+2.7V to 3.6V
1.65V to VCC
The EVIO feature was designed to support voltages from 1.65V to VCC. Device testing is conducted at EVIO=VCC.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification are not implied. Exposure to
absolute maximum rating conditions for extended period may affect reliability.
Specifications contained within the following tables are subject to change.
During voltage transitions, all pins may overshoot VSS to -2.0V and VCC to +2.0V for periods up to 20ns, see below
Figure.
Specification for the W29GL256P is preliminary. See preliminary designation at the end of this document.
20ns
20ns
20ns
Vss
Vcc +2.0V
Vss -2.0V
Vcc
20ns
Figure 7-1
20ns
Maximum Negative Overshoot Figure 7-2
30
20ns
Maximum Positive Overshoot
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
7.3
DC Characteristics
DESCRIPTION
SYMBOL
Input Leak
ILI
A9 Leak
Output Leak
ILIT
ILO
Read Current
VCC Page Read Current
ICC1
ICC2
Write Current
ICC3
Standby Current
ICC4
Reset Current
ICC5
Sleep Mode Current(1)
ICC6
Conditions
MIN
TYP.
MAX
±2.0
±5.0
35
±1.0
Unit
µA
µA
µA
µA
6+
20
mA
20
30
mA
45
55
mA
7
15
mA
15
25
mA
20
30
mA
70
100
µA
70
100
µA
70
100
µA
1
5
µA
10
20
mA
20
30
mA
Others
WP#/ACC
A9=10.5V
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=1MHz
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=5MHz
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=10MHz
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=10MHz
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=33MHz
#CE=VIL, #OE=VIH, VCC=VCCmax
#CE, #RESET=VCC ±0.3V,
#OE=VIH, VCC=VCCmax,
VIL=VSS + 0.3V/-0.1V
VCC=VCCmax, #RESET enabled,
other pins disabled
VCC=VCCmax, VIH=VCC ±0.3,
VIL=VSS +(0.3v/-0.1v),
#WP/ACC=VIH
VCC deep power down
IDPD
current
Accelerated Pgm
#CE=VIL, #OE=VIH
Current, WP#/ACC,
IACC1
pin(Word/Byte)
Accelerated Pgm
#CE=VIL, #OE=VIH
Current, VCC pin,
IACC2
(Word/Byte)
Input Low Voltage
VIL
Input High Voltage
VIH
Very High Voltage for
Auto Select/
VHH
Accelerated Program
Output Low Voltage
VOL
IOL=100µA
Output High Voltage
VOH IOH=-100µA
VCC Write Protect
VWPT
Threshold
Table 7-3
DC Characteristics
-0.1
0.7xEVIO
9.5
0.3xEVIO V
EVIO+0.3 V
10.5
0.45
V
V
2.5
V
0.85xEVIO
2.3
Note:
1. Sleep mode enable the lower power when address remain stable for tAA+30ns.
31
Publication Release Date: Jul 02, 2014
Revision A
W29GL256P
7.4
Switching Test Circuits
Figure 7-3
Switch Test Circuit
Test Condition
Output Load
Output Load Capacitance
Rise/Fall Times
Input Pulse levels
Input timing measurement reference level (If EVIO
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