W29N01HV
W29N01HV
1G-BIT 3.3V
NAND FLASH MEMORY
1
Release Date: Oct 15, 2015
Revision A
W29N01HV
Table of Contents
1.
GENERAL DESCRIPTION ............................................................................................................... 6
2.
FEATURES ....................................................................................................................................... 6
3.
PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7
3.1
Pin assignment 48-pin TSOP1(x8) ....................................................................................... 7
3.2
Pin assignment 48 ball VFBGA (x8) ..................................................................................... 8
3.3
Pin assignment 63 ball VFBGA ............................................................................................ 9
3.4
Pin Descriptions .................................................................................................................. 10
4.
PIN DESCRITPIONS ...................................................................................................................... 11
4.1
Chip Enable (#CE).............................................................................................................. 11
4.2
Write Enable (#WE) ............................................................................................................ 11
4.3
Read Enable (#RE) ............................................................................................................ 11
4.4
Address Latch Enable (ALE) .............................................................................................. 11
4.5
Command Latch Enable (CLE) .......................................................................................... 11
4.6
Write Protect (#WP)............................................................................................................ 11
4.7
Ready/Busy (RY/#BY) ........................................................................................................ 11
4.8
Input and Output (I/Ox) ....................................................................................................... 11
5.
BLOCK DIAGRAM .......................................................................................................................... 12
6.
MEMORY ARRAY ORGANIZATION .............................................................................................. 13
6.1
Array Organization (x8) ...................................................................................................... 13
7.
MODE SELECTION TABLE ........................................................................................................... 14
8.
COMMAND TABLE......................................................................................................................... 15
9.
DEVICE OPERATIONS .................................................................................................................. 16
9.1
READ operation .................................................................................................................. 16
9.2
9.3
9.4
9.1.1
PAGE READ (00h-30h)......................................................................................................... 16
9.1.2
RANDOM DATA OUTPUT (05h-E0h) ................................................................................... 17
9.1.3
READ ID (90h) ...................................................................................................................... 17
9.1.4
READ PARAMETER PAGE (ECh) ....................................................................................... 18
9.1.5
READ STATUS (70h)............................................................................................................ 21
PROGRAM operation ......................................................................................................... 22
9.2.1
PAGE PROGRAM (80h-10h) ................................................................................................ 22
9.2.2
SERIAL DATA INPUT (80h).................................................................................................. 22
9.2.3
RANDOM DATA INPUT (85h) .............................................................................................. 23
COPY BACK operation....................................................................................................... 24
9.3.1
READ for COPY BACK (00h-35h) ........................................................................................ 24
9.3.2
PROGRAM for COPY BACK (85h-10h) ................................................................................ 24
BLOCK ERASE operation .................................................................................................. 26
9.4.1
9.5
9.5.1
9.6
10.
BLOCK ERASE (60h-D0h).................................................................................................... 26
RESET operation................................................................................................................ 27
RESET (FFh) ........................................................................................................................ 27
WRITE PROTECT .............................................................................................................. 28
ELECTRICAL CHARACTERISTICS............................................................................................... 30
10.1 Absolute Maximum Ratings ................................................................................................ 30
10.2 Operating Ranges .............................................................................................................. 30
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W29N01HV
10.3
10.4
10.5
10.6
10.7
10.8
Device power-up timing ...................................................................................................... 31
DC Electrical Characteristics .............................................................................................. 32
AC Measurement Conditions ............................................................................................. 33
AC timing characteristics for Command, Address and Data Input ..................................... 34
AC timing characteristics for Operation .............................................................................. 35
Program and Erase Characteristics ................................................................................... 36
11.
TIMING DIAGRAMS ....................................................................................................................... 37
12.
INVALID BLOCK MANAGEMENT .................................................................................................. 46
12.1 Invalid blocks ...................................................................................................................... 46
12.2 Initial invalid blocks ............................................................................................................. 46
12.3 Error in operation ................................................................................................................ 47
12.4 Addressing in program operation ....................................................................................... 48
13.
PACKAGE DIMENSIONS ............................................................................................................... 49
13.1 TSOP 48-pin 12x20 ............................................................................................................ 49
13.2 Fine-Pitch Ball Grid Array 48-ball ....................................................................................... 50
13.3 Fine-Pitch Ball Grid Array 63-ball ....................................................................................... 51
14.
ORDERING INFORMATION .......................................................................................................... 52
15.
VALID PART NUMBERS ................................................................................................................ 53
16.
REVISION HISTORY ...................................................................................................................... 54
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W29N01HV
List of Tables
Table 3.1 Pin Descriptions .......................................................................................................................... 10
Table 6.1 Addressing .................................................................................................................................. 13
Table 7.1 Mode Selection ........................................................................................................................... 14
Table 8.1 Command Table.......................................................................................................................... 15
Table 9.1 Device ID and configuration codes for Address 00h................................................................... 18
Table 9.2 ONFI identifying codes for Address 20h ..................................................................................... 18
Table 9.3 Parameter Page Output Value .................................................................................................... 20
Table 9.4 Status Register Bit Definition ...................................................................................................... 21
Table 10.1 Absolute Maximum Ratings ...................................................................................................... 30
Table 10.3 Operating Ranges ..................................................................................................................... 30
Table 10.5 DC Electrical Characteristics .................................................................................................... 32
Table 10.7 AC Measurement Conditions .................................................................................................... 33
Table 10.9 AC timing characteristics for Command, Address and Data Input ........................................... 34
Table 10.11 AC timing characteristics for Operation .................................................................................. 35
Table 10.13 Program and Erase Characteristics ........................................................................................ 36
Table 12.1 Valid Block Number .................................................................................................................. 46
Table 12.2 Block failure ............................................................................................................................... 47
Table 15.1 Part Numbers for Industrial Temperature ................................................................................. 53
Table 16.1 History Table ............................................................................................................................. 54
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W29N01HV
List of Figures
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S) ...................................................................... 7
Figure 3-2 Pin Assignment 48-ball VFBGA (Package code D) ..................................................................... 8
Figure 3-3 Pin Assignment 63-ball VFBGA (Package Code B) .................................................................... 9
Figure 5-3 NAND Flash Memory Block Diagram ........................................................................................ 12
Figure 6-1 Array Organization ..................................................................................................................... 13
Figure 9-1 Page Read Operations .............................................................................................................. 16
Figure 9-2 Random Data Output ................................................................................................................. 17
Figure 9-3 Read ID ...................................................................................................................................... 17
Figure 9-4 Read Parameter Page ............................................................................................................... 18
Figure 9-5 Read Status Operation .............................................................................................................. 21
Figure 9-6 Page Program............................................................................................................................ 22
Figure 9-7 Random Data Input ................................................................................................................... 23
Figure 9-8 Copy Back Program Operation .................................................................................................. 25
Figure 10-1 Power ON/OFF sequence ....................................................................................................... 31
Figure 11-1 Command Latch Cycle ............................................................................................................ 37
Figure 11-2 Address Latch Cycle ................................................................................................................ 37
Figure 11-3 Data Latch Cycle ..................................................................................................................... 38
Figure 11-4 Serial Access Cycle after Read ............................................................................................... 38
Figure 11-5 Serial Access Cycle after Read (EDO) .................................................................................... 39
Figure 11-6 Read Status Operation ............................................................................................................ 39
Figure 11-7 Page Read Operation .............................................................................................................. 40
Figure 11-8 #CE Don't Care Read Operation ............................................................................................. 40
Figure 11-9 Random Data Output Operation .............................................................................................. 41
Figure 11-10 Read ID .................................................................................................................................. 42
Figure 11-11 Page Program........................................................................................................................ 42
Figure 11-12 #CE Don't Care Page Program Operation ............................................................................ 43
Figure 11-13 Page Program with Random Data Input ................................................................................ 43
Figure 11-14 Copy Back ............................................................................................................................. 44
Figure 11-15 Block Erase............................................................................................................................ 44
Figure 11-16 Reset ..................................................................................................................................... 45
Figure 12-1 flow chart of create initial invalid block table ........................................................................... 47
Figure 12-2 Bad block Replacement ........................................................................................................... 48
Figure 13-1 TSOP 48-PIN 12X20mm ......................................................................................................... 49
Figure 13-2 Fine-Pitch Ball Grid Array 48-Ball ............................................................................................ 50
Figure 13-3 Fine-Pitch Ball Grid Array 63-Ball (9x11mm) .......................................................................... 51
Figure 14-1 Ordering Part Number Description .......................................................................................... 52
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W29N01HV
1. GENERAL DESCRIPTION
The W29N01HV (1G-bit) NAND Flash memory provides a storage solution for embedded systems with
limited space, pins and power. It is ideal for code shadowing to RAM, solid state applications and storing
media data such as, voice, video, text and photos. The device operates on a single 2.7V to 3.6V power
supply with active current consumption as low as 25mA 10uA for CMOS standby current.
The memory array totals 138,412,032 bytes, and organized into 1,024 erasable blocks of 135,168 bytes.
Each block consists of 64 programmable pages of 2,112-bytes each. Each page consists of 2,048-bytes
for the main data storage area and 64-bytes for the spare data area (The spare area is typically used for
error management functions).
The W29N01HV supports the standard NAND flash memory interface using the multiplexed 8-bit bus to
transfer data, addresses, and command instructions. The five control signals, CLE, ALE, #CE, #RE and
#WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write
Protect) and the RY/#BY (Ready/Busy) for monitoring the device status.
2. FEATURES
Basic Features
– Density : 1Gbit (Single chip solution)
– Vcc : 2.7V to 3.6V
– Bus width : x8
– Operating temperature
Industrial: -40°C to 85°C
Single-Level Cell (SLC) technology.
Organization
– Density: 1G-bit/128M-byte
– Page size
2,112 bytes (2048 + 64 bytes)
– Block size
64 pages (128K + 4K bytes)
Highest Performance
– Read performance (Max.)
Random read: 25us
Sequential read cycle: 25ns
– Write Erase performance
Page program time: 250us(typ.)
Block erase time: 2ms(typ.)
– Endurance 100,000 Erase/Program
Cycles
– 10-years data retention
Command set
– Standard NAND command set
– Additional command support
Copy Back
Lowest power consumption
– Read: 25mA(typ.3V),
– Program/Erase: 25mA(typ.3V),
– CMOS standby: 10uA(typ.)
Space Efficient Packaging
– 48-pin standard TSOP1
– 48-ball VFBGA
– 63-ball VFBGA
– Contact Winbond for stacked
packages/KGD
Note:
1.
Endurance specification is based on 1bit/528 byte ECC (Error Correcting Code).
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Revision A
W29N01HV
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W29N01HV is offered in a 48-pin TSOP1 package (Code S) and 48-ball VFBGA package (Code D)
and 63-ball VFBGA package (Code B) as shown in Figure 3-1 to 3-3, respectively. Package
diagrams and dimensions are illustrated in Section: Package Dimensions.
3.1
Pin assignment 48-pin TSOP1(x8)
Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S)
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3.2
Pin assignment 48 ball VFBGA (x8)
Figure 3-2 Pin Assignment 48-ball VFBGA (Package code D)
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W29N01HV
3.3
Pin assignment 63 ball VFBGA
Top View, ball down
1
2
A
N.C
N.C
B
N.C
3
4
5
6
7
8
C
#WP
ALE
Vss
#CE
#WE
RY/ #BY
D
N.C
#RE
CLE
N.C
N.C
N.C
E
N.C
N.C
N.C
N.C
N.C
N.C
F
N.C
N.C
N.C
N.C
N.C
N.C
G
DNU
N.C
DNU
N.C
N.C
N.C
H
N.C
IO0
N.C
N.C
N.C
Vcc
J
N.C
IO1
N.C
Vcc
IO5
IO7
K
Vss
IO2
IO3
IO4
IO6
Vss
9
10
N.C
N.C
N.C
N.C
L
N.C
N.C
N.C
N.C
M
N.C
N.C
N.C
N.C
Figure 3-3 Pin Assignment 63-ball VFBGA (Package Code B)
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W29N01HV
3.4
Pin Descriptions
PIN NAME
I/O
FUNCTION
#WP
I
Write Protect
ALE
I
Address Latch Enable
#CE
I
Chip Enable
#WE
I
Write Enable
RY/#BY
O
Ready/Busy
#RE
I
Read Enable
CLE
I
Command Latch Enable
I/O[0-7]
I/O
Vcc
Supply
Power supply
Vss
Supply
Ground
DNU
-
Do Not Use: This pins are unconnected pins.
N.C
-
No Connect
Data Input/Output
Table 3.1 Pin Descriptions
Note:
1.
Connect all Vcc and Vss pins to power supply or ground. Do not leave Vcc or Vss disconnected.
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4. PIN DESCRITPIONS
4.1 Chip Enable (#CE)
#CE pin enables and disables device operation. When #CE is high the device is disabled and the
I/O pins are set to high impedance and enters into standby mode if not busy. When #CE is set low
the device will be enabled, power consumption will increase to active levels and the device is ready
for Read and Write operations.
4.2 Write Enable (#WE)
#WE pin enables the device to control write operations to input pins of the device. Such as,
command instructions, addresses and data that are latched on the rising edge of #WE.
4.3 Read Enable (#RE)
#RE pin controls serial data output from the pre-loaded Data Register. Valid data is present on the
I/O bus after the tREA period from the falling edge of #RE. Column addresses are incremented for
each #RE pulse.
4.4 Address Latch Enable (ALE)
ALE pin controls address input to the address register of the device. When ALE is active high,
addresses are latched via the I/O pins on the rising edge of #WE.
4.5 Command Latch Enable (CLE)
CLE pin controls command input to the command register of the device. When CLE is active high,
commands are latched into the command register via I/O pins on the rising edge of #WE.
4.6 Write Protect (#WP)
#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is
active low, all program/erase operations are disabled.
4.7 Ready/Busy (RY/#BY)
RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is
processing either a program, erase or read operations. When it returns to high, those operations
have completed. RY/#BY pin is an open drain.
4.8 Input and Output (I/Ox)
I/Ox bi-directional pins are used for the following; command, address and data operations.
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W29N01HV
5. BLOCK DIAGRAM
#CE
#RE
#WE
ALE
CLE
#WP
Logic
Control
Control
unit
RY/ #BY
RY/ #BY
Data register
IO8 to IO15
(x16 only)
Row decode unit
Flash Memory Block Diagram
Column decode unit
IO0 to IO7
Status
register
Figure 5-4 NAND
Address
latch
IO control
Command
unit
latch
Memory array
High
Voltage
Generator
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W29N01HV
6. MEMORY ARRAY ORGANIZATION
6.1
Array Organization (x8)
Total
1024 blocks
IO0 ~ IO7
1 block
2048
Data register
1 page
= 2048+64 bytes
1 block
= 64 pages
= (128K+4K) bytes
1 device
=1024 blocks
= (128M + 4M) bytes
64
2112 bytes
Figure 6-1 Array Organization
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st cycle
A7
A6
A5
A4
A3
A2
A1
A0
2nd cycle
L
L
L
L
A11
A10
A9
A8
cycle
A19
A18
A17
A16
A15
A14
A13
A12
4th cycle
A27
A26
A25
A24
A23
A22
A21
A20
3rd
Table 6.1 Addressing
Notes:
1.
“L” indicates a low condition, which must be held during the address cycle to insure correct processing.
2.
A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A27 during the 3rd and 4th cycles
are row addresses.
3.
The device ignores any additional address inputs that exceed the device’s requirement.
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W29N01HV
7. MODE SELECTION TABLE
MODE
CLE
ALE
#CE
#WE
#RE
#WP
Read
mode
Command input
H
L
L
H
X
Address input
L
H
L
H
X
Program
Command input
H
L
L
H
H
Erase
mode
Address input
L
H
L
H
H
Data input
L
L
L
H
H
Sequential Read and Data output
L
L
L
H
During read (busy)
X
X
X
X
H
X
During program (busy)
X
X
X
X
X
H
During erase (busy)
X
X
X
X
X
H
Write protect
X
X
X
X
X
L
Standby
X
X
H
X
X
0V/Vcc
X
Table 7.1 Mode Selection
Notes:
1.
“H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” indicates a Don’t Care Level.
2.
#WP should be biased to CMOS HIGH or LOW for standby.
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W29N01HV
8. COMMAND TABLE
1ST
CYCLE
2ND
CYCLE
PAGE READ
00h
30h
READ for COPY BACK
00h
35h
READ ID
90h
READ STATUS
70h
Yes
RESET
FFh
Yes
PAGE PROGRAM
80h
10h
PROGRAM for COPY BACK
85h
10h
BLOCK ERASE
60h
D0h
RANDOM DATA INPUT*1
85h
RANDOM DATA OUTPUT*1
05h
READ PARAMETER PAGE
ECh
COMMAND
3rd
CYCLE
4th
CYCLE
Acceptable
during
busy
E0h
Table 8.1 Command Table
Notes:
1.
RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page.
2.
Any command that are not in the above table are considered as undefined and are prohibited as inputs.
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W29N01HV
9. DEVICE OPERATIONS
9.1 READ operation
9.1.1 PAGE READ (00h-30h)
When the device powers on, 00h command is latched to command register. Therefore, system only
issues four address cycles and 30h command for initial read from the device. This operation can
also be entered by writing 00h command to the command register, and then write four address
cycles, followed by writing 30h command. After writing 30h command, the data is transferred from
NAND array to Data Register during tR. Data transfer progress can be done by monitoring the
status of the RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there is
an alternate method by using the READ STATUS (70h) command. If the READ STATUS command
is issued during read operation, the Read (00h) command must be re-issued to read out the data
from Data Register. When the data transfer is complete, RY/#BY signal goes HIGH, and the data
can be read from Data Register by toggling #RE. Read is sequential from initial column address to
the end of the page. (See Figure 9-1)
CLE
#CE
#WE
ALE
#RE
l/Ox
00h
Data Output (Serial Access)
30h
Address (4cycles)
tR
RY/#BY
Don’t care
Figure 9-1 Page Read Operations
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W29N01HV
9.1.2 RANDOM DATA OUTPUT (05h-E0h)
The RANDOM DATA OUTPUT allows the selection of random column addresses to read out data
from a single or multiple of addresses. The use of the RANDOM DATA OUTPUT command is
available after the PAGE READ (00h-30h) sequence by writing the 05h command following by the
two cycle column address and then the E0h command. Toggling #RE will output data sequentially.
The RANDOM DATA OUTPUT command can be issued multiple times, but limited to the current
loaded page.
tR
RY/ #BY
#RE
I/ Ox
00h
Address(4cycles)
30h
Data out
05h
Address(2cycles)
E0h
Data out
Figure 9-2 Random Data Output
9.1.3 READ ID (90h)
READ ID command is comprised of two modes determined by the input address, device (00h) or
ONFI (20h) identification information. To enter the READ ID mode, write 90h to the Command
Register followed by a 00h address cycle, then toggle #RE for 5 single byte cycles, W29N01HV.
The pre-programmed code includes the Manufacturer ID, Device ID, and Product-Specific
Information (see Table 9.1). If the READ ID command is followed by 20h address, the output code
includes 4 single byte cycles of ONFI identifying information (See Table 9.2). The device remains in
the READ ID Mode until the next valid command is issued.
CLE
#CE
#WE
tAR
ALE
#RE
tWHR
I/ Ox
90h
00h
tREA
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
(or 20h)
Address, 1 cycle
Figure 9-3 Read ID
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W29N01HV
# of
1st
2nd
Byte/Cycles Byte/Cycle Byte/Cycle
W29N01HV
Description
EFh
3rd
Byte/Cycle
4th
Byte/Cycle
5th
Byte/Cycle
00h
95h
00h
Cache
Programming
Non-supported
Page Size:2KB
Spare Area Size:64b
BLK Size w/o
Spare:128KB
Organized:x8 or x16
Serial Access:25ns
F1h
MFR ID
Device ID
x16 device : the ID is outputted at word units, and defined lower-byte (IO0-7). ID table shows only lower-byte ID.
Table 9.1 Device ID and configuration codes for Address 00h
# of Byte/Cycles
1st
Byte/Cycle
2nd
Byte/Cycle
3rd
Byte/Cycle
4th
Byte/Cycle
Code
4Fh
4Eh
46h
49h
Table 9.2 ONFI identifying codes for Address 20h
9.1.4 READ PARAMETER PAGE (ECh)
READ PARAMETER PAGE can read out the device’s parameter data structure, such as,
manufacturer information, device organization, timing parameters, key features, and other pertinent
device parameters. The data structure is stored with at least three copies in the device’s parameter
page. Figure 9-4 shows the READ PARAMETER PAGE timing. The RANDOM DATA OUTPUT
(05h-E0h) command is supported during data output.
CLE
#WE
ALE
#RE
I/ Ox
ECh
00h
P0
P1
・・・
P1022
P1023
tR
RY/ #BY
Figure 9-4 Read Parameter Page
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W29N01HV
Byte
Description
Value
0-3
Parameter page signature
4Fh, 4Eh, 46h, 49h
4-5
Revision number
02h, 00h
6-7
Features
supported
W29N01HV
10h, 00h
8-9
Optional commands supported
10h, 00h
10-31
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h
32-43
Device manufacturer
57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,
20h
44-63
Device model
57h, 32h, 39h, 4Eh, 30h, 31h, 48h, 56h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h
64
W29N01HV
Manufacturer ID
EFh
65-66
Date code
00h, 00h
67-79
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
80-83
# of data bytes per page
00h, 08h, 00h, 00h
84-85
# of spare bytes per page
40h, 00h
86-89
# of data bytes per partial page
00h, 02h, 00h, 00h
90-91
# of spare bytes per partial page
10h, 00h
92-95
# of pages per block
40h, 00h, 00h, 00h
96-99
# of blocks per unit
00h, 04h, 00h, 00h
100
# of logical units
01h
101
# of address cycles
22h
102
# of bits per cell
01h
103-104
Bad blocks maximum per unit
14h, 00h
105-106
Block endurance
01h, 05h
Guaranteed valid blocks at beginning of
target
01h
Block endurance for guaranteed valid
blocks
00h, 00h
110
# of programs per page
04h
111
Partial programming attributes
00h
112
# of ECC bits
01h
113
# of interleaved address bits
00h
107
108-109
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W29N01HV
Byte
114
Description
Value
Interleaved operation attributes
00h
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
I/O pin capacitance
0Ah
129-130
Timing mode
support
1Fh, 00h
131-132
Program cache timing
00h, 00h
133-134
Maximum page program time
BCh, 02h
135-136
Maximum block erase time
10h, 27h
137-138
Maximum random read time
19h, 00h
139-140
tCCS
minimum
3Ch, 00h
141-163
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h
164-165
Vendor specific revision #
01h,00h
166-253
Vendor specific
00h
254-255
Integrity CRC
Set at shipment
256-511
Value of bytes 0-255
512-767
Value of bytes 0-255
115-127
128
>767
W29N01HV
W29N01HV
Additional redundant parameter pages
Table 9.3 Parameter Page Output Value
20
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W29N01HV
9.1.5 READ STATUS (70h)
The W29N01HV has an 8-bit Status Register which can be read during device operation. Refer to
Table 9.4 for specific Status Register definitions. After writing 70h command to the Command
Register, read cycles will only read from the Status Register. The status can be read from I/O[7:0]
outputs, as long as #CE and #RE are LOW. Note; #RE does not need to be toggled for Status
Register read. The Command Register remains in status read mode until another command is
issued. To change to normal read mode, issue the PAGE READ (00h) command. After the PAGE
READ command is issued, data output starts from the initial column address.
#CE
tCLR
CLE
tREA
#WE
#RE
Status Output
70h
I/ Ox
Figure 9-5 Read Status Operation
SR bit
Page Read
Page Program
Block Erase
Definition
I/O 0
Not Use
Pass/Fail
Pass/Fail
I/O 1
Not Use
Not Use
Not Use
I/O 2
Not Use
Not Use
Not Use
0
I/O 3
Not Use
Not Use
Not Use
0
I/O 4
Not Use
Not Use
Not Use
0
I/O 5
Ready/Busy
Ready/Busy
Ready/Busy
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
I/O 7
Write Protect
Write Protect
Write Protect
0=Successful Program/Erase
1=Error in Program/Erase
0=Successful Program
1=Error in Program
Ready = 1
Busy = 0
Ready = 1
Busy = 0
Unprotected = 1
Protected = 0
Table 9.4 Status Register Bit Definition
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9.2 PROGRAM operation
9.2.1 PAGE PROGRAM (80h-10h)
The W29N01HV Page Program command will program pages sequentially within a block, from the
lower order page address to higher order page address. Programming pages out of sequence is
prohibited. The W29N01HV supports partial-page programming operations up to 4 times before an
erase is required if partitioning a page. Note; programming a single bit more than once without first
erasing it is not supported.
9.2.2 SERIAL DATA INPUT (80h)
Page Program operation starts with the execution of the Serial Data Input command (80h) to the
Command Register, following next by inputting four address cycles and then the data is loaded.
Serial data is loaded to Data register with each #WE cycle. The Program command (10h) is written
to the Command Register after the serial data input is finished. At this time the internal write state
controller automatically executes the algorithms for program and verifies operations. Once the
programming starts, determining the completion of the program process can be done by monitoring
the RY/#BY output or the Status Register Bit 6, which will follow the RY/#BY signal. RY/#BY will
stay LOW during the internal array programming operation during the period of (tPROG). During
page program operation, only two commands are available, READ STATUS (70h) and RESET
(FFh). When the device status goes to the ready state, Status Register Bit 0 (I/O0) indicates
whether the program operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-6). The Command
Register remains in read status mode until the next command is issued.
tPROG
RY/ #BY
I/ Ox
80h
Address (4cycles)
Din
10h
70h
Status
I/O0=0pass
I/O0=1fail
Figure 9-6 Page Program
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9.2.3 RANDOM DATA INPUT (85h)
After the Page Program (80h) execution of the initial data has been loaded into the Data register, if
the need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command
can perform this function to a new column address prior to the Program (10h) command. The
RANDOM DATA INPUT command can be issued multiple times in the same page (See Figure 9-7).
CLE
#CE
#WE
ALE
#RE
tPROG
RY/ #BY
I/ Ox
80h
Address (4cycles)
Din
85h
Address
(2 cycles)
Din
10h
70h
Status
Don’t care
Figure 9-7 Random Data Input
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9.3
COPY BACK operation
Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h)
command first, then the PROGRAM for COPY BACK (85h-10h) command.
9.3.1 READ for COPY BACK (00h-35h)
The READ for COPY BACK command is used together with the PROGRAM for COPY BACK (85h10h) command. To start execution, READ for COPY BACK (00h) command is written to the
Command Register, followed by the four cycles of the source page address. To start the transfer of
the selected page data from the memory array to the Data register, write the 35h command to the
Command Register.
After execution of the READ for COPY BACK command sequence and RY/#BY returns to HIGH
marking the completion of the operation, the transferred data from the source page into the Data
register may be read out by toggling #RE. Data is output sequentially from the column address that
was originally specified with the READ for COPY BACK command. RANDOM DATA OUTPUT (05hE0h) commands can be issued multiple times without any limitation after READ for COPY BACK
command has been executed (see Figures 9-8 and 9-9).
At this point the device is in ready state to accept the PROGRAM for COPY BACK command.
9.3.2 PROGRAM for COPY BACK (85h-10h)
After the READ for COPY BACK command operation has been completed and RY/#BY goes HIGH,
the PROGRAM for COPY BACK command can be written to the Command Register. The command
results in the transfer of data to the Data Register, then internal operations start programming of the
new destination page. The sequence would be, write 85h to the Command Register, followed by the
four cycle destination page address to the NAND array. Next write the 10h command to the
Command Register; this will signal the internal controller to automatically start to program the data
to new destination page. During this programming time, RY/#BY will LOW. The READ STATUS
command can be used instead of the RY/#BY signal to determine when the program is complete.
When Status Register Bit 6 (I/O6) equals to “1”, Status Register Bit 0 (I/O0) will indicate if the
operation was successful or not.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for COPY BACK
command for modifying the original data. Once the data is copied into the Data register using the
READ for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h)
command, along with the address of the data to be changed. The data to be changed is placed on
the external data pins. This operation copies the data into the Data register. Once the 10h
command is written to the Command Register, the original data and the modified data are
transferred to the Data Register, and programming of the new page commences. The RANDOM
DATA INPUT command can be issued numerous times without limitation, as necessary before
starting the programming sequence with 10h command.
Since COPY BACK operations do not use external memory and the data of source page might
include a bit errors, a competent ECC scheme should be developed to check the data before
programming data to a new destination page.
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CLE
#CE
#WE
ALE
#RE
I/ Ox
00h
Address (4cycles)
Data output
35h
05h
Address
(2cycles)
E0h
Data Output
85h
Address(4cycles)
10h
70h
Status
Output
No limitation
Optional
tPROG
tR
RY/ # BY
Don’t care
Figure 9-8 Copy Back Program Operation
CLE
#CE
#WE
ALE
#RE
I/ Ox
00h Address(5Cycles) 35h
DataOutput
85h Address(5cycles)
Data Input
85h
Address
(2cycles)
Data Input
10h
70h
Status
Output
No limitation
Optional
tPROG
tR
RY/ #BY
Don’t care
Figure 9-9 Copy Back Operation with Random Data Input
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9.4 BLOCK ERASE operation
9.4.1
BLOCK ERASE (60h-D0h)
Erase operations happen at the architectural block unit. This W29N01HV has 1024 erase blocks.
Each block is organized into 64 pages (2112 bytes/page), 132K bytes (128K + 4K bytes)/block. The
BLOCK ERASE command operates on a block by block basis.
Erase Setup command (60h) is written to the Command Register. Next, the two cycle block address
is written to the device. The page address bits are loaded during row address cycle, but are
ignored. The Erase Confirm command (D0h) is written to the Command Register at the rising edge
of #WE, RY/#BY goes LOW and the internal controller automatically handles the block erase
sequence of operation. RY/#BY goes LOW during Block Erase internal operations for a period of
tBERS,
The READ STATUS (70h) command can be used for confirm block erase status. When Status
Register Bit6 (I/O6) becomes to “1”, block erase operation is finished. Status Register Bit0 (I/O0)
will indicate a pass/fail condition (see Figure 9-10).
CLE
#CE
#WE
ALE
#RE
I/ Ox
60h
Address Input (2cycles)
70h
D0h
tBERS
Status Output
I/ O 0 = 0 pass
I/ O 0 = 1 fail
RY/ #BY
Don’t care
Figure 9-10 Block Erase Operation
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9.5
RESET operation
9.5.1 RESET (FFh)
READ, PROGRAM, and ERASE commands can be aborted by the RESET (FFh) command during
the time the W29N01HV is in the busy state. The Reset operation puts the device into known
status. The data that is processed in either the programming or erasing operations are no longer
valid. This means the data can be partially programmed or erased and therefore data is invalid. The
Command Register is cleared and is ready to accept next command. The Data Register contents
are marked invalid.
The Status Register indicates a value of E0h when #WP is HIGH; otherwise a value of 60h is
written when #WP is LOW. After RESET command is written to the command register, RY/#BY
goes LOW for a period of tRST (see Figure 9-11).
CLE
#CE
tWB
#WE
tRST
RY/ #BY
I/ Ox
FFh
RESET
command
Figure 9-11 Reset Operation
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9.6
WRITE PROTECT
#WP pin can enable or disable program and erase commands preventing or allowing program and
erase operations. Figure 9-12 to 9-17 shows the enabling or disabling timing with #WP setup time
(tWW) that is from rising or falling edge of #WP to latch the first commands. After first command is
latched, #WP pin must not toggle until the command operation is complete and the device is in the
ready state. (Status Register Bit5 (I/O5) equal 1)
#WE
tWW
60h
I /Ox
D0h
#WP
RY/#BY
Figure 9-12 Erase Enable
#WE
tWW
I/ Ox
60h
D0h
#WP
RY/#BY
Figure 9-13 Erase Disable
#WE
tWW
I/Ox
80h
10h
10h
#WP
RY/#BY
Figure 9-14 Program Enable
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#WE
tWW
I/ Ox
80 h
10h
#WP
RY/ #BY
Figure 9-15 Program Disable
#WE
tWW
I/ Ox
85h
10h
#WP
RY/ #BY
Figure 9-16 Program for Copy Back Enable
#WE
tWW
I/ Ox
10h
85h
#WP
RY/ #BY
Figure 9-17 Program for Copy Back Disable
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10. ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
CONDITIONS
VCC
Voltage Applied to Any Pin
VIN
Storage Temperature
Relative to Ground
TSTG
RANGE
UNIT
–0.6 to +4.6
V
–0.6 to +4.6
V
–65 to +150
°C
5
mA
Short circuit output current, I/Os
Table 10.1 Absolute Maximum Ratings
Notes:
1.
Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V
for periods
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