W39L020Q-90

W29EE012 128K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29EE012 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29EE012 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES • • Single 5-volt program and erase operations Fast page-write operations − 128 bytes per page − Page program cycle: 10 mS (max.) − Effective byte-program cycle time: 39 µS − Optional software-protected data write • Low power consumption − Active current: 25 mA (typ.) − Standby current: 20 µA (typ.) • • Automatic program timing with internal VPP generation End of program detection − Toggle bit − Data polling • • • • Fast chip-erase operation: 50 mS Page program/erase cycles: 1,000 Ten-year data retention Software and hardware data protection • • • Latched address and data TTL compatible I/O JEDEC standard byte-wide pinouts -1- Publication Release Date: March 26, 2002 Revision A3 W29EE012 PIN CONFIGURATIONS BLOCK DIAGRAM NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 VDD #WE NC A14 A13 A8 A9 A11 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS #CE #OE #WE CONTROL OUTPUT BUFFER DQ0 . . DQ7 32-pin DIP 26 25 24 23 22 21 20 19 18 17 A0 . . A16 DECODER CORE ARRAY V# AAA 1 11NDWN 256CDEC 4 5 6 7 8 9 10 11 12 13 3 2 1 32 31 30 29 28 27 PIN DESCRIPTION A14 A13 A8 A9 A11 #OE A10 #CE DQ7 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 SYMBOL A0 − A16 DQ0 − DQ7 #CE #OE #WE VDD GND NC PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection 32-pin PLCC 26 25 24 23 22 21 14 15 16 17 18 19 20 DDGDDDD QQNQQQQ 12D3456 -2- W29EE012 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29EE012 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29EE012 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FFh" during programming of the page. The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE, whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200 µS, after the initial byte-load cycle, the W29EE012 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer within 300 µS (TBLCO) from the last byte-load cycle, i.e., there is no subsequent #WE high-to-low transition after the last rising edge of #WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29EE012 is shipped with the software data unprotection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram. Publication Release Date: March 26, 2002 Revision A3 -3- W29EE012 Hardware Data Protection The integrity of the data stored in the W29EE012 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and operation are inhibited when VDD is less than 3.8V. (3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. Data Polling (DQ7)-Write Status Detection The W29EE012 includes a data polling feature to indicate the end of a programming cycle. When the W29EE012 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. Toggle Bit (DQ6)-Write Status Detection In addition to data polling, the W29EE012 provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-Only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the device code (C1h). The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE high, and raising A9 to 12 volts. Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details. -4- W29EE012 TABLE OF OPERATING MODES Operating Mode Selection Operating Range = 0 to 70°C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V MODE #CE Read Write Standby Write Inhibit Output Disable 5-Volt Software Chip Erase Product ID VIL VIL VIH X X X VIL VIL VIL #OE VIL VIH X VIL X VIH VIH VIL VIL #WE VIH VIL X X VIH X VIL VIH VIH AIN AIN X X X X AIN PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z DIN Manufacturer Code DA (Hex) Device Code C1 (Hex) DQ. A0 = VIL; A1-A16 = VIL; A9 = VHH A0 = VIH; A1-A16 = VIL; A9 = VHH -5- Publication Release Date: March 26, 2002 Revision A3 W29EE012 Command Codes for Software Data Protection BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION ADDRESS 5555H 2AAAH 5555H DATA AAH 55H A0H TO DISABLE PROTECTION ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 20H Software Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AA to address 5555 Software Data Protection Disable Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data A0 to address 5555 Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 20 to address 5555 Notes for software program code: Data Format: DQ7 − DQ0 (Hex) Address Format: A14 − A0 (Hex) -6- W29EE012 Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Sofware Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Notes for software chip erase: Data Format: DQ7 − DQ0 (Hex) Address Format: A14 − A0 (Hex) -7- Publication Release Date: March 26, 2002 Revision A3 W29EE012 Command Codes for Product Identification BYTE SEQUENCE SOFTWARE PRODUCT IDENTIFICATION ENTRY ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 10 µS DATA AAH 55H 80H AAH 55H 60H SOFTWARE PRODUCT IDENTIFICATION EXIT ADDRESS 5555H 2AAAH 5555H Pause 10 µS DATA AAH 55H F0H - Software Product Identification Acquisition Flow Product Identification Entry(1) Product Identification Mode(2,3) Product Identification Exit(1) Load data AA to address 5555 Load data 55 to address 2AAA Load data AA to address 5555 Load data 80 to address 5555 Read address = 0 data = DA Load data 55 to address 2AAA Load data AA to address 5555 Load data FO to address 5555 Load data 55 to address 2AAA Read address = 1 data = C1 S Pause 10 µm Load data 60 to address 5555 (4) Normal Mode Pause 10 µS Notes for software product identification: (1) Data format: DQ7 − DQ0 (Hex); address format: A14 − A0 (Hex). (2) A1 − A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns to standard operation mode. -8- W29EE012 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Except #OE Transient Voltage (≤20 nS) on Any Pin to Ground Potential Voltage on #OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V °C °C V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER Power Supply Current SYM. ICC TEST CONDITIONS MIN. #CE = #OE = VIL, #WE = VIH, all I/Os open Address inputs = VIL/VIH, at f = 5 MHz - LIMITS TYP. MAX. 50 UNIT mA Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage ISB1 #CE = VIH, all I/Os open Other inputs = VIL/VIH ISB2 #CE = VDD -0.3V, all I/Os open Other inputs = VDD -0.3V/GND ILI ILO VIL VIH VOL IOL = 2.1 mA VOH IOH = -0.4 mA VIN = GND to VDD VIN = GND to VDD - -0.3 2.0 2.4 2 20 - 3 100 1 10 0.8 VDD +0.5 0.45 - mA µA µA µA V V V V Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU.READ TPU.WRITE TYPICAL 100 5 UNIT µS mS -9- Publication Release Date: March 26, 2002 Revision A3 W29EE012 CAPACITANCE (VDD = 5.0V, TA = 25° C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL CI/O CIN CONDITIONS VI/O = 0V VIN = 0V MAX. 12 6 UNIT pF pF AC CHARACTERISTICS AC Test Conditions (VDD = 5V ±10%) PARAMETER 90 nS/120 nS Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V/3V 5 nS 1.5V/1.5V CONDITIONS 150 nS 0V/3V 10 nS 1.5V/1.5V 1 TTL Gate and CL = 100 pF 1 TTL Gate and CL = 100 pF AC Test Load and Waveforms +5V 1.8K ohm DOUT 1.3K ohm 100 pF for 90/120/150 nS (Including Jig and Scope) Input Test Point 3.0V 1.5V Output Test Point 1.5V 0V - 10 - W29EE012 Read Cycle Timing Parameters (VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. W29EE012 MIN. MAX. 150 150 70 45 45 - UNIT Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #CE Low to Active Output #OE Low to Active Output #CE High to High-Z Output #OE High to High-Z Output Output Hold from Address Change TRC TCE TAA TOE TCLZ TOLZ TCHZ TOHZ TOH 150 0 0 0 nS nS nS nS nS nS nS nS nS Byte/Page-Write Cycle Timing Parameters PARAMETER Write Cycle (Erase and Program) Address Setup Time Address Hold Time #WE and #CE Setup Time #WE and #CE Hold Time #OE High Setup Time #OE High Hold Time #CE Pulse Width #WE Pulse Width #WE High Width Data Setup Time Data Hold Time Byte Load Cycle Time Byte Load Cycle Time-out SYMBOL TWC TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBLC TBLCO MIN. 0 50 0 0 10 10 70 70 150 50 10 0.22 300 TYP. MAX. 10 200 UNIT mS nS nS nS nS nS nS nS nS nS nS nS µS µS Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 11 - Publication Release Date: March 26, 2002 Revision A3 W29EE012 Data Polling and Toggle Bit Timing Parameters PARAMETER SYM. W29EE012-90 W29EE012-12 W29EE012-15 MIN. #OE to Data Polling Output Delay #CE to Data Polling Output Delay #OE to Toggle Bit Output Delay #CE to Toggle Bit Output Delay TOEP TCEP TOET TCET MAX. 45 90 45 90 MIN. MAX. 60 120 60 120 MIN. MAX. 70 150 70 150 nS nS nS nS UNIT TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A16-0 #CE TCE #OE TOE VIH #WE TOLZ T OHZ TCLZ High-Z TOH Data Valid TAA T CHZ High-Z Data Valid DQ7-0 - 12 - W29EE012 Timing Waveforms, continued #WE Controlled Write Cycle Timing Diagram TBLCO TAS Address A16-0 TAH T WC #CE TCS TOES TCH T OEH #OE TWP TWPH #WE TDS DQ7-0 Data Valid TDH Internal write starts #CE Controlled Write Cycle Timing Diagram TAS TBLCO T AH T WC Address A16-0 T CPH T CP #CE T OES #OE #WE T DS DQ7-0 High Z Data Valid T OEH T DH Internal Write Starts - 13 - Publication Release Date: March 26, 2002 Revision A3 W29EE012 Timing Waveforms, continued Page Write Cycle Timing Diagram TWC Address A16-0 DQ7-0 #CE #OE TWP #WE Byte 0 T WPH TBLC TBLCO Byte 1 Byte 2 Byte N-1 Internal Write Start Byte N #DATA Polling Timing Diagram Address A16-0 #WE TCEP #CE TOEH #OE TOEP DQ7-0 X X TWC X X TOES - 14 - W29EE012 Timing Waveforms, continued Toggle Bit Timing Diagram Address A16-0 #WE #CE TOEH #OE TOES DQ6 TWC Page Write Timing Diagram Software Data Protection Mode Three-byte sequence for software data protection mode Address A16-0 5555 2AAA 5555 Byte/page load cycle starts TWC DQ6 AA 55 A0 #CE #OE #WE TWP TWPH TBLC TBLCO SW0 SW1 SW2 Byte 0 Byte N-1 Byte N (last byte) Internal write starts - 15 - Publication Release Date: March 26, 2002 Revision A3 W29EE012 Timing Waveforms, continued Reset Software Data Protection Timing Diagram Six-byte sequence for resetting software data protection mode Address A16-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ7-0 AA 55 80 AA 55 20 #CE #OE #WE TWP TWPH SW0 TBLC TBLCO SW1 SW2 SW3 SW4 SW5 Internal programming starts 5 Volt-Only Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A16-0 5555 2AAA 5555 5555 2AAA 5555 TWC DQ7-0 AA 55 80 AA 55 10 #CE #OE #WE TWP TWPH SW0 TBLC TBLCO SW1 SW2 SW3 SW4 SW5 Internal programming starts - 16 - W29EE012 ORDERING INFORMATION PART NO. ACCESS POWER SUPPLY STANDBY VDD TIME CURRENT MAX. CURRENT MAX. (nS) (mA) (µA) 50 100 PACKAGE HARDWARE SID READ FUNCTION Y W29EE012 Notes: - 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. In Hardware SID Read column: Y = with SID read function; N = without SID read function. - 17 - Publication Release Date: March 26, 2002 Revision A3 W29EE012 BONDING PAD DIAGRAM 6 A6 6 A5 7 A4 5 4 4 3 2 1 33s 33s 32 31 30 -2 -1 Vcc Vcc Vcc #WE A14 29 28 A13 A8 27 A9 26 A11 A7 A12 A15 A16 Y X 9 A3 10 RA8014 A2 11 A1 12 13 14 15 16 17s 17s -1 -2 18 19 20 21 22 25 #OE 24 A10 23 GND A0 DQ0 DQ1 DQ2 GND GND DQ3 DQ4 DQ5 DQ6 DQ7 #CE PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17S-1 17S-2 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33S-1 33S-2 X -187.04 -380.84 -517.64 -1121.73 -1258.52 -1484.75 -1484.75 -1484.75 -1453.92 -1453.92 -1453.92 -1240.62 -977.19 -727.22 -504.26 -264.72 -86.90 -1.70 286.06 509.01 758.98 981.94 1231.90 1469.29 1468.29 1469.29 1476.60 1476.60 1476.60 1311.85 891.00 523.36 310.36 180.16 94.96 Y 1920.30 1920.30 1920.30 1920.30 1920.30 1901.22 1713.42 1576.62 -1577.46 -1742.70 -1879.50 -1923.06 -1921.98 -1921.98 -1921.98 -1900.20 -1900.20 -1900.20 -1909.98 -1909.98 -1909.98 -1909.98 -1909.98 -1897.26 -1708.32 -1571.52 1564.62 1752.42 1889.22 1920.30 1920.30 1920.30 1914.24 1914.24 1914.24 Note: For bare chip form (C.O.B.) applications, the substrate must be connected to VDD or left floating in the PCB layout. - 18 - W29EE012 VERSION HISTORY VERSION A1 A2 A3 DATE Jan. 1997 Apr. 2000 Mar. 26, 2002 PAGE 10 1, 17, 19, 20 1,11 4, 17 4 18 Initial Issued Modify VIH/VIL = 0V/3V and VOH/VOL = 1.5V/1.5V Delete Package Description Delete Access Time Add in Hardware SID Read function note Modify VDD Power Up/Down Detection in Hardware Data Protection Add Bonding Pad Diagram DESCRIPTION Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 19 - Publication Release Date: March 26, 2002 Revision A3