W39L512

W39L512 64K × 8 CMOS FLASH MEMORY 1. GENERAL DESCRIPTION The W39L512 is a 512Kbit, 3.3-volt only CMOS flash memory organized as 64K × 8 bits. For flexible erase capability, the 512Kbits of data are divided into 16 small even pages with 4 Kbytes. The bytewide (× 8) data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39L512 results in fast program/erase operations with extremely low current consumption (compared to other comparable 3.3-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers. 2. FEATURES • Single 3.3-volt operations − 3.3-volt Read − 3.3-volt Erase − 3.3-volt Program • Flexible 4K-page size can be used as Parameter Blocks − 1K/10K • Typical program/erase cycles: • Twenty-year data retention • Low power consumption • Fast Program operation: − Byte-by-Byte programming: 50 µS (max.) Fast Erase operation: 100 mS (max.) 16 even pages with 4K bytes Any individual page can be erased − Optional 8K byte Top/Bottom Boot Block with lockout protection • − Active current: 10 mA (typ.) − Standby current: 15 µA (typ.) • End of program detection • Read access time: 70/90 nS • • − Software method: Toggle bit/Data polling • TTL compatible I/O • JEDEC standard byte-wide pinouts • Available packages: 32-pin PLCC and • Hardware protection: 32-pin STSOP (8 x 14 mm) -1- Publication Release Date: July 9, 2002 Revision A2 W39L512 3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM VDD VSS A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 V ND CD 1 # WN EC A 1 5 3 N C #CE #OE #WE 29 28 27 A14 A13 A8 A9 A11 #OE A10 #CE DQ7 CONTROL OUTPUT BUFFER DQ0 . . DQ7 2 32 31 30 32-pin PLCC 26 25 24 23 22 21 A0 . . A15 DECODER CORE ARRAY D Q 1 D Q 2 VD SQ S3 D Q 4 D Q 5 D Q 6 A11 A9 A8 A13 A14 NC #WE VDD NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 V SS DQ2 DQ1 DQ0 A0 A1 A2 A3 5. PIN DESCRIPTION SYMBOL A0 − A15 DQ0 − DQ7 #CE #OE #WE VDD VSS NC PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connections 32-pin STSOP 26 25 24 23 22 21 20 19 18 17 -2- W39L512 6. FUNCTIONAL DESCRIPTION Device Bus Operation Read Mode The read operation of the W39L512 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details. Write Mode Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to bring #WE to logic low state, while #CE is at logic low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE, whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Standby Mode There are two ways to implement the standby mode on the W39L512 device, both using the #CE pin. A CMOS standby mode is achieved with the #CE input held at VDD ±0.3V. Under this condition the current is typically reduced to less than 20 µA. A TTL standby mode is achieved with the #CE pin held at VIH. Under this condition the current is typically reduced to 2 mA. In the standby mode the outputs are in the high impedance state, independent of the #OE input. Output Disable Mode W ith the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. Auto-select Mode The auto-select mode allows the reading of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are don′t cares except A0 and A1 (see "Auto-select Codes"). -3- Publication Release Date: July 9, 2002 Revision A2 W39L512 The manufacturer and device codes may also be read via the command register, for instance, when the W39L512 is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "Auto-select Codes". Byte 0 (A0 = VIL) represents the manufacturer′s code (Winbond = DAH) and byte 1 (A0 = VIH) the device identifier code (W39L512 = 38H). All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Auto-select, A1 must be low state. Data Protection The W39L512 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise. Boot Block Operation There are two alternatives to set the boot block. The 8K-byte in the top/bottom location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 8K bytes or first 8K bytes of the memory with the address range from E000(hex) to FFFF(hex) for top location or 0000(hex) to 1FFF(hex) for bottom location. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. In order to detect whether the boot block feature is set on the first/last 8K-byte block or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 0002(hex) for first(bottom) location or FFF2(hex) for last(top) location. If the DQ0/DQ1 of output data is "1," the 8Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 of output data is "0," the lockout feature will be inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. Low VDD Inhibit To avoid initiation of a write cycle during VDD power-up and power-down, the W39L512 locks out when VDD < 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited when VDD is less than 2.0V typical. The W39L512 ignores all write and read operations until VDD > 2,0V. The user must ensure that the control pins are in the correct logic state when VDD > 2.0V to prevent unintentional writes. Write Pulse "Glitch" Protection Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle. -4- W39L512 Logical Inhibit Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle #CE and #WE must be a logical zero while #OE is a logical one. Power-up Write Inhibit Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state machine is automatically reset to the read mode on power-up. Command Definitions Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "Command Definitions" defines the valid register command sequences. Read Command The device will automatically power-up in the read state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. The device will automatically returns to read state after completing an Embedded Program or Embedded Erase algorithm. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Auto-select Command Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice. The device contains an auto-select command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39L512 = 38H). To terminate the operation, it is necessary to write the auto-select exit command sequence into the register. Byte Program Command The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm. -5- Publication Release Date: July 9, 2002 Revision A2 W39L512 Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. Programming is allowed in any sequence and across page boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only erase operations can convert "0"s to "1"s. Refer to the Programming Command Flow Chart using typical command strings and bus operations. Chip Erase Command Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically erase and verify the entire memory for an all one data pattern. The erase is performed sequentially on each pages at the same time (see "Feature"). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data on DQ7 is "1" at which time the device returns to read the mode. Refer to the Erase Command Flow Chart using typical command strings and bus operations. Page Erase Command Page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the page erase command. The page address (any address location within the desired page) is latched on the falling edge of #WE, while the command (50H) is latched on the rising edge of #WE. Page erase does not require the user to program the device prior to erase. When erasing a page, the remaining unselected pages are not affected. The system is not required to provide any controls or timings during these operations. The automatic page erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last page erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the pages being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations. -6- W39L512 Write Operation Status DQ7: Data Polling The W39L512 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a "1" at the DQ7 output. For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write pulse sequences. For page erase, the Data Polling is valid after the last rising edge of the page erase #WE pulse. Data Polling must be performed at addresses within any of the pages being erased. Otherwise, the status may not be valid. Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (#OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte′s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 – DQ6 may be still invalid. The valid data on DQ0 − DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or page erase time-out (see "Command Definitions"). DQ6: Toggle Bit The W39L512 also features the "Toggle Bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth #WE pulse in the six write pulse sequence. For page erase, the Toggle Bit is valid after the last rising edge of the page erase #WE pulse. The Toggle Bit is active during the page erase time-out. Either #CE or #OE toggling will cause DQ6 to toggle. -7- Publication Release Date: July 9, 2002 Revision A2 W39L512 7. TABLE OF OPERATING MODES Device Bus Operations (VID = 12 ±0.5V) MODE #CE Read Write Standby Write Inhibit Output Disable Auto select Manufacturers ID Auto select Device ID VIL VIL VIH X X PIN #OE #WE VIL VIH X VIL X A0 A0 A0 X X X X VIL VIH A1 A1 A1 X X X X VIL VIL A9 A9 A9 X X X X VID VID DQ0 − DQ7 Dout Din High Z High Z/Dout High Z/Dout VIH VIL X X VIH VIH VIH VIH VIL VIL VIL VIH VIL VIL High Z DA(hex) 38h Auto-select Codes (High Voltage Method) (VID = 12 ±0.5V) DESCRIPTION Manufacturer ID: Winbond Device ID: W39L512 #CE VIL VIL #OE VIL VIL #WE VIH VIH A9 VID VID THE OTHER ADDRESS All Add = VIL A1= VIH, All other = VIL DQ[7:0] DA(hex) 38h -8- W39L512 Command Definitions COMMAND DESCRIPTION Read Chip Erase Page Erase Byte Program Top Boot Block Lockout –8KByte Bottom Boot Block Lockout - 8KByte Product ID Entry Product ID Exit (2) Product ID Exit (2) NO. OF Cycles 1 6 6 4 6 6 3 3 1 1ST CYCLE Addr. (1)Data AIN 5555 5555 5555 5555 5555 5555 5555 XXXX DOUT AA AA AA AA AA AA AA F0 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 55 55 5555 5555 5555 5555 5555 5555 5555 80 80 A0 80 80 90 F0 5555 5555 AIN 5555 5555 AA AA DIN AA AA 2AAA 2AAA 55 55 5555 5555 70 70 FFFF 00000 XX(4) XX(4) 2AAA 2AAA 55 55 5555 PA(3) 10 50 2ND CYCLE Addr. Data 3RD CYCLE Addr. Data 4TH CYCLE Addr. Data 5TH CYCLE Addr. Data 6TH CYCLE Addr. Data 7TH CYCLE Addr. Data Notes: 1. Address Format: A15 − A0 (Hex); Data Format: DQ7 − DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. PA: Page Address PA = FXXXh for Page 15 PA = EXXXh for Page 14 PA = DXXXh for Page 13 PA = CXXXh for Page 12 PA = BXXXh for Page 11 PA = AXXXh for Page 10 PA = 9XXXh for Page 9 PA = 8XXXh for Page 8 PA = 7XXXh for Page 7 PA = 6XXXh for Page 6 PA = 5XXXh for Page 5 PA = 4XXXh for Page 4 PA = 3XXXh for Page 3 PA = 2XXXh for Page 2 PA = 1XXXh for Page 1 PA = 0XXXh for Page 0 4. XX: Don't care -9- Publication Release Date: July 9, 2002 Revision A2 W39L512 Embedded Programming Algorithm Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit Pause T BP No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 10 - W39L512 Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Successfully Completed Pause T EC /TPEC Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Page Erase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Page Address/50H - 11 - Publication Release Date: July 9, 2002 Revision A2 W39L512 Embedded #Data Polling Algorithm Start VA = Byte address for programming = Any of the page addresses within the page being erased during page erase operation =Any of the device addresses being erased during chip operation Read Byte (DQ0 - DQ7) Address = VA No DQ7 = Data ? Yes Pass Embedded Toggle Bit Algorithm Start Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 12 - W39L512 Boot Block Lockout Enable Flow Chart Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Pause 2 mS Load data 80 to address 5555 Exit Load data AA to address 5555 Load data 55 to address 2AAA Load data 70 to address 5555 Load data XX to 70 to lcok 8K Boot Block address FFFF/0 h FFFF(XX) to lock Top Boot Block 0000(XX) to lock Bottom Boot Block - 13 - Publication Release Date: July 9, 2002 Revision A2 W39L512 Software Product Identification and Boot Block Lockout Detection Flow Chart Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Mode (3) Detection Product Identification Exit(6) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 0000 data = DA Load data 55 to address 2AAA Load data 90 to address 5555 Read address = 0001 data = 38 (2) Load data F0 to address 5555 Pause 10 µ S Read address= 02/FFF2 for Bottom/Top data: in DQ1 = "1" or "0" for 8K Boot Block (4) Pause 10 µS (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7 − DQ0 (Hex); Address Format: A15 − A0 (Hex) (2) A1 − A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0 or DQ1= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0 or DQ1= " 0," the lockout feature is inactivated and the matched boot block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 14 - W39L512 8. DC CHARACTERISTICS Absolute maximum Ratings PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature Voltage on Any Pin to Ground Potential Except A9 Voltage on A9 Pin to Ground Potential RATING -2.0 to +4.6 0 to +70 -65 to +125 -2.0 to +4.6 -2.0 to +13.0 UNIT V °C °C V V Note: Exposure to conditions beyond those listed under Absolute maximum Ratings may adversely affect the life and reliability of the device. DC Operating Characteristics (VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. TEST CONDITIONS #CE = #OE = VIL, #WE = VIH, all DQs open, Address inputs = VIL/ VIH, at f = 5 MHz #CE = VIH, all DQs open Other inputs = VIL/VIH #CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/ VSS VIN = VSS to VDD VOUT = VSS to VDD IOL = 2.1 mA IOH = -0.4 mA LIMITS MIN. TYP. MAX. 20 UNIT mA Power Supply Current Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IDD ISB1 - 10 -0.3 2.0 2.4 1 15 - 2 50 1 1 0.8 VDD +0.5 0.45 - mA µA µA µA V V V V ISB2 ILI ILO VIL VIH VOL VOH Pin Capacitance (VDD = 3.3V, TA = 25° C, f = 1 MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT CONDITIONS VIN = 0V VOUT = 0V TYP. 6 10 MAX. 8 12 UNIT pF pF - 15 - Publication Release Date: July 9, 2002 Revision A2 W39L512 9. AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 3V