W39V040BQ

W39V040B Data Sheet 512K × 8 CMOS FLASH MEMORY WITH LPC INTERFACE Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS............................................................................................................. 4 BLOCK DIAGRAM ...................................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 4 FUNCTIONAL DESCRIPTION.................................................................................................... 5 6.1 Interface Mode Selection and Description......................................................................... 5 6.2 Read (Write) Mode ............................................................................................................ 5 6.3 Reset Operation................................................................................................................. 5 6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP ........................... 5 6.5 Sector Erase Command .................................................................................................... 5 6.6 Program Operation ............................................................................................................ 6 6.7 Hardware Data Protection ................................................................................................. 6 6.8 WRITE OPERATION STATUS.......................................................................................... 6 REGISTER FOR LPC MODE ..................................................................................................... 8 7.1 General Purpose Inputs Register for LPC Mode ............................................................... 8 7.2 Identification Input Pins ID[3:0] .......................................................................................... 8 7.3 Product Identification Registers......................................................................................... 8 TABLE OF OPERATING MODES .............................................................................................. 9 8.1 Operating Mode Selection - Programmer Mode................................................................ 9 8.2 Operating Mode Selection - LPC Mode............................................................................. 9 8.3 LPC Cycle Definition.......................................................................................................... 9 TABLE OF COMMAND DEFINITION ....................................................................................... 10 9.1 Embedded Programming Algorithm ................................................................................ 11 9.2 Embedded Erase Algorithm............................................................................................. 12 9.3 Embedded #Data Polling Algorithm................................................................................. 13 9.4 Embedded Toggle Bit Algorithm...................................................................................... 14 9.5 Software Product Identification and Boot Block Lockout Detection Acquisition Flow ..... 15 ELECTRICAL CHARACTERISTICS......................................................................................... 16 10.1 Absolute Maximum Ratings......................................................................................... 16 10.2 Programmer interface Mode DC Operating Characteristics ....................................... 16 10.3 LPC Interface Mode DC Operating Characteristics .................................................... 17 10.4 Power-up Timing ......................................................................................................... 17 10.5 Capacitance................................................................................................................. 17 10.6 Programmer Interface Mode AC Characteristics ........................................................ 18 10.7 Read Cycle Timing Parameters .................................................................................. 19 Publication Release Date: April 14, 2005 Revision A3 7. 8. 9. 10. -1- W39V040B 10.8 10.9 11. Write Cycle Timing Parameters................................................................................... 19 Data Polling and Toggle Bit Timing Parameters ......................................................... 19 TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE ....................................... 20 11.1 Read Cycle Timing Diagram ....................................................................................... 20 11.2 Write Cycle Timing Diagram........................................................................................ 20 11.3 Program Cycle Timing Diagram .................................................................................. 21 11.4 #DATA Polling Timing Diagram................................................................................... 21 11.5 Toggle Bit Timing Diagram.......................................................................................... 22 11.6 Sector Erase Timing Diagram ..................................................................................... 22 LPC INTERFACE MODE AC CHARACTERISTICS................................................................. 23 12.1 AC Test Conditions ..................................................................................................... 23 12.2 Read/Write Cycle Timing Parameters......................................................................... 23 12.3 Reset Timing Parameters............................................................................................ 23 TIMING WAVEFORMS FOR LPC INTERFACE MODE........................................................... 24 13.1 Read Cycle Timing Diagram ....................................................................................... 24 13.2 Write Cycle Timing Diagram........................................................................................ 24 13.3 Program Cycle Timing Diagram .................................................................................. 25 13.4 #DATA Polling Timing Diagram................................................................................... 26 13.5 Toggle Bit Timing Diagram.......................................................................................... 27 13.6 Sector Erase Timing Diagram ..................................................................................... 28 13.7 FGPI Register/Product ID Readout Timing Diagram .................................................. 29 13.8 Reset Timing Diagram................................................................................................. 29 ORDERING INFORMATION..................................................................................................... 30 HOW TO READ THE TOP MARKING...................................................................................... 30 PACKAGE DIMENSIONS ......................................................................................................... 31 16.1 32L PLCC .................................................................................................................... 31 16.2 32L STSOP ................................................................................................................. 31 VERSION HISTORY ................................................................................................................. 32 12. 13. 14. 15. 16. 17. -2- Publication Release Date: April 14, 2005 Revision A3 W39V040B 1. GENERAL DESCRIPTION The W39V040B is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is required for accelerated program. The unique cell architecture of the W39V040B results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode, Low pin count (LPC) bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also be programmed and erased using standard EPROM programmers. 2. FEATURES • Single 3.3-volt operations: − 3.3-volt Read − 3.3-volt Erase − 3.3-volt Program Fast Program operation: − Byte-by-Byte programming: 9 µS (typ.) (VPP = 12V) − Byte-by-Byte programming: 12 µS (typ.) (VPP = Vcc) Fast Erase operation: − Sector erase 0.6 Sec. (typ.) Fast Read access time: Tkq 11 nS Endurance: 10K cycles (typ.) Twenty-year data retention 8 Even sectors with 64K bytes Any individual sector can be erased • • Hardware protection: − #TBL supports 64-Kbyte Boot Block hardware protection − #WP supports the whole chip except Boot Block hardware protection Low power consumption − Active current: 15 mA (typ. for LPC read mode) Automatic program and erase timing with internal VPP generation End of program or erase detection − Toggle bit − Data polling Latched address and data TTL compatible I/O Available packages: 32L PLCC, 32L STSOP 32L PLCC Lead free, 32L STSOP Lead free • • • • • • • • • • • • -3- Publication Release Date: April 14, 2005 Revision A3 W39V040B 3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM #WP #TBL CLK LAD[3:0] #LFRAM MODE #INIT #RESET R/#C A[10:0] DQ[7:0] NC NC NC VSS MODE A10(FGPI4) R/#C(CLK) V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 #OE(#INIT) #WE(#LFRAM RY/#BY(RSV) DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) DQ3(LAD3) VSS DQ2(LAD2) DQ1(LAD1) DQ0(LAD0) A0(ID0) A1(ID1) A2(ID2) A3(ID3) LPC Interface 64K BYTES BLOCK 7 64K BYTES BLOCK 6 64K BYTES BLOCK 5 64K BYTES BLOCK 4 64K BYTES BLOCK 3 Programmer Interface 64K BYTES BLOCK 2 64K BYTES BLOCK 1 64K BYTES BLOCK 0 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 #OE #WE RY/#BY Vpp 32L STSOP #RESET A9(FGPI3) A8(FGPI2) A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) 5. PIN DESCRIPTION SYM. INTERFACE PGM LPC * * * * * * * * * * * * * * * * * * * * * * * PIN NAME Interface Mode Selection Reset Initialize Top Boot Block Lock Write Protect CLK Input General Purpose Inputs Identification Inputs They Are Internal Pull Down to Vss Address/Data Inputs LPC Cycle Initial Row/Column Select Address Inputs Data Inputs/Outputs Output Enable Write Enable Ready/ Busy Power Supply Ground Accelerate Program Power Supply Reserved Pins No Connection A 8 ^ F G P I 2 v 4 A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) A3(ID3) A2(ID2) A1(ID1) A0(ID0) DQ0(LAD0) 5 6 7 8 9 10 11 12 13 14 D Q 1 L^ A D 1 v A 9 ^ F G P I 3 v 3 # R E S E T 2 V P P 1 V D D 32 R / # C ^ C L K v 31 A 1 0 ^ F G P I 4 v 30 29 28 27 26 MODE V SS NC NC MODE #RESET #INIT #TBL #WP CLK FGPI[4:0] ID[3:0] LAD[3:0] #LFRAM R/#C A[10:0] DQ[7:0] #OE #WE RY/#BY VDD VSS VPP RSV NC 32L PLCC 25 24 23 22 21 V DD #OE(#INIT) #WE(#LFRAM) RY/#BY(RSV) DQ7(RSV) 15 D Q 2 ^ L A D 2 v 16 V S S 17 D Q 3 ^ L A D 3 v 18 D Q 4 ^ R S V v 19 D Q 5 ^ R S V v 20 D Q 6 ^ R S V v * * * * * -4- Publication Release Date: April 14, 2005 Revision A3 W39V040B 6. FUNCTIONAL DESCRIPTION 6.1 Interface Mode Selection and Description This device can operate in two interface modes, one is Programmer interface mode, and the other is LPC interface mode. The Mode pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When ic (Mode) pin is set to VDD, the device will be in the Programmer mode; while the Mode pin is set to low state (or leaved no connection), it will be in the LPC mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column address are mapped to the lower internal address A[10:0]. For LPC mode, it complies with the LPC Interface Specification, through the LAD[3:0] to communicate with the system chipset . 6.2 Read (Write) Mode In Programmer interface mode, the read (write) operation of the W39V040B is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As for in the LPC interface mode, the read or write is determined by the "START CYCLE ". Refer to the LPC cycle definition and timing waveforms for further details. 6.3 Reset Operation The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals. 6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP There is a hardware method to protect the top boot block and other sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased. In order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 7FFF2(hex). You can check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is “0”, it means the #TBL pin is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is “1”, it means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it means the #WP pin is in high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if the DQ3 is “1”, then all the sectors except the boot block are programmed/erased inhibited. To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. 6.5 Sector Erase Command Sector erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the Sector erase command. The Publication Release Date: April 14, 2005 Revision A3 -5- W39V040B Sector address (any address location within the desired Sector) is latched on the rising edge of R/#C in programmer mode, while the command (30H) is latched on the rising edge of #WE. Sector erase does not require the user to program the device prior to erase. When erasing a Sector, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic Sector erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last Sector erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations. 6.6 Program Operation The W39V040B is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byte-program command is entered. The internal program timer will automatically time-out (9µS typ. TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. 6.7 Hardware Data Protection The integrity of the data stored in the W39V040B is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 5 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 2.0V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. 6.8 WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY in programmer mode, to determine whether an Embedded Program or Erase operation is in progress or has been completed. DQ7: #Data Polling The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. Once the Embedded Program algorithm has completed, the device outputs the data programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1µS, and then the device returns to the read mode. During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded Publication Release Date: April 14, 2005 Revision A3 -6- W39V040B Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7. Just before the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. RY/#BY: Ready/#Busy The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to VDD. When the output is low (Busy), the device is actively erasing or programming. When the output is high (Ready), the device is in the read mode or standby mode. DQ6: Toggle Bit Toggle Bit on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE to control the read cycles. Once the operation has completed, DQ6 stops toggling. The system can use DQ6 to determine whether a sector is actively erasing. If the device is actively erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address falls within a protected sector, DQ6 toggles for about 1 µs after the program command sequence is written, and then returns to reading array data. DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not successfully completed. The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.” Under both these conditions, the system must write the reset command to return to the read mode. Multi-Chip Operation Multiple devices can be wired on the single LPC bus. There are four ID pins can be used to support up to 16 devices. But in order not to violate the BIOS ROM memory space defined by Intel, Winbond W39V040A will only used 3 ID pins to allow up to 8 devices, 4Mbytes for BIOS code and 4Mbytes for registers memory space. -7- Publication Release Date: April 14, 2005 Revision A3 W39V040B 7. REGISTER FOR LPC MODE There are two kinds of registers on this device, the General Purpose Input Registers and Product Identification Registers. Users can access these registers through respective address in the 4Gbytes memory map. There are detail descriptions in the sections below. 7.1 General Purpose Inputs Register for LPC Mode This register reads the FGPI[4:0] pins on the W39V040B.This is a pass-through register which can read via memory address FBC0100(hex). Since it is pass-through register, there is no default value. GPI Register Table BIT FUNCTION 7−5 4 3 2 1 0 Reserved Read FGPI4 pin status Read FGPI3 pin status Read FGPI2 pin status Read FGPI1 pin status Read FGPI0 pin status 7.2 Identification Input Pins ID[3:0] These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot device should be 0000b. And all the subsequent parts should use the up-count strapping. Note that a 1M byte ROM will occupy two Ids. For example: a 1MByte ROM's ID is 0000b, the next ROM's ID is 0010b. These pins all are pulled down with internal resistor. 7.3 Product Identification Registers In the LPC interface mode, a read from FBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FBC, 0001(hex) can output the device code 54(hex). There is an alternative software method (six commands bytes) to read out the Product Identification in both the Programmer interface mode and the LPC interface mode. Thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms. In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 54(hex). The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table for detail). -8- Publication Release Date: April 14, 2005 Revision A3 W39V040B 8. TABLE OF OPERATING MODES 8.1 Operating Mode Selection - Programmer Mode MODE PINS #OE #WE #RESET ADDRESS DQ. Read Write Standby Write Inhibit Output Disable VIL VIH X VIL X VIH VIH VIL X X VIH X VIH VIH VIL VIH VIH VIH AIN AIN X X X X Dout Din High Z High Z/DOUT High Z/DOUT High Z 8.2 Operating Mode Selection - LPC Mode Operation modes in LPC interface mode are determined by "START Cycle" when it is selected. When it is not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "LPC Cycle Definition". 8.3 LPC Cycle Definition FIELD NO. OF CLOCKS DESCRIPTION Start Cycle Type & Dir TAR Addr. 1 1 2 8 "0000b" appears on LPC bus to indicate the initial "010Xb" indicates memory read cycle; while "011xb" indicates memory write cycle. "X" mean don't have to care. Turned Around Time Address Phase for Memory Cycle. LPC supports the 32 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.) Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, other values are reserved. Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first, then DQ[7:4] on LAD[3:0] last.) Sync. N Data 2 -9- Publication Release Date: April 14, 2005 Revision A3 W39V040B 9. TABLE OF COMMAND DEFINITION COMMAND DESCRIPTION Read Sector Erase Byte Program Product ID Entry Product ID Exit Product ID Exit Notes: 1. The cycle means the write command cycle not the LPC clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11] 3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector Address SA = 7XXXXh for Unique Sector7 (Boot Sector) SA = 6XXXXh for Unique Sector6 SA = 5XXXXh for Unique Sector5 SA = 4XXXXh for Unique Sector4 SA = 3XXXXh for Unique Sector3 SA = 2XXXXh for Unique Sector2 SA = 1XXXXh for Unique Sector1 SA = 0XXXXh for Unique Sector0 (4) (4) NO. OF Cycles (1) 1 6 4 3 3 1 1ST CYCLE Addr. Data AIN 5555 5555 5555 5555 XXXX DOUT AA AA AA AA F0 2ND CYCLE Addr. Data 3RD CYCLE Addr. Data 4TH CYCLE Addr. Data 5TH CYCLE Addr. Data 6TH CYCLE Addr. Data (5) 2AAA 2AAA 2AAA 2AAA 55 55 55 55 5555 5555 5555 5555 80 A0 90 F0 5555 AIN AA DIN 2AAA 55 SA 30 - 10 - Publication Release Date: April 14, 2005 Revision A3 W39V040B 9.1 Embedded Programming Algorithm Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 11 - Publication Release Date: April 14, 2005 Revision A3 W39V040B 9.2 Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H Sector Address/30H - 12 - Publication Release Date: April 14, 2005 Revision A3 W39V040B 9.3 Embedded #Data Polling Algorithm Start Read Byte (DQ0 - DQ7) Address = SA DQ7 = Data ? No No Yes DQ5 = 1 Yes Read Byte (DQ0 - DQ7) Address = SA Yes DQ7 = Data No Fail Pass Note: SA = Valid address for programming .During a sector erase operation, a valid address is an address within any sector selected for erasure. - 13 - Publication Release Date: April 14, 2005 Revision A3 W39V040B 9.4 Embedded Toggle Bit Algorithm Start Read Byte (DQ0-DQ7) Read Byte (DQ0-DQ7) No Toggle Bit =Toggle ? Yes No DQ5 = 1 ? Yes Read Byte (DQ0-DQ7) twin No Toggle Bit =Toggle ? Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation complete Note: Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. - 14 - Publication Release Date: April 14, 2005 Revision A3 W39V040B 9.5 Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Identification and Boot Block Lockout Detection Mode (3) Product Product Identification Exit(6) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 00000 data = DA Load data 55 to address 2AAA Load data 90 to address 5555 Read address = 00001 data = 54 (2) Load data F0 to address 5555 Pause 10 µ S Read address = 7FFF2 Check DQ[3:0] of data outputs (4) Pause 10 µ S (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex) (2) A1−A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) The DQ[3:2] to indicate the sectors protect status as below: 0 1 DQ2 64Kbytes Boot Block Unlocked by #TBL hardware trapping 64Kbytes Boot Block Locked by #TBL hardware trapping DQ3 Whole Chip Unlocked by #WP hardware trapping Except Boot Block Whole Chip Locked by #WP hardware trapping Except Boot Block (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockout detection. - 15 - Publication Release Date: April 14, 2005 Revision A3 W39V040B 10. ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETER RATING UNIT Operating Temperature Storage Temperature Power Supply Voltage to VSS Potential D.C. Voltage on Any Pin to Ground Potential VPP Voltage Transient Voltage (