W39V040FAPZ

W39V040FA Data Sheet 512K × 8 CMOS FLASH MEMORY WITH FWH INTERFACE Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 4 2. FEATURES ................................................................................................................................. 4 3. PIN CONFIGURATIONS ............................................................................................................ 5 4. BLOCK DIAGRAM ...................................................................................................................... 5 5. PIN DESCRIPTION..................................................................................................................... 5 6. FUNCTIONAL DESCRIPTION ................................................................................................... 6 6.1 Interface Mode Selection and Description..................................................................... 6 6.2 Read (Write) Mode ........................................................................................................ 6 6.3 Reset Operation............................................................................................................. 6 6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP ....................... 6 6.5 Chip Erase Operation .................................................................................................... 7 6.6 Sector/Page Erase Command....................................................................................... 7 6.7 Program Operation ........................................................................................................ 7 6.8 Hardware Data Protection ............................................................................................. 8 6.9 Data Polling (DQ7)- Write Status Detection .................................................................. 8 6.10 Toggle Bit (DQ6)- Write Status Detection ..................................................................... 8 6.11 Register.......................................................................................................................... 8 6.12 Block Locking Registers ................................................................................................ 9 6.13 Read Lock.................................................................................................................... 10 6.14 Write Lock .................................................................................................................... 10 6.15 Lock Down ................................................................................................................... 10 6.16 Product Identification Registers................................................................................... 10 6.17 Table of Operating Mode ............................................................................................. 10 6.18 Table of Command Definition ...................................................................................... 11 6.19 FWH Cycle Definition................................................................................................... 12 6.20 Embedded Programming Algorithm ............................................................................ 13 6.21 Embedded Erase Algorithm......................................................................................... 14 6.22 Embedded #Data Polling Algorithm............................................................................. 15 6.23 Embedded Toggle Bit Algorithm.................................................................................. 15 6.24 Software Product Identification and Boot Block Lockout Detection Acquisition Flow . 16 6.25 Boot Block Lockout Enable Acquisition Flow .............................................................. 17 -1- Publication Release Date: April 14, 2005 Revision A6 W39V040FA 7. 8. 9. 10. 11. ELECTRICAL CHARACTERISTICS......................................................................................... 18 7.1 Absolute Maximum Ratings ......................................................................................... 18 7.2 Programmer interface Mode DC Operating Characteristics........................................ 18 7.3 FWH Interface Mode DC Operating Characteristics ................................................... 19 7.4 Power-up Timing.......................................................................................................... 19 7.5 Capacitance................................................................................................................. 19 PROGRAMMER INTERFACE MODE AC CHARACTERISTICS............................................. 20 8.1 AC Test Conditions...................................................................................................... 20 8.2 AC Test Load and Waveform ...................................................................................... 20 8.3 Read Cycle Timing Parameters................................................................................... 21 8.4 Write Cycle Timing Parameters................................................................................... 21 8.5 Data Polling and Toggle Bit Timing Parameters ......................................................... 21 TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE ....................................... 22 9.1 Read Cycle Timing Diagram........................................................................................ 22 9.2 Write Cycle Timing Diagram........................................................................................ 22 9.3 Program Cycle Timing Diagram .................................................................................. 23 9.4 #DATA Polling Timing Diagram................................................................................... 23 9.5 Toggle Bit Timing Diagram .......................................................................................... 24 9.6 Boot Block Lockout Enable Timing Diagram ............................................................... 24 9.7 Chip Erase Timing Diagram ........................................................................................ 25 9.8 Sector/Page Erase Timing Diagram ............................................................................ 25 FWH INTERFACE MODE AC CHARACTERISTICS ............................................................... 26 10.1 AC Test Conditions...................................................................................................... 26 10.2 Read/Write Cycle Timing Parameters ......................................................................... 26 10.3 Reset Timing Parameters ............................................................................................ 26 TIMING WAVEFORMS FOR FWH INTERFACE MODE.......................................................... 27 11.1 Read Cycle Timing Diagram........................................................................................ 27 11.2 Write Cycle Timing Diagram........................................................................................ 27 11.3 Program Cycle Timing Diagram .................................................................................. 28 11.4 #DATA Polling Timing Diagram................................................................................... 29 11.5 Toggle Bit Timing Diagram .......................................................................................... 30 11.6 Boot Block Lockout Enable Timing Diagram ............................................................... 31 11.7 Chip Erase Timing Diagram ........................................................................................ 32 11.8 Sector Erase Timing Diagram ..................................................................................... 33 11.9 Page Erase Timing Diagram ....................................................................................... 34 11.10 FGPI Register/Product ID Readout Timing Diagram................................................... 35 -2- W39V040FA 11.11 Reset Timing Diagram ................................................................................................. 35 12. 13. ORDERING INFORMATION .............................................................................................. 36 13. HOW TO READ THE TOP MARKING...................................................................................... 36 14. PACKAGE DIMENSIONS ......................................................................................................... 37 14.1 32L PLCC .................................................................................................................... 37 15. 14.2 32L STSOP.................................................................................................................. 37 14.3 40L TSOP (10 mm x 20 mm)....................................................................................... 38 VERSION HISTORY ................................................................................................................. 39 -3- Publication Release Date: April 14, 2005 Revision A6 W39V040FA 1. GENERAL DESCRIPTION The W39V040FA is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased insystem with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39V040FA results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification. The device can also be programmed and erased using standard EPROM programmers. 2. FEATURES • − #TBL & #WP support the whole chip hardware protection Single 3.3-volt operations: − 3.3-volt Read − 3.3-volt Erase − 3.3-volt Program • Fast Program operation: − Byte-by-Byte programming: 35 μS (typ.) • Fast Erase operation: − Chip erase 100 mS (max.) − Sector erase 25 mS (max.) − Page erase 25 mS (max.) • Flexible 4K-page size can be used as Parameter Blocks • Low power consumption − Active current: 12.5 mA (typ. for FWH mode) • Automatic program and erase timing with internal VPP generation • End of program or erase detection − Toggle bit • Fast Read access time: Tkq 11 nS • Endurance: 10K cycles (typ.) • Latched address and data • Twenty-year data retention • TTL compatible I/O • 8 Even sectors with 64K bytes each, which is composed of 16 flexible pages with 4K bytes • • Any individual sector or page can be erased • Hardware protection: Available packages: 32L PLCC, 32L STSOP, 40L TSOP (10 x 20 mm), 32L PLCC Lead free, 32L STSOP Lead free and 40L TSOP (10 x 20 mm) Lead free − Data polling − Optional 16K byte or 64K byte Top Boot Block with lockout protection -4- W39V040FA 3. PIN CONFIGURATIONS A 8 ^ F G P I 2 v A 9 ^ F G P I 3 v # R E S V E N D T C D 4 3 2 R / # C ^ C L K v 4. BLOCK DIAGRAM 7FFFF #WP #TBL CLK FWH[3:0] FWH4 A 1 0 ^ F G P I 4 v BOOT BLOCK 64K BYTES FWH Interface MAIN MEMORY BLOCK6 64K BYTES MAIN MEMORY BLOCK5 64K BYTES IC #INIT MAIN MEMORY BLOCK4 64K BYTES #RESET 1 32 31 30 A7(FGPI1) 5 29 A6(FGPI0) 6 28 VSS A5(#WP) 7 27 NC A4(#TBL) 8 26 NC A3(ID3) A2(ID2) 32L PLCC 9 25 MAIN MEMORY BLOCK3 64K BYTES R/#C IC A[10:0] DQ[7:0] MAIN MEMORY BLOCK2 64K BYTES Programmer Interface MAIN MEMORY BLOCK1 64K BYTES #OE VDD 10 24 #OE(#INIT) A1(ID1) 11 23 #WE(FWH4) A0(ID0) 12 22 NC DQ0(FWH0) 13 21 DQ7(RSV) #WE MAIN MEMORY BLOCK0 64K BYTES 70000 6FFFF Optional 16KBytes as Boot Block 4K Page 7FFFF 4K Page 4K Page 4K Page 60000 5FFFF 4K Page 50000 4FFFF 4K Page 40000 3FFFF 4K Page 7C000 7BFFF 4K Page 4K Page 4K Page 30000 2FFFF 4K Page 4K Page 20000 1FFFF 4K Page 4K Page 10000 0FFFF 00000 4K Page 4K Page 70000 14 15 16 17 18 19 20 D Q 1 ^ F W H 1 v NC NC NC VSS IC A10(FGPI4) R/#C(CLK) VDD NC #RESET A9(FGPI3) A8(FGPI2) A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) NC IC NC NC NC NC A10(FGPI4) NC CLK VDD NC #RESET NC NC A9(FGPI3) A8(FGPI2) A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D V D D Q S Q Q 2 S 3 4 ^ ^ ^ F F R W W S H H V 2 3 v v v D Q 5 ^ R S V v 32L STSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 D Q 6 ^ R S V v 40L TSOP 5. PIN DESCRIPTION SYM. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 #OE(#INIT) #WE(FWH4) VDD DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) DQ3(FWH3) VSS DQ2(FWH2) DQ1(FWH1) DQ0(FWH0) A0(ID0) A1(ID1) A2(ID2) A3(ID3) 40 39 VSS VDD 38 37 36 35 34 33 32 31 30 29 28 27 26 #WE(FWH4) #OE(#INIT) NC 25 24 23 22 21 INTERFACE PIN NAME PGM FWH IC * * Interface Mode Selection #RESET * * Reset #INIT * Initialize #TBL * Top Boot Block Lock #WP * Write Protect CLK * CLK Input FGPI[4:0] * General Purpose Inputs ID[3:0] * Identification Inputs They Are Internal Pull Down to Vss FWH[3:0] * Address/Data Inputs FWH4 * FWH Cycle Initial DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) VDD VSS VSS DQ3(FWH3) DQ2(FWH2) DQ1(FWH1) DQ0(FWH0) A0(ID0) A1(ID1) A2(ID2) A3(ID3) -5- R/#C * Row/Column Select A[10:0] * Address Inputs DQ[7:0] * Data Inputs/Outputs #OE * Output Enable #WE * VDD * * Write Enable Power Supply VSS * * Ground RSV * * Reserved Pins NC * * No Connection Publication Release Date: April 14, 2005 Revision A6 W39V040FA 6. FUNCTIONAL DESCRIPTION 6.1 Interface Mode Selection and Description This device can operate in two interface modes, one is Programmer interface mode, and the other is FWH interface mode. The IC pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When IC pin is set to VDD, the device will be in the Programmer mode; while the IC pin is set to low state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column address are mapped to the lower internal address A[10:0]. For FWH mode, it complies with the FWH Interface Specification. Through the FWH[3:0] and FWH4 to communicate with the system chipset . 6.2 Read (Write) Mode In Programmer interface mode, the read (write) operation of the W39V040FA is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for further details. 6.3 Reset Operation The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals. 6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WP There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex). See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. Besides the software method, there is a hardware method to protect the top boot block and other sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased. In order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 7FFF2(hex). If the DQ0/DQ1 output data is "1," the 64Kbytes/16Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 output data is "0," the lockout feature will be inactivated and the boot block can be erased/programmed. But the hardware protection will override the software lock setting, i.e., while the #TBL pin is trapped at low state, the top boot block cannot be programmed/erased whether the output data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL will lock the whole 64Kbytes top boot block, it will not partially lock the 16Kbytes boot block. You can -6- W39V040FA check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is "0", it means the #TBL pin is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is "1", it means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is "0", it means the #WP pin is in high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if the DQ3 is "1", then all the sectors except the boot block are programmed/erased inhibited. To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. 6.5 Chip Erase Operation The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 100 mS (max). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory sectors will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. 6.6 Sector/Page Erase Command Sector/page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase command. The sector/page address (any address location within the desired sector/page) is latched on the falling edge of #WE, while the command (30H/50H) is latched on the rising edge of #WE. Sector/page erase does not require the user to program the device prior to erase. When erasing a sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector/page erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors/pages being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations. 6.7 Program Operation The W39V040FA is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (50 μS max. TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. -7- Publication Release Date: April 14, 2005 Revision A6 W39V040FA 6.8 Hardware Data Protection The integrity of the data stored in the W39V040FA is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 1.5V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. 6.9 Data Polling (DQ7)- Write Status Detection The W39V040FA includes a data polling feature to indicate the end of a program or erase cycle. When the W39V040FA is in the internal program or erase cycle, any attempts to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and when erase cycle has been completed it becomes logical "1" or true data. 6.10 Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W39V040FA provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 6.11 Register There are three kinds of registers on this device, the General Purpose Input Registers, the Block Lock Control Registers and Product Identification Registers. Users can access these registers through respective address in the 4Gbytes memory map. There are detail descriptions in the sections below. 6.11.1 General Purpose Inputs Register This register reads the FGPI[4:0] pins on the W39V040FA.This is a pass-through register which can read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value. GPI Register Table BIT 7−5 FUNCTION Reserved 4 Read FGPI4 pin status 3 Read FGPI3 pin status 2 Read FGPI2 pin status 1 Read FGPI1 pin status 0 Read FGPI0 pin status -8- W39V040FA 6.12 Block Locking Registers This part provides 8 even 64Kbytes blocks, and each block can be locked by register control. These control registers can be set or clear through memory address. Below is the detail description. Block Locking Registers type and access memory map Table REGISTERS REGISTERS TYPE CONTROL BLOCK DEVICE PHYSICAL ADDRESS 4GBYTES SYSTEM MEMORY ADDRESS BLR7 R/W 7 7FFFFh – 70000h FFBF0002h BLR6 R/W 6 6FFFFh – 60000h FFBE0002h BLR5 R/W 5 5FFFFh – 50000h FFBD0002h BLR4 R/W 4 4FFFFh – 40000h FFBC0002h BLR3 R/W 3 3FFFFh – 30000h FFBB0002h BLR2 R/W 2 2FFFFh – 20000h FFBA0002h BLR1 R/W 1 1FFFFh – 10000h FFB90002h BLR0 R/W 0 0FFFFh – 00000h FFB80002h Block Locking Register Bits Function Table BIT FUNCTION 7–3 Reserved Read Lock 1: Prohibit to read in the block where set 0: Normal read operation in the block where clear. This is default state. Lock Down 1: Prohibit further to set or clear the Read Lock or Write Lock bits. This Lock Down Bit can only be set not clear. Only the device is reset or re-powered, the Lock Down Bit is cleared. 0: Normal operation for Read Lock or Write Lock. This is the default state. Write Lock 1: Prohibited to write in the block where set. This is default state. 0: Normal programming/erase operation in the block where clear. 2 1 0 Register Based Block Locking Value Definitions Table BIT [7:3] BIT 2 BIT 1 BIT 0 RESULT 00000 0 0 0 Full Access. 00000 0 0 1 Write Lock. Default State. 00000 0 1 0 Locked Open (Full Access, Lock Down). 00000 0 1 1 Write Locked, Locked Down. 00000 1 0 0 Read Locked. 00000 1 0 1 Read & Write Locked. 00000 1 1 0 Read Locked, Locked Down. 00000 1 1 1 Read & Write Locked, Locked Down. -9- Publication Release Date: April 14, 2005 Revision A6 W39V040FA 6.13 Read Lock Any attempt to read the data of read locked block will result in “00.” The default state of any block is unlocked upon power up. User can clear or set the write lock bit anytime as long as the lock down bit is not set. 6.14 Write Lock This is the default state of blocks upon power up. Before any program or erase to the specified block, user should clear the write lock bit first. User can clear or set the write lock bit anytime as long as the lock down bit is not set. The write lock function is in conjunction with the hardware protect pins, #WP & TBL. When hardware protect pins are enabled, it will override the register block locking functions and write lock the blocks no matter how the status of the register bits. Reading the register bit will not reflect the status of the #WP or #TBL pins. 6.15 Lock Down The default state of lock down bit for any block is unlocked. This bit can be set only once; any further attempt to set or clear is ignored. Only the reset from #RESET or #INIT can clear the lock down bit. Once the lock down bit is set for a block, then the write lock bit & read lock bit of that block will not be set or cleared, and keep its current state. 6.16 Product Identification Registers In the FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC,0001(hex) can output the device code 34(hex). There is an alternative software method (six commands bytes) to read out the Product Identification in both the Programmer interface mode and the FWH interface mode. Thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms. In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 34(hex).” The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table for detail). 6.17 Table of Operating Mode 6.17.1 Operating Mode Selection - Programmer Mode PINS MODE #OE #WE #RESET ADDRESS Read VIL VIH VIH AIN Dout Write VIH VIL VIH AIN Din X X VIL X High Z VIL X VIH X High Z/DOUT X VIH VIH X High Z/DOUT VIH X VIH X High Z Standby Write Inhibit Output Disable - 10 - DQ. W39V040FA 6.17.2 Operating Mode Selection - FWH Mode Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle Definition". 6.18 Table of Command Definition COMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE DESCRIPTION Cycles (1) Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Read 1 AIN DOUT Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA (5) 30 Page Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 PA (6) 50 Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN Top Boot Block Lockout – 64K/16KByte 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40/70 Product ID Entry 3 5555 AA 2AAA 55 5555 90 Product ID Exit (4) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit (4) 1 XXXX F0 DIN Notes: 1. The cycle means the write command cycle not the FWH clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11] 3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector Address SA = 7XXXXh for Unique Sector7 (Boot Sector) SA = 6XXXXh for Unique Sector6 SA = 5XXXXh for Unique Sector5 SA = 4XXXXh for Unique Sector4 SA = 3XXXXh for Unique Sector3 SA = 2XXXXh for Unique Sector2 SA = 1XXXXh for Unique Sector1 SA = 0XXXXh for Unique Sector0 6. PA: Page Address PA = 7FXXXh for Page 15 in Sector 7 PA = PA = PA = PA = PA = PA = PA = PA = 7EXXXh for Page 14 in Sector 7 6FXXXh 5FXXXh 4FXXXh 3FXXXh 2FXXXh 1FXXXh 0FXXXh to to to to to to to PA = 7DXXXh for Page 13 in Sector 7 00XXXh 10XXXh 20XXXh 30XXXh 40XXXh 50XXXh 60XXXh PA = 7CXXXh for Page 12 in Sector 7 for for for for for for for PA = 7BXXXh for Page 11 in Sector 7 Page 15 Page 15 Page 15 Page 15 Page 15 Page 15 Page 15 PA = 7AXXXh for Page 10 in Sector 7 to to to to to to to PA = 79XXXh for Page 9 in Sector 7 Page 0 Page 0 Page 0 Page 0 Page 0 Page 0 Page 0 PA = 78XXXh for Page 8 in Sector 7 In In In In In In In PA = 77XXXh for Page 7 in Sector 7 Sector 6 Sector 5 Sector 4 Sector 3 Sector 2 Sector 1 Sector 0 PA = 76XXXh for Page 6 in Sector 7 (Reference (Reference (Reference (Reference (Reference (Reference (Reference to the to the to the to the to the to the to the PA = 75XXXh for Page 5 in Sector 7 first first first first first first first PA = 74XXXh for Page 4 in Sector 7 column) column) column) column) column) column) column) PA = 73XXXh for Page 3 in Sector 7 PA = 72XXXh for Page 2 in Sector 7 PA = 71XXXh for Page 1 in Sector 7 PA = 70XXXh for Page 0 in Sector 7 - 11 - Publication Release Date: April 14, 2005 Revision A6 W39V040FA 6.19 FWH Cycle Definition FIELD NO. OF CLOCKS DESCRIPTION START 1 "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH Memory Write cycle. 0000b" appears on FWH bus to indicate the initial IDSEL 1 This one clock field indicates which FWH component is being selected. MSIZE 1 Memory Size. There is always show “0000b” for single byte access. TAR 2 Turned Around Time ADDR 7 Address Phase for Memory Cycle. FWH supports the 28 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and Address[3:0] on FWH[3:0] last.) SYNC N Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. DATA 2 Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then DQ[7:4] on FWH[3:0] last.) - 12 - W39V040FA 6.20 Embedded Programming Algorithm Start Write Program Command Sequence (see below) Pause T BP #Data Polling/ Toggle bit No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 13 - Publication Release Date: April 14, 2005 Revision A6 W39V040FA 6.21 Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Successfully Completed Pause T EC /TSEC/TPEC Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector Erase Command Sequence (Address/Command): Individual Page Erase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 2AAAH/55H 5555H/10H Sector Address/30H - 14 - Page Address/50H W39V040FA 6.22 Embedded #Data Polling Algorithm Start VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Any of the page addresses within the page being erased during page erase operation = Any of the device addresses being erased during chip erase operation Read Byte (DQ0 - DQ7) Address = VA No DQ7 = Data ? Yes Pass 6.23 Embedded Toggle Bit Algorithm Start Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 15 - Publication Release Date: April 14, 2005 Revision A6 W39V040FA 6.24 Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Product Identification Exit(6) Identification and Boot Block Lockout Detection Mode (3) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 00000 data = DA Load data 90 to address 5555 Read address = 00001 data = 34 Pause 10 μS Read address = 7FFF2 Check DQ[3:0] of data outputs (2) Load data 55 to address 2AAA Load data F0 to address 5555 (4) Pause 10 μS (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7 − DQ0 (Hex); Address Format: A14 − A0 (Hex) (2) A1 − A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) The DQ[3:0] to indicate the sectors protect status as below: DQ0 DQ1 0 64K Boot Block Unlocked by Software 16Kbytes Boot Block Unlocked by Software 1 64K Boot Block Locked by Software 16Kbytes Boot Block Locked by Software DQ2 64Kbytes Boot Block Unlocked by #TBL hardware trapping 64Kbytes Boot Block Locked by #TBL hardware trapping DQ3 Whole Chip Unlocked by #WP hardware trapping Except Boot Block Whole Chip Locked by #WP hardware trapping Except Boot Block (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockout detection. - 16 - W39V040FA 6.25 Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Pause T BP Load data 80 to address 5555 Exit Load data AA to address 5555 Load data 55 to address 2AAA Load data 40/70 to address 5555 40 to lock 64K Boot Block 70 to lcok 16K Boot Block - 17 - Publication Release Date: April 14, 2005 Revision A6 W39V040FA 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +4.6 V 0 to +70 °C -65 to +150 °C D.C. Voltage on Any Pin to Ground Potential -0.5 to VDD +0.5 V Transient Voltage (