W45B012P

Preliminary W45B012 1M × 1 SERIAL FLASH MEMORY GENERAL DESCRIPTION The W45B012 is manufactured with Winbond’s high performance CMOS WinFlash technology. The Serial Flash is organized as 32 sectors of 4096 Bytes for the W45B012. The memory is accessed for Read or Erase/Program by the SPI bus compatible serial protocol. The bus signals are: serial data input (SI), serial data output (SO), serial clock (SCK), write protect (#WP), chip enable (#CE), and hardware reset (#RESET). This device is offered in 8L SON and 32L PLCC package. FEATURES • • Single 2.7 − 3.6V Read and Write Operations Serial Interface Architecture − SPI Compatible: Mode 0 and Mode 3 • Automatic Write Timing − Internal VPP Generation End-of-Write Detection − Software Status 20 MHz Max Clock Frequency Hardware Reset Pin (#RESET) − Resets the device to Standby Mode TTL Compatibility Hardware Data Protection − Protects/Unprotects the device from Write operation • • • Byte Serial Read with Single Command Superior Reliability − Endurance: 10,000 Cycles (typ.) − 20 years Data Retention • • • Low Power Consumption − Active Current: 30 mA (max) − Standby Current: 15 µA (max) • • • Sector or Chip-Erase Capability − Uniform 4 KByte sectors Fast Erase and Byte-Program − Chip-Erase Time: 100 mS (Max.) − Sector-Erase Time: 25 mS (Max.) − Byte-Program Time: 50 µS (Max.) • Packages Available − 8 SON (5 x 6 mm), 32L PLCC • -1- Publication Release Date: April 18, 2002 Revision A1 Preliminary W45B012 PIN CONFIGURATIONS BLOCK DIAGRAM Address Buffers and Latches X-Decoder SuperFlash Cell Array 1 2 3 4 #CE SO #WP Vss 8L SON Top View VDD #RESE T SCK SI 8 7 6 5 Control Logic I/O Buffers and Data Latches Y-Decoder Serial Interface #CE # R E S E T SCK SI SO #WP #RESET N C 4 NC NC NC NC NC NC NC #CE NC 5 6 7 8 9 10 11 12 13 N C 3 N C 2 N C 1 V D D S C K PIN DESCRIPTION SYMBOL 29 28 27 SI NC NC NC NC #WP NC NC NC 32 31 30 PIN NAME Chip Enable Serial Data Input Serial Data Output Serial Clock Write Protect Reset Power Supply Ground #CE SI SO SCK #WP #RESET VDD VSS 32L PLCC 26 25 24 23 22 21 14 15 16 17 18 19 20 S O N C V S S N C N C N C N C PRODUCT IDENTIFICATION BYTE Manufacturer’s ID Device ID: W45B012 0000 h 0001 h DATA DA h 98 h -2- Preliminary W45B012 FUNCTIONAL DESCRIPTION Device Operation The W45B012 uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in the table below. All instructions are synchronized off a high to low transition of #CE. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low to high transition on #CE before the input instruction completes will terminate any instruction in progress and return the device to the standby mode. Read The Read operation outputs the data in order from the initial accessed address. While SCK is input, the address will be incremented automatically until end (top) of the address space, then the internal address pointer automatically increments to beginning (bottom) of the address space (00000h), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a low to high transition on #CE. Sector/Chip-erase Operation The Sector-Erase operation clears all bits in the selected sector to "FF". The Chip-Erase instruction clears all bits in the device to "FF". Byte-program Operation The Byte-Program operation programs the bits in the selected byte to the desired data. The selected byte must be in the erased state ("FF") when initiating a Program operation. The data is input from bit 7 to bit 0 in order. Software Status Operation The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a "0" an Erase or Program operation is in progress, the device is busy. If bit 0 is at a "1" the device is ready for any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on #CE. Reset Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a high to low transition on the #RESET pin. The device will remain in reset condition as long as #RESET is low. Minimum reset time is 10 µS. See Figure 14 for reset timing diagram. #RESET is internally pulled-up and could remain unconnected during normal operation. After reset, the device is in standby mode, a high to low transition on #CE is required to start the next operation. An internal power-on reset circuit protects against accidental data writes. Applying a logic level low to #RESET during the poweron process then changing to a logic level high when VDD has reached the correct voltage level will provide additional protection against accidental writes during power on. Read WINBOND ID/Read Device ID The Read Manufacturer ID and Read Device ID operations read the JEDEC assigned manufacturer identification and the manufacturer assigned device identification codes. These codes may be used to determine the actual device resident in the system. -3- Publication Release Date: April 18, 2002 Revision A1 Preliminary W45B012 Write Protect The #WP pin provides inadvertent write protection. The #WP pin must be held high for any Erase or Program operation. The #WP pin is "don't care" for all other operations. In typical use, the #WP pin is connected to VSS with a standard pull-down resistor. #WP is then driven high whenever an Erase or Program operation is required. If the #WP pin is tied to VDD with a pull-up resistor, then all operations may occur and the write protection feature is disabled. The #WP pin has an internal pull-up and could remain unconnected when not used. DEVICE OPERATION INSTRUCTION BUS CYCLE Operation/Type Read Sector-erase Chip-erase Byte-program Software-status Read Manufacture ID Read Device ID Notes: 1. A23 − A17 are "Don't Care" for device. 2. A16 − A12 are used to determine sector address, A11 − A8 are don't care. 3. With A16 − A1 = 0, W45B010 Device ID = 98h, is read with A0 = 1. 3 2 1 2 3 4 Address A7 − A0 X X A7 − A0 A0 = 0 A0 = 1 5 Data X Dout Dout Din 6 Dummy X X X X 7 Data Dout Command Address 1 Address FFh 20h 60h 10h 9Fh 90h 90h A23 − A16 A15 − A8 A23 − A16 A15 − A8 X X A23 − A16 A15 − A8 Dout X X X X DAh 98h DEVICE OPERATION TABLE OPERATION Read Sector-erase Chip-erase Byte-program Software-status Reset2 Read Manufacture ID Read Device ID SI X X X Din X X X X SO Dout X X X Dout X Dout Dout #CE1 Low Low Low Low Low X Low Low #WP X High High High X X X X #RESET High High High High High Low High High Notes: 1. A high to low transition on #CE will be required to start any device operation except for Reset. 2. The #RESET low will return the device to standby and terminate any Erase or Program operation in progress. -4- Preliminary W45B012 DC CHARACTERISTICS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) PARAMETER Temperature Under Bias Storage Temperature D. C. Voltage on Any Pin to Ground Potential Transient Voltage (