W49F002U

W49F002U 256K × 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F002U results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES • Single 5-volt operations: − 5-volt Read − 5-volt Erase − 5-volt Program Fast Program operation: − Byte-by-Byte programming: 35 µS (typ.) Fast Erase operation: 100 mS (typ.) Fast Read access time: 70/90/120 nS Endurance: 10K cycles (typ.) Ten-year data retention Hardware data protection One 16K byte Boot Block with Lockout protection Two 8K byte Parameter Blocks • • Two Main Memory Blocks (96K, 128K) Bytes Low power consumption − Active current: 25 mA (typ.) − Standby current: 20 µA (typ.) • • Automatic program and erase timing with internal VPP generation End of program or erase detection − Toggle bit − Data polling • • • • • • • • • • • • Latched address and data TTL compatible I/O JEDEC standard byte-wide pinouts Available packages: 32-pin DIP and 32-pin TSOP and 32-pin-PLCC -1- Publication Release Date: April 2000 Revision A2 W49F002U PIN CONFIGURATIONS BLOCK DIAGRAM RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 VDD WE A17 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS CE OE CONTROL WE RESET OUTPUT BUFFER DQ0 . . DQ7 32-pin DIP 26 25 24 23 22 21 20 19 18 17 A0 . . DECODER BOOT BLOCK 16K BYTES PARAMETER BLOCK1 8K BYTES PARAMETER BLOCK2 8K BYTES MAIN MEMORY BLOCK1 96K BYTES 3FFFF 3C000 3BFFF 3A000 39FFF 38000 37FFF 20000 1FFFF 00000 A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 AA 11 56 3 2 / R E S E T A17 V/ DW DE A 1 7 1 32 31 30 29 28 27 A14 A13 A8 A9 A11 OE A10 CE DQ7 MAIN MEMORY BLOCK2 128K BYTES 32-pin PLCC 26 25 24 23 22 21 14 15 16 17 18 19 20 DDG QQN 12D D Q 3 D Q 4 D Q 5 D Q 6 PIN DESCRIPTION SYMBOL PIN NAME Reset Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground 32 31 30 29 28 27 A11 A9 A8 A13 A14 A17 WE V DD RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 RESET A0−A17 DQ0−DQ7 CE OE WE VDD GND 32-pin TSOP 26 25 24 23 22 21 20 19 18 17 A16 A15 A12 A7 A6 A5 A4 -2- W49F002U FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F002U is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Reset Operation The reset input pin can be used in some application. When RESET pin is at high state, the device is in normal operation mode. When RESET pin is at low state, it will halts the device and all outputs are at high impedance state. As the high state re-asserted to the RESET pin, the device will return to read or standby mode, it depends on the control signals. When the system drives the RESET pin low for at least a period of 500 nS, the device immediately terminates any operation in progress duration of the RESET pulse. The other function for RESET pin is temporary reset the boot block. By applying the 12V to RESET pin, the boot block can be reprogrammed even though the boot block lockout function is enabled. Boot Block Operation There is one 16K-byte boot block in this device, which can be used to store boot code. It is located in the last 16K bytes with the address range of the boot block is 3C000(hex) to 3FFFF(hex).See Command Code sequence for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed with the regular programming method. Once the boot block programming lockout feature is activated, the chip erase function can no longer erase the boot block. There is one condition that the lockout feature can be overridden. Just apply 12V to RESET pin, the lockout feature will temporarily be inactivated and the block can be erased/programmed. Once the RESET pin return to TTL level, the lockout feature will be activated again. In order to detect whether the boot block feature is set on the 16K-bytes block, users can perform software command code sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 (hex)". If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data is "0 ," the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command code sequence (or an alternate singlebyte command) to exit the identification mode. For the specific code, see Command Code for Identification/Boot Block Lockout Detection. Chip Erase Operation The chip-erase mode can be initiated by a six-byte command code sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed as fast as 100 mS (typical). The host system is not required to provide any control or timing during this operation. The entire memory array will be erased to FF hex. by the chip erase Publication Release Date: April 2000 Revision A2 -3- W49F002U operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the whole chip erase function will erase the two main memory blocks and the two parameter blocks but not the boot block. The device will automatically return to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Sector Erase Operation There are four sectors: two main memory blocks and two parameters blocks which can be erased individually by initiating a six-byte command code sequence. Sector address is latched on the falling edge of W E signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of W E in this cycle. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed as fast as 100 mS (typical). The host system does not require to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect the end of erase cycle. When different sector address is loaded in the sixth cycle for sector erase command, the correspondent sectors will be erased automatically; that these sections will be erased independedntly. For detail sector to be erased information, please refer to the Table of Command Definition. Program Operation The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and two parameter blocks and/or boot block from "0" to "1") is needed before programming. The program operation is initiated by a 4-byte command code sequence (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (50 µS max. TBP). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49F002U is also hardware protected in the following ways: (1) Noise/Glitch Protection: A W E pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing OE low, CE high, or W E high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7)- Write Status Detection The W49F002U includes a data polling feature to indicate the end of a program or erase cycle. When the W49F002U is in the internal program or erase cycle, any attempt to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed. -4- W49F002U Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49F002U provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a three-byte (or JEDEC 3-byte) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code DA(hex). A read from address 0001H outputs the device code 0B(hex). The product ID operation can be terminated by a three-byte command code sequence or an alternate one-byte command code sequence (see Command Definition table). In the hardware access mode, access to the product ID is activated by forcing CE and OE low, W E high, and raising A9 to 12 volts. TABLE OF OPERATING MODES Operating Mode Selection (VHH = 12V ± 5%) MODE PINS RESET Read Write Standby Write Inhibit Output Disable Reset Mode Product ID VIH VIH VIH VIH VIH VIH VIL VIH VIH CE VIL VIL VIH X X X X VIL VIL OE VIL VIH X VIL X VIH X VIL VIL WE VIH VIL X X VIH X X VIH VIH AIN AIN X X X X X ADDRESS Dout Din High Z DQ. High Z/DOUT High Z/DOUT High Z High Z Manufacturer Code DA (Hex) Device Code 0B (Hex) A0 = VIL; A1−A17 = VIL; A9 = VHH A0 = VIH; A1−A17 = VIL; A9 = VHH -5- Publication Release Date: April 2000 Revision A2 W49F002U TABLE OF COMMAND DEFINITION(1) COMMAND DESCRIPTION Read Chip Erase Sector Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit Product ID Exit Notes: 1. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. SA means: Sector Address If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated, nothing will happen and the device will go back to read mode after 100nS. If the Boot Block programming lockout feature is not activated, this command will erase Boot Block. If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1. If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2. If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1. If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2. (2) (2) NO. OF 1 6 6 4 6 3 3 1 1ST CYCLE AIN DOUT 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 AA 2AAA 55 5555 A0 AIN 5555 AA 2AAA 55 5555 90 5555 AA 2AAA 55 5555 F0 XXXX F0 DIN 5555 40 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 SA (3) 30 -6- W49F002U Command Codes for Byte Program COMMAND SEQUENCE 0 Write 1 Write 2 Write 3 Write ADDRESS 5555H 2AAAH 5555H Programmed-address DATA AAH 55H A0H Programmed-data Byte Program Flow Chart Byte Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmedaddress Pause TBP Exit Notes for software program code: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -7- Publication Release Date: April 2000 Revision A2 W49F002U Command Codes for Chip Erase BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause TEC Exit Notes for chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) -8- W49F002U Command Codes for Sector Erase BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH SA* DATA AAH 55H 80H AAH 55H 30H Sector Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 30 to address SA* Pause TEC Exit Notes for chip erase: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) SA : For details, see the page 6 . -9- Publication Release Date: April 2000 Revision A2 W49F002U Command Codes for Product Identification and Boot Block Lockout Detection BYTE SEQUENCE SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 1 Write 2 Write 3 Write 5555 2AAA 5555 Pause 10 µS DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT(6) ADDRESS 5555H 2AAAH 5555H Pause 10 µS DATA AAH 55H F0H Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit(6) Load data 55 to address 2AAA (2) Read address = 0000 data = DA Load data 55 to address 2AAA Load data 90 to address 5555 Read address = 0001 (2) Load data F0 to address 5555 Pause 10 µS (4) Read address = 0002 data =in DQ0= "1" / "0" µ (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex) (2) A1−A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0 = " 0 ," the lockout feature is inactivated and the boot block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 10 - W49F002U Command Codes for Boot Block Lockout Enable BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause TBP DATA AAH 55H 80H AAH 55H 40H Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause T BP Exit Notes for boot block lockout enable: Data Format: DQ7−DQ0 (Hex) Address Format: A14−A0 (Hex) - 11 - Publication Release Date: April 2000 Revision A2 W49F002U DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential except OE Transient Voltage (