W49V002FA

W49V002FA 256K × 8 CMOS FLASH MEMORY WITH FWH INTERFACE GENERAL DESCRIPTION The W49V002FA is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K × 8 bits. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49V002FA results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification. The device can also be programmed and erased using standard EPROM programmers. FEATURES • Single 3.3-volt operations: − 3.3-volt Read − 3.3-volt Erase − 3.3-volt Program • • • Two 8K bytes Parameter Blocks Four main memory blocks (with 32K bytes, 64K bytes, 64K bytes, 64K bytes each) Low power consumption − Active current: 40 mA (typ. for FWH) Automatic program and erase timing with internal VPP generation End of program or erase detection − Toggle bit − Data polling • Fast program operation: − Byte-by-byte programming: 50 µS (typ.) Fast erase operation: 150 mS (typ.) Fast read access time: Tkq 11 nS Endurance: 10K cycles (typ.) Twenty-year data retention Hardware data protection − #TBL & #WP serve as hardware protection One 16K bytes Boot Block with lockout protection • • • • • • • • • • • Latched address and data TTL compatible I/O Available packages: 32L PLCC, 32L STSOP -1- Publication Release Date: February 19, 2002 Revision A2 W49V002FA PIN CONFIGURATIONS BLOCK DIAGRAM #WP #TBL CLK FWH[3:0] FWH4 IC #RESET BOOT BLOCK 16K BYTES Interface PARAMETER BLOCK1 8K BYTES PARAMETER BLOCK2 8K BYTES MAIN MEMORY BLOCK1 32K BYTES MAIN MEMORY BLOCK2 64K BYTES MAIN MEMORY BLOCK3 64K BYTES MAIN MEMORY BLOCK4 64K BYTES 3FFFF 3C000 3BFFF 3A000 39FFF 38000 37FFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 A 8 ^ F G P I 2 v 4 A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) A3(ID3) A2(ID2) A1(ID1) A0(ID0) DQ0(FWH0) 5 6 7 8 9 10 11 12 13 A 9 ^ F G P I 3 v 3 # R E S V END TCD 2 R # C ^ C L K v A 1 0 ^ F G P I 4 v #INIT R/#C A[10:0] DQ[7:0] #OE 29 28 27 IC GND NC GND VDD #OE(#INIT) #WE(FWH4) NC DQ7(RSV) Programmer Interface 1 32 31 30 #WE 32L PLCC 26 25 24 23 22 21 PIN DESCRIPTION SYM. IC #RESET #INIT #TBL #WP CLK FGPI[4:0] ID[3:0] INTERFACE PGM * * FWH * * * * * * * * PIN NAME Interface Mode Selection Reset Initialize Top Boot Block Lock Write Protect CLK Input General Purpose Inputs Identification Inputs They Are Internal Pull Down to VSS Address/Data Inputs FWH Cycle Initial Row/Column Select Address Inputs Data Inputs/Outputs Output Enable Write Enable Power Supply Ground Reserved Pins No Connection 14 15 16 17 18 19 20 D Q 1 ^ F W H 1 v DGDD QN QQ 2D34 ^ ^^ F FR W WS H HV 2 3v v v D Q 5 ^ R S V v D Q 6 ^ R S V v NC NC NC GND IC A10(FGPI4) R/#C(CLK) VDD NC #RESET A9(FGPI3) A8(FGPI2) A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32L TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 #OE(#INIT) #WE(FWH4) NC DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) DQ3(FWH3) GND DQ2(FWH2) DQ1(FWH1) DQ0(FWH0) A0(ID0) A1(ID1) A2(ID2) A3(ID3) FWH[3:0] FWH4 R/#C A[10:0] DQ[7:0] #OE #WE VDD GND RSV NC * * * * * * * * * * * * * * * -2- W49V002FA FUNCTIONAL DESCRIPTION Interface Mode Selection And Description This device can be operated in two interface modes, one is Programmer interface mode, the other is FWH interface mode. The IC pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go through address inputs A[10:0]. For FWH mode, It complies with the FWH Interface Specification. Through the FWH[3:0] to communicate with the system chipset . Read (Write) Mode In Programmer interface mode, the read (write) operation of the W49V002FA is controlled by #OE (#WE). The #OE(#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition for further details. Reset Operation The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals. Chip Erase Operation The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 150 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory blocks will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. Sector Erase Operation The seven sectors, one boot block and two parameter memory and four main blocks, can be erased individually by initiating a six-byte command sequence. Sector address is latched on the falling #WE edge of the sixth cycle, while the 30(hex) data input command is latched at the rising edge of #WE. After the command loading cycle, the device enters the internal sector erase mode, which is automatically timed and will be completed within fast 150 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle. -3- Publication Release Date: February 19, 2002 Revision A2 W49V002FA Program Operation The W49V002FA is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (100 µS max. TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. Boot Block Operation and Hardware Protection at Initial- #TBL & #WP There are two alternatives to set the boot block. One is software command sequences method; the other is hardware method. 16K-byte in the top location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes of the memory with the address range from 3C000(hex) to 3FFFF(hex). Please see Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set, the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. Besides the software method, there is a hardware method to protect the top boot block and other sectors. Before program/erase to this device, set the #TBL pin to low state and then the top boot block will not be programmed/erased. When enabling hardware top boot block, #TBL being low state, it will override the software method setting. That is, if #TBL is at low state, then top boot block cannot be programmed/erased no matter how the software boot block lock setting. Another pin, #WP, will protect the whole chip if this pin is set to low state before program/erase. The enable of this pin will override the #TBL setting. That is, the top boot block cannot be programmed/erased if this pin is set to low no matter how the #TBL or software boot block lock setting. Hardware Data Protection The integrity of the data stored in the W49V002FA is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 1.5V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation. Data Polling (DQ7)- Write Status Detection The W49V002FA includes a data polling feature to indicate the end of a program or erase cycle. When the W49V002FA is in the internal program or erase cycle, any attempts to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and when erase cycle has been completed it becomes logical "1" or true data. -4- W49V002FA Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49V002FA provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. General Purpose Inputs Register This register reads the FGPI[4:0] pins on the W49V002FA.This is a pass-through register which can read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value. BIT 7−5 4 3 2 1 0 FUNCTION Reserved Read FGPI4 pin status Read FGPI3 pin status Read FGPI2 pin status Read FGPI1 pin status Read FGPI0 pin status Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software operation. In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 32(hex).” The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table). As for FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC, 0001(hex) can output the device code 32(hex). TABLE OF OPERATING MODES Operating Mode Selection - Programmer Mode (VHH = 12V ± 5%) MODE PINS #OE Read Write Standby Write Inhibit Output Disable VIL VIH X VIL X VIH #WE VIH VIL X X VIH X #RESET VIH VIH VIL VIH VIH VIH ADDRESS AIN AIN X X X X Dout Din High Z DQ. High Z/DOUT High Z/DOUT High Z -5- Publication Release Date: February 19, 2002 Revision A2 W49V002FA Operating Mode Selection - FWH Mode Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle Definition". TABLE OF COMMAND DEFINITION COMMAND DESCRIPTION Read Chip Erase Sector Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit (1) NO. OF Cycles 1 6 6 4 6 3 3 1 1ST CYCLE Addr. Data AIN DOUT 2ND CYCLE Addr. Data 3RD CYCLE Addr. Data 4TH CYCLE Addr. Data 5TH CYCLE Addr. Data 6TH CYCLE Addr. Data 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA XXXX F0 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 5555 80 5555 80 5555 A0 5555 80 5555 90 5555 F0 5555 AA 5555 AA AIN DIN 2AAA 55 2AAA 55 5555 10 SA 30 5555 AA 2AAA 55 5555 40 Product ID Exit (1) Notes: 1. The cycle means the write command cycle not the FWH clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11] 3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector Address SA = 3C000h to 3FFFFh for Boot Block SA = 3A000h to 3BFFFh for Parameter Block1 SA = 38000h to 39FFFh for Parameter Block2 SA = 30000h to 37FFFh for Main Memory Block1 SA = 2XXXXh for Main Memory Block2 SA = 1XXXXh for Main Memory Block3 SA = 0XXXXh for Main Memory Block4 -6- W49V002FA FWH CYCLE DEFINITION FIELD START IDSEL MSIZE TAR ADDR NO. OF CLOCKS 1 1 1 2 7 DESCRIPTION "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH Memory Write cycle. This one clock field indicates which FWH component is being selected. Memory Size. There is always show “0000b” for single byte access. Turned Around Time Address Phase for Memory Cycle. FWH supports the 28 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[27:24] on FWH[3:0] first , and Address[3:0] on FWH[3:0] last.) Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first , then DQ[7:4] on FWH[3:0] last.) SYNC N DATA 2 -7- Publication Release Date: February 19, 2002 Revision A2 W49V002FA Embedded Programming Algorithm Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit Pause TBP No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data -8- W49V002FA Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle BitSuccessfully Completed Pause T EC /T SEC Erasure Completed Chip Erase Command Sequence (Address/Command): 5555H/AAH Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Sector Address/30H -9- Publication Release Date: February 19, 2002 Revision A2 W49V002FA Embedded #Data Polling Algorithm Start VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any sector group address during chip erase Read Byte (DQ0 - DQ7) Address = VA No DQ7 = Data ? Yes Pass Embedded Toggle Bit Algorithm Start Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 10 - W49V002FA Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit(6) Load data AA to address 5555 (2) Load data 55 to address 2AAA Read address = 00000 data = DA Load data 55 to address 2AAA Load data 90 to address 5555 Read address = 00001 data = 32 (Hex) (2) Load data F0 to address 5555 Pause 10 µS Read address = 00002 DQ0 of data outputs = 1/0 (4) Pause 10 µS (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7 − DQ0 (Hex); Address Format: A14 − A0 (Hex) (2) A1 − A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 11 - Publication Release Date: February 19, 2002 Revision A2 W49V002FA Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause TBP Exit - 12 - W49V002FA DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Transient Voltage (