W528S10

W528SXX ADPCM VOICE SYNTHESIZER (PowerSpeech) GENERAL DESCRIPTION The W528xxx family are programmable speech synthesis ICs that utilize the ADPCM coding method to generate all types of voice effects. The W528xxx's LOAD and JUMP commands and four programmable registers provide powerful userprogrammable functions that make this chip suitable for an extremely wide range of speech IC applications. The W528xxx family includes 12 kinds of bodies which are the same except for the voice duration shown below: BODY Second BODY Second W528S03 3 Sec W528S20 20 Sec W528S05 5 Sec W528S25 25 Sec W528S08A 8 Sec W528S30 30 Sec W528S10 10 Sec W528S40 40 Sec W528S12 12 Sec W528S50 50 Sec W528S15 15 Sec W528S60 60 Sec Note: The voice durations are estimated by 6.4KHz sampling rate. FEATURES • • • • • • • • • • Programmable speech synthesizer W ide operating voltage range: 2.4 to 5.5 volts 4-bit ADPCM synthesis method Provides 4 direct trigger inputs that can easily be extended to 8 or 12 matrix trigger inputs Two trigger input debounce times (20 to 40 mS or 160 to 320 µS) can be set Provides up to 2 LEDs and 3 STOP outputs Every LED pin can drive 3 LEDs simultaneously LED flash frequency: 3 Hz AUD output current: 5 mA Flexible functions programmable through the following: − LD (load), JP (jump) commands − Four registers: R0, EN, STOP, and MODE − Conditional instructions − Speech equation − END instruction − Global repeat (GR) setting − Output frequency and LED flash type setting • Programmable power-on initialization (POI) (can be interrupted by trigger inputs) -1- Publication Release Date: Nov 2000 Revision A1 W528SXX • • POI delay time of 160 mS ensures stable voltage when chip is powered on Can be programmed for the following functions: − Interrupt or non-interrupt for rising or falling edge of each trigger pin (this feature determines retriggerable, non-retriggerable, overwrite, and non-overwrite features of each trigger pin) − Four playing modes: One Shot (OS) Level Hold (LH) Single-cycle level hold (S_LH) Complete-cycle level hold (C_LH) − Stop output signal setting − Serial, direct, or random trigger mode setting Four frequency options (4/4.8/6/8 KHz) and LED On/Off control can be set independently in each GO instruction of speech equation • Independent control of LED1 and LED2 • Total of 256 voice group entries available for programming • Provides the following mask options: • − LED flash type: synchronous/alternate − LED1 section-controlled: Yes/No − LED2: section-controlled/STPC-controlled − LED volume-controlled: No/Yes PAD CONFIGURATIONS W5281-4 W528S03-S12 TEST TG1 TG2 TG3 TG4/LED2/STPC LED1 TEST4 OSC TG1 VDD VSS SPK TG2 TG3 W5285-9 W528S15-S60 OSC V DD TEST3 VSS TG4/LED2/STPC LED1 STPB STPA STPB STPA TEST1 TEST2 SPK -2- W528SXX PAD DESCRIPTION PAD NAME TG1 TG2 TG3 TG4/LED2/STPC LED1 STPB STPA SPK VSS VDD OSC *Test1 *Test2 *Test3 Test4 I/O I I I I/O O O O O I Trigger Input 1 Trigger Input 2 Trigger Input 3 Trigger Input 4 or LED 2 or Stop Signal C LED 1 Stop Signal B Stop Signal A Current Output for Speaker Negative Power Supply Positive Power Supply Oscillation Frequency Control Test Pin Test Pin Test Pin Test Pin FUNCTION * These pads only exist in W528S15~60. -3- Publication Release Date: Nov 2000 Revision A1 W528SXX BLOCK DIAGRAM OSC TIMING GENERATOR DATA ROM *TEST1 *TEST2 *TEST3 TEST4 TG1 TG2 TG3 TG4/LED2/STPC LED1 STPA STPB CONTROLLER COUNTER & SHIFT REGISTER SHIFT REGISTER ADPCM SYNTHESIZER D/A CONVERTER VDD VSS SPK * These pins only exist in W528S15~60. FUNCTIONAL DESCRIPTION The W528Sxx family provides up to four direct trigger pins, which can be extended to eight or twelve matrix trigger inputs, up to three stop signal output pins, an LED section control, and powerful programmable features. The JUMP and LOAD commands and four programmable registers can be used to program the desired playing mode, stop output signal form, LED flash type, and trigger pin interrupt modes. The chip's programmable features can also be used to develop new, customized functions for a wide variety of innovative applications. A. Instruction Set Description This section describes three types of instructions: • • • Unconditional instructions, which are executed immediately after they are issued. Conditional instructions, which are executed only when the conditions specified in the instructions are satisfied. END instruction, which is used to stop all device activity. Instructions are programmed by writing LOAD and JUMP commands into the R0, EN, STOP, and MODE registers. -4- W528SXX Unconditional Instructions: 1. LOAD (LD) Command: LD R0, value: This instruction is used to load a voice-group entry value into register R0. The voice-group entry value may range from 0 to 255. The initial value of the R0 register is "00000000." LD EN, operand: This instruction is used to define the trigger interrupt settings by loading the operand message into register EN. The initial value of the EN register is "11111111." a. The operand is an 8-bit value that can be entered in decimal (default) or hexadecimal (with "0x" as a prefix). b. EN is an 8-bit register that is used to enable/disable the rising/falling edge of each of the four trigger inputs. The 8 bits correspond to the rising/falling edges of the triggers as shown below: Bit: TG: 7 4R 6 3R 5 2R 4 1R 3 4F 2 3F 1 2F 0 1F where "nR/F" represents the rising/falling edge of the n-th trigger pin. c. When any one of the eight bits is set to "1" (default), the corresponding trigger will interrupt the current state at the edge indicated. When the bits are set to "0," the triggers will be disabled. d. The voice group entry addresses correspond to the interrupt vectors as follows: TG: Group: EXAMPLE: The instruction "LD EN, 0x41" is programmed. EXPLANATION: a. "41" is a hexadecimal value equal to the binary value "0100 0001." b. These 8 bits of data represent the following trigger interrupt settings: 4R,  0 RESULT: a. When the rising edge of TG3 (3R) is activated, the EN register will cause TG3 to interrupt the current playing state and jump immediately to voice group 6, the voice group that corresponds to 3R. b. When the falling edge of TG1 goes active, the EN register will cause TG1 to interrupt the current playing state and jump immediately to voice group 0, the voice group that corresponds to 1F. 3R,  1 2R,  0 1R,  0 4F,  0 3F,  0 2F,  0 1F  1 4R 7 3R 6 2R 5 1R 4 4F 3 3F 2 2F 1 1F 0 -5- Publication Release Date: Nov 2000 Revision A1 W528SXX c. No action will be taken when the other trigger pins are pressed, because the corresponding bits are set to "0." LD STOP, operand: This instruction loads the operand message into the STOP register to set the output levels of the stop signals. The initial value of the STOP register is "XXXXX111." a. This register is used to program the output levels of the three STOP signals, STPA, STPB, and STPC. Only three of the bits in the register are used, as shown below (an "X" indicates "Don't care"): Bit: Stop: 7 X 6 X 5 X 4 X 3 X 2 STPC 1 STPB 0 STPA b. When a particular STOP bit is set to "1," The corresponding stop signal will be a high output; when a bit is set to "0," the corresponding stop signal will be a low output. EXAMPLE: The instruction "LD STOP, 0x43" is programmed. EXPLANATION: a. "43" is a hexadecimal value equal to a binary value of "0100 0011." b. These 8 bits of data represent the following settings: X,  0 RESULT: a. The STPA and STPB outputs will be high outputs. b. The STPC signal will be a low output. c. The sixth bit "1" is a "Don't Care" bit and so has no effect on the stop signal output settings. LD MODE, operand: This instruction is used to select various operating modes. It loads an operand message into the MODE register to select one mode from each of four pairs of modes, which correspond to bits 4 through 7 of the register (bits 0 to 3 are "Don't Care" bits). The four pairs of modes and the corresponding bits are as follows: Bit: MODE: 7 Flash/DC 6 LED2/STPC 5 TG4/LED2_STPC 4 45 mS/350 µS 3 X 2 X 1 X 0 X X,  1 X,  0 X,  0 X,  0 STPC,  0 STPB,  1 STPA  1 A "1" for one of these bits selects the first of the pair of modes indicated; a "0" selects the second of the pair. The initial value of the mode register is "1111XXXX." -6- W528SXX EXAMPLE 1: The four bits are programmed as "1111," so that the eight bits of the register are as follows (an "X" indicates a "Don't Care" bit): Flash/DC,  1 RESULT: The mode settings are as follows: a. Pin 4 (TG4/LED2_STPC) is configured as a trigger pin (TG4), and the LED2/STPC option will be ignored. b. The LED is set as a flash type, with a flash frequency of 3 Hz. c. The debounce time of the trigger inputs is set to 45 mS. EXAMPLE 2: The four bits are programmed as "0000," so that the eight bits of the register are as follows (an "X" indicates a "Don't Care" bit): Flash/DC,  0 RESULT: The mode settings are as follows: a. Pin 4 (TG4/LED2_STPC) is configured as either the LED2 or STPC output (determined by bit 6, LED2/STPC; see next item). b. Pin 4 is configured as the STPC output pin. c. LED will be lit constantly during operation. d. The debounce time of the trigger inputs is set as 350 µS. 2. JUMP (JP) Command: JP value: Instructs device to jump directly to the voice group corresponding to the value indicated. The voice group value may range from 0 to 127 (direct jump). JP R0: Instructs device to jump to whatever voice group is indicated by the value currently stored in register R0, from 0 to 255 (indirect jump). LED2/STPC,  0 TG4/LED2_STPC,  0 45 mS/350 µS,  0 X,  X X,  X X,  X X  X LED2/STPC,  1 TG4/LED2_STPC,  1 45 mS/350 µS,  1 X,  X X,  X X,  X X  X -7- Publication Release Date: Nov 2000 Revision A1 W528SXX Conditional Instructions: Conditional instructions are executed only when the conditions specified in the instructions hold. The conditional instructions are listed below. An explanation of the notation used in the instructions follows. (Note: There are no conditional instructions for LD MODE.) LD R0, VALUE @LAST: VALUE can be set from 0 to 255. LD R0, VALUE @TGn_STATUS: VALUE can be set from 0 to 255. LD EN, OPERAND @LAST: EN - 4R, 3R, 2R, 1R, 4F, 3F, 2F, 1F. LD STOP, OPERAND @LAST: STOP - X, X, X, X, X, STPC, STPB, STPA. JP VALUE @LAST: VALUE can be set from 0 to 127. JP R0 @LAST JP VALUE @TGn_STATUS: VALUE can be set from 0 to 127 JP R0 @TGn_STATUS EXPLANATION: @LAST: At last time of global repeat. @TGn_STATUS: When the status of the trigger specified (TGn) is in the condition specified, where the possible triggers and conditions are the following: TG1_HIGH TG1_LOW TG2_HIGH TG2_LOW TG3_HIGH TG3_LOW TG4_HIGH TG4_LOW End Instruction: END: This command instructs the chip to cease all activity immediately. B. Program Structure Features and Execution Rules 1. There are eight hardware group entry points and 248 software group entry points, as follows: Group 8 H/W entries: TG1F: TG2F: TG3F: TG4F: TG1R: 0 1 2 3 4 -8- W528SXX (Continued) TG2R: TG3R: TG4R: 248 S/W entries: 5 6 7 8 9 . . . POI: 32 33 . . . 254 255 2. Execution begins from group entry and is terminated by END instruction. 3. A H/W trigger interrupt stops the group currently being executed immediately and begins a new group. C. Mask Options There are four mask options for the W528xxx family; the mask options are used to select features that cannot be programmed through the chip's registers. The options are the following: LED flash type (synchronous/alternate) LED volume-controlled: No/Yes LED1 section-controlled: Yes/No LED2: section-controlled/STPC-controlled D. Speech Equation Description The format of the speech equations for the W528xxx family is the same as that of the equations used in the Winbond W52160, W525XX, and W527XX series speech ICs. The following is an example of the speech equation format: GR = N H4+m1*SOUND1_FL+m2*SOUND2_FL+[1FFFF]+...+T4 END where Publication Release Date: Nov 2000 Revision A1 -9- W528SXX GR = N defines the number of global repeats (from 1 to 16); m1 and m2 define the number of local repeats (from 1 to 7); SOUND1 and SOUND2 are the *.WAM files of ADPCM converted voice data; _FL is the section control setting, for which the parameters F and L are as follows: F: Voice output frequency setting: 0 = 4 KHz, 1 = 4.8 KHz, 2 = 6 KHz, 3 = 8 KHz; L: LED output setting: 1: ON 0: OFF; and [1FFFF] is a period of silence of length 1FFFF; H4, T4: Represent head and tail ADPCM files, respectively. E. Programmable Power-on Initialization Whenever the W528xxx is powered on, the program contained in the 32nd voice group will be executed after the power-on delay (about 160 mS), so the user can write a program into this group to set the power-on initial state. If the user does not wish to execute a program at power-on, an "END" instruction should be entered in group 32. The W528xxx power-on initialization process can be interrupted by trigger inputs. F. Progamming Examples This section presents several examples of how the functions of the W528xxx may be programmed. Customer programs should be written in ASCII code using a text editor; after compiling, the sound effects resulting from the programs can be tested using a Winbond demo board. EXAMPLE1: Four playing mode settings: a. One-Shot Trigger Mode 0: LD EN, 0x01 H4 + sound1 + T4 END The timing diagram for this example is shown below: ; Enable TG1 falling edge input only. case 1: TG1: case 2: TG1: AUD: Sound 1 AUD: Sound 1 - 10 - W528SXX b. 0: Level-Hold Trigger Mode LD EN, 0x11 H4 + sound1 + T4 JP 0 4: END ; Repeat sound1 until TG1 key released. ; As soon as TG1 key is released, execute this group entry. ; Enable TG1 rising/falling edge input. The timing diagram is shown below: case 1: TG1: case 2: TG1: AUD: Stop Immediately AUD: Sound 1 Stop Immediately c. 0: Complete-Cycle Level Hold LD EN, 0x01 H4 + sound1 + T4 JP 0 @TG1_LOW ; If TG1 status is low level voltage (trigger is pressed), then j ump to 0; if not, execute next instruction (END). END ; Enable TG1 falling edge only. The timing diagram is shown below: case 1: TG1: case 2: TG1: AUD: Sound 1 AUD: Sound 1 Sound 1 d. 0: Single-Cycle Level Hold LD EN, 0x11 H4 + sound1 + T4 END • • • ; Enable both falling and rising edge input of TG1. 4: END ; As soon as TG1 is key released, execute this group entry. - 11 - Publication Release Date: Nov 2000 Revision A1 W528SXX The timing diagram is shown below: case 1: TG1: case 2: TG1: AUD: Stop Immediately AUD: Sound 1 EXAMPLE 2: Retriggerable and Non-retriggerable setting a. Retriggerable: 0: LD EN, 0x01 END • • • ; 0x01 = 00000001B, only TG1 falling edge interrupt is enabled. END The timing diagram is shown below: TG1: AUD: Restart Restart Sound 1 Sound 1 b. Non-retriggerable: 0: LD EN, 0x00 • • ; 0x00 = 00000000B, TG1 falling edge interrupt is disabled. LD EN, 0x11 END ; Recover the TG1 falling and rising edge interrupt is enabled. The timing diagram is shown below: TG1: AUD: Sound 1 Sound 1 - 12 - W528SXX ABSOLUTE MAXIMUM RATINGS PARAMETER Power Supply Input Voltage Storage Temp. Operating Temp. SYMBOL VDD−VSS VIN TSTG TOPR CONDITIONS All Inputs RATED VALUE -0.3 to +7.0 VSS -0.3 to VDD +0.3 -55 to +150 0 to +70 UNIT V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. ELECTRICAL CHARACTERISTICS (TA = 25° C, VSS = 0 V) PARAMETER Operating Voltage Input Voltage SYM. VDD VIL VIH IDD1 IDD2 IOP1 IOP2 IIN IO1 IOL IOH IO IOL IOH FOSC ∆FOSC FOSC CONDITIONS All Input Pins MIN. 2.4 VSS -0.3 0.7 VDD -4.0 1 -0.5 10 15 1 -1 2.7 2.7 0 45 350 LIMITS TYP. 3 -5.0 3 -3 3 3 4 MAX. 5.5 0.3 VDD VDD 0.2 0.4 400 800 6 -6.0 3.3 3.3 7.5 - UNIT V V µA µA µA mA mA Standby Current Operating Current Input Current for TG1−TG4 SPK (D/A Full Scale) Output Current of STPC LED1 LED2 STPA STPB VDD = 3V, No Playing VDD = 5V, No Playing VDD = 3V, No Load VDD = 5V, No Load VDD = 3V, VIN = 0V VDD = 4.5V, RL = 100 Ω VDD = 3V, VOUT = 0.4V VDD = 3V, VOUT = 2.7V VDD = 3V, VOUT = 1V VDD = 4.5V, VOUT = 1V VDD = 3V, VOUT = 0.4V VDD = 3V, VOUT = 2.7V VDD = 3V, ROSC = Typ. VDD = 4.5V, ROSC = Typ. F(3V) − F(2.4) F(3V) FOSC = 3 MHz, SR = 6 KHz Output Current Oscillation Freq. mA MHz % mS µS Oscillation Freq. Deviation by Voltage Drop Input Debounce Time TDEB1 TDEB2 Notes: 1. Rosc = 430KOhm for all bodies in W528xxx - 13 - Publication Release Date: Nov 2000 Revision A1 W528SXX TYPICAL APPLICATION CIRCUIT V DD TG1 TG2 TG3 OSC VDD Rosc TG4/LED2/STPC LED1 STPB STPA R 39/100 ohm Speaker 8 ohm 1/4 watt SPK V SS C s Rs 8050 D Notes: 1. In principle, the playing speed determined by ROSC should correspond to the sampling rate during the coding phase. The playing speed may be adjusted by varying ROSC, however. 2. Rs is an optional current-dividing resistor. If Rs is added, the resistance should be between 470 and 750Ω. 3. Cs is optional. 4. The DC current gain β of transistor 8050 ranges from 120 to 200. 5. All unused trigger pins can be left open because of their internal pull-high resistance. 6. R is used to limit the current on the LED. Case 1: VDD = 3V, R = 39Ω for 1/2/3 LEDs. Case 2: VDD = 4.5V, R = 39Ω for 2/3 LEDs and R = 100Ω for 1 LED. 7. No warranty for production. SUPPLEMENT A. Power Bouncing If an irregularity (such as bouncing) occurs in the power supply to VDD, as shown in the diagram, the W528xxx may hang or the logic state machine may lock up. To return the chip to normal operation, short VDD and VSS for the W528xxx and then release again. Power bouncing VDD Power on Power on reset W528x Battery - 14 - W528SXX B. Ttigger Pin Coupling Effect The trigger pins (TG1−TG4) are built-in 500KΩ pull high resistor. If the wire of the input trigger is very close to the speaker wire in the application environment, the coupling effect will occur. The input voltage of the trigger pin will be unstable, causing the trigger operation to become abnormal. An external pull high resistor (Ri) connecting the trigger pin and VDD can resolve this problem. The value of the Ri depends on your application environment. VDD Ri TGn SPK VDD Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 15 - Publication Release Date: Nov 2000 Revision A1