W632GG8KB
32M 8 BANKS 8 BIT DDR3 SDRAM
Table of Contents1.
GENERAL DESCRIPTION ................................................................................................................... 5
2.
FEATURES ........................................................................................................................................... 5
3.
ORDER INFORMATION ....................................................................................................................... 6
4.
KEY PARAMETERS ............................................................................................................................. 7
5.
BALL CONFIGURATION ...................................................................................................................... 8
6.
BALL DESCRIPTION ............................................................................................................................ 9
7.
BLOCK DIAGRAM .............................................................................................................................. 11
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
FUNCTIONAL DESCRIPTION ............................................................................................................ 12
Basic Functionality .............................................................................................................................. 12
RESET and Initialization Procedure .................................................................................................... 12
8.2.1
Power-up Initialization Sequence ..................................................................................... 12
8.2.2
Reset Initialization with Stable Power .............................................................................. 14
Programming the Mode Registers....................................................................................................... 15
8.3.1
Mode Register MR0 ......................................................................................................... 17
8.3.1.1
Burst Length, Type and Order ................................................................................ 17
8.3.1.2
CAS Latency........................................................................................................... 18
8.3.1.3
Test Mode............................................................................................................... 18
8.3.1.4
DLL Reset............................................................................................................... 18
8.3.1.5
Write Recovery ....................................................................................................... 19
8.3.1.6
Precharge PD DLL ................................................................................................. 19
8.3.2
Mode Register MR1 ......................................................................................................... 19
8.3.2.1
DLL Enable/Disable ................................................................................................ 20
8.3.2.2
Output Driver Impedance Control ........................................................................... 20
8.3.2.3
ODT RTT Values .................................................................................................... 20
8.3.2.4
Additive Latency (AL) ............................................................................................. 20
8.3.2.5
Write leveling .......................................................................................................... 20
8.3.2.6
Output Disable ........................................................................................................ 21
8.3.2.7
TDQS, TDQS#........................................................................................................ 21
8.3.3
Mode Register MR2 ......................................................................................................... 22
8.3.3.1
Partial Array Self Refresh (PASR) .......................................................................... 23
8.3.3.2
CAS Write Latency (CWL) ...................................................................................... 23
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) ............................. 23
8.3.3.4
Dynamic ODT (Rtt_WR) ......................................................................................... 23
8.3.4
Mode Register MR3 ......................................................................................................... 24
8.3.4.1
Multi Purpose Register (MPR) ................................................................................ 24
No OPeration (NOP) Command .......................................................................................................... 25
Deselect Command ............................................................................................................................. 25
DLL-off Mode ...................................................................................................................................... 25
DLL on/off switching procedure ........................................................................................................... 26
8.7.1
DLL “on” to DLL “off” Procedure .......................................................................... 26
8.7.2
8.8
DLL “off” to DLL “on” Procedure .......................................................................... 27
Input clock frequency change.............................................................................................................. 28
8.8.1
Frequency change during Self-Refresh............................................................................ 28
8.8.2
Frequency change during Precharge Power-down .......................................................... 28
Publication Release Date: Dec. 08, 2014
Revision: A04
-1-
W632GG8KB
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
Write Leveling ..................................................................................................................................... 30
8.9.1
DRAM setting for write leveling & DRAM termination function in that mode .................... 31
8.9.2
Write Leveling Procedure ................................................................................................. 31
8.9.3
Write Leveling Mode Exit ................................................................................................. 33
Multi Purpose Register ........................................................................................................................ 34
8.10.1
MPR Functional Description ............................................................................................. 35
8.10.2
MPR Register Address Definition ..................................................................................... 36
8.10.3
Relevant Timing Parameters ............................................................................................ 36
8.10.4
Protocol Example ............................................................................................................. 36
ACTIVE Command.............................................................................................................................. 42
PRECHARGE Command .................................................................................................................... 42
READ Operation ................................................................................................................................. 43
8.13.1
READ Burst Operation ..................................................................................................... 43
8.13.2
READ Timing Definitions .................................................................................................. 44
8.13.2.1
READ Timing; Clock to Data Strobe relationship.................................................... 45
8.13.2.2
READ Timing; Data Strobe to Data relationship ..................................................... 46
8.13.2.3
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ............................................. 47
8.13.2.4
tRPRE Calculation .................................................................................................. 48
8.13.2.5
tRPST Calculation .................................................................................................. 48
8.13.2.6
Burst Read Operation followed by a Precharge...................................................... 54
WRITE Operation ................................................................................................................................ 56
8.14.1
DDR3 Burst Operation ..................................................................................................... 56
8.14.2
WRITE Timing Violations ................................................................................................. 56
8.14.2.1
Motivation ............................................................................................................... 56
8.14.2.2
Data Setup and Hold Violations .............................................................................. 56
8.14.2.3
Strobe to Strobe and Strobe to Clock Violations..................................................... 56
8.14.2.4
Write Timing Parameters ........................................................................................ 56
8.14.3
Write Data Mask............................................................................................................... 57
8.14.4
tWPRE Calculation........................................................................................................... 58
8.14.5
tWPST Calculation ........................................................................................................... 58
Refresh Command .............................................................................................................................. 65
Self-Refresh Operation ....................................................................................................................... 67
Power-Down Modes ............................................................................................................................ 69
8.17.1
Power-Down Entry and Exit ............................................................................................. 69
8.17.2
Power-Down clarifications - Case 1 ................................................................................. 75
8.17.3
Power-Down clarifications - Case 2 ................................................................................. 75
8.17.4
Power-Down clarifications - Case 3 ................................................................................. 76
ZQ Calibration Commands .................................................................................................................. 77
8.18.1
ZQ Calibration Description ............................................................................................... 77
8.18.2
ZQ Calibration Timing ...................................................................................................... 78
8.18.3
ZQ External Resistor Value, Tolerance, and Capacitive loading ...................................... 78
On-Die Termination (ODT) .................................................................................................................. 79
8.19.1
ODT Mode Register and ODT Truth Table ...................................................................... 79
8.19.2
Synchronous ODT Mode .................................................................................................. 80
8.19.2.1
ODT Latency and Posted ODT ............................................................................... 80
8.19.2.2
Timing Parameters ................................................................................................. 80
8.19.2.3
ODT during Reads .................................................................................................. 82
8.19.3
Dynamic ODT .................................................................................................................. 83
8.19.3.1
Functional Description: ........................................................................................... 83
Publication Release Date: Jul. 28, 2014
Revision: A04
-2-
W632GG8KB
8.19.3.2
ODT Timing Diagrams ............................................................................................ 84
8.19.4
Asynchronous ODT Mode ................................................................................................ 88
8.19.4.1
Synchronous to Asynchronous ODT Mode Transitions .......................................... 89
8.19.4.2
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry .. 89
8.19.4.3
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit..... 92
8.19.4.4
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
low periods
93
9.
9.1
9.2
9.3
10.
OPERATION MODE ........................................................................................................................... 94
Command Truth Table ........................................................................................................................ 94
CKE Truth Table ................................................................................................................................. 96
Simplified State Diagram ..................................................................................................................... 97
ELECTRICAL CHARACTERISTICS ................................................................................................... 98
Absolute Maximum Ratings ................................................................................................................ 98
Operating Temperature Condition ....................................................................................................... 98
DC & AC Operating Conditions ........................................................................................................... 98
10.3.1
Recommended DC Operating Conditions ........................................................................ 98
10.4
Input and Output Leakage Currents .................................................................................................... 99
10.5
Interface Test Conditions .................................................................................................................... 99
10.6
DC and AC Input Measurement Levels ............................................................................................. 100
10.6.1
DC and AC Input Levels for Single-Ended Command and Address Signals .................. 100
10.6.2
DC and AC Input Levels for Single-Ended Data Signals ................................................ 101
10.6.3
Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ........... 103
10.6.4
Single-ended requirements for differential signals ......................................................... 104
10.6.5
Differential Input Cross Point Voltage ............................................................................ 105
10.6.6
Slew Rate Definitions for Single-Ended Input Signals .................................................... 106
10.6.7
Slew Rate Definitions for Differential Input Signals ........................................................ 106
10.7
DC and AC Output Measurement Levels .......................................................................................... 107
10.7.1
Output Slew Rate Definition and Requirements ............................................................. 107
10.7.1.1
Single Ended Output Slew Rate ........................................................................... 108
10.7.1.2
Differential Output Slew Rate ............................................................................... 109
10.8
34 ohm Output Driver DC Electrical Characteristics .......................................................................... 110
10.8.1
Output Driver Temperature and Voltage sensitivity ........................................................ 112
10.9
On-Die Termination (ODT) Levels and Characteristics ..................................................................... 113
10.9.1
ODT Levels and I-V Characteristics ............................................................................... 113
10.9.2
ODT DC Electrical Characteristics ................................................................................. 114
10.9.3
ODT Temperature and Voltage sensitivity ..................................................................... 114
10.9.4
Design guide lines for RTTPU and RTTPD ....................................................................... 115
10.10
ODT Timing Definitions............................................................................................................ 116
10.10.1
Test Load for ODT Timings ............................................................................................ 116
10.10.2
ODT Timing Definitions .................................................................................................. 116
10.11
Input/Output Capacitance ........................................................................................................ 120
10.12
Overshoot and Undershoot Specifications............................................................................... 121
10.12.1
AC Overshoot /Undershoot Specification for Address and Control Pins: ....................... 121
10.12.2
AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins: ......... 121
10.13
IDD and IDDQ Specification Parameters and Test Conditions ................................................ 122
10.13.1
IDD and IDDQ Measurement Conditions ....................................................................... 122
10.13.2
IDD Current Specifications ............................................................................................. 132
10.14
Clock Specification .................................................................................................................. 133
10.15
Speed Bins .............................................................................................................................. 134
10.15.1
DDR3-1333 Speed Bin and Operating Conditions ......................................................... 134
10.1
10.2
10.3
Publication Release Date: Jul. 28, 2014
Revision: A04
-3-
W632GG8KB
10.15.2
10.15.3
10.15.4
DDR3-1600 Speed Bin and Operating Conditions ......................................................... 135
DDR3-1866 Speed Bin and Operating Conditions ......................................................... 136
Speed Bin General Notes .............................................................................................. 137
10.16
AC Characteristics ................................................................................................................... 138
10.16.1
AC Timing and Operating Condition for -11 speed grade .............................................. 138
10.16.2
AC Timing and Operating Condition for -12/12I/-15/15I speed grades........................... 142
10.16.3
Timing Parameter Notes ................................................................................................ 146
10.16.4
Address / Command Setup, Hold and Derating ............................................................. 149
10.16.5
Data Setup, Hold and Slew Rate Derating ..................................................................... 156
11.
PACKAGE SPECIFICATION ............................................................................................................ 158
12.
REVISION HISTORY ........................................................................................................................ 159
Publication Release Date: Jul. 28, 2014
Revision: A04
-4-
W632GG8KB
1. GENERAL DESCRIPTION
The W632GG8KB is a 2G bits DDR3 SDRAM, organized as 33,554,432 words 8 banks 8 bits. This
device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. The W632GG8KB is sorted into the following speed grades: -11, -12, 12I, -15 and 15I.
The -11 grade is compliant to the DDR3-1866 (13-13-13) specification. The -12 and 12I grades are
compliant to the DDR3-1600 (11-11-11) specification (the 12I industrial grade which is guaranteed to
support -40°C ≤ TCASE ≤ 95°C). The -15 and 15I grades are compliant to the DDR3-1333 (9-9-9)
specification (the 15I industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C).
The W632GG8KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Data masks (DM) for write data
Programmable CAS Write Latency (CWL) per operating frequency
Write Latency WL = AL + CWL
Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence
System level timing calibration support via write leveling and MPR read pattern
Publication Release Date: Jul. 28, 2014
Revision: A04
-5-
W632GG8KB
ZQ Calibration for output driver and ODT using external reference resistor to ground
Asynchronous RESET# pin for Power-up initialization sequence and reset function
Programmable on-die termination (ODT) for data, data mask and differential strobe pairs
Dynamic ODT mode for improved signal integrity and preselectable termination impedances during
writes
1K Byte page size
Interface: SSTL_15
Packaged in WBGA 78 Ball (8x10.5 mm2), using lead free materials with RoHS compliant
3. ORDER INFORMATION
PART NUMBER
SPEED GRADE
OPERATING TEMPERATURE
W632GG8KB-11
DDR3-1866 (13-13-13)
0°C ≤ TCASE ≤ 95°C
W632GG8KB-12
DDR3-1600 (11-11-11)
0°C ≤ TCASE ≤ 95°C
W632GG8KB12I
DDR3-1600 (11-11-11)
-40°C ≤ TCASE ≤ 95°C
W632GG8KB-15
DDR3-1333 (9-9-9)
0°C ≤ TCASE ≤ 95°C
W632GG8KB15I
DDR3-1333 (9-9-9)
-40°C ≤ TCASE ≤ 95°C
Publication Release Date: Jul. 28, 2014
Revision: A04
-6-
W632GG8KB
4. KEY PARAMETERS
Speed Bin
DDR3-1866
DDR3-1600
DDR3-1333
CL-nRCD-nRP
13-13-13
11-11-11
9-9-9
Part Number Extension
-11
-12/12I
-15/15I
Unit
Parameter
Sym.
Min.
Max.
Min.
Max.
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
fCKMAX
933
800
667
MHz
tAA
13.91
20
13.75
(13.125) *5
20
13.5
(13.125) *5
20
nS
tRCD
13.91
13.75
(13.125) *5
13.5
(13.125) *5
nS
PRE command period
tRP
13.91
13.75
(13.125) *5
13.5
(13.125) *5
nS
ACT to ACT or REF command period
tRC
47.91
48.75
(48.125) *5
49.5
(49.125) *5
nS
ACT to PRE command period
tRAS
34
9 * tREFI
35
9 * tREFI
36
9 * tREFI
nS
2.5
3.3
Internal read command to first data
ACT to internal read or write delay time
CL = 6
CWL = 5
tCK(AVG)
CL = 7
CWL = 6
tCK(AVG)
CL = 8
CWL = 6
tCK(AVG)
CL = 9
CWL = 7
tCK(AVG)
CL = 10
CWL = 7
tCK(AVG)
CL = 11
CWL = 8
tCK(AVG)
CL = 13
CWL = 9
tCK(AVG)
Supported CL Settings
Supported CWL Settings
Reserved
1.875
< 2.5
Reserved
1.5
< 1.875
Reserved
1.07
2.5
3.3
2.5
3.3
nS
1.875
< 2.5
1.875
< 2.5
nS
1.875
< 2.5
1.875
< 2.5
nS
1.5
< 1.875
1.5
< 1.875
nS
1.5
< 1.875
1.5
< 1.875
nS
1.25
< 1.5
< 1.25
Reserved
nS
Reserved
Reserved
nS
nCK
Sup_CL
6, 8, 10, 13
6, (7), 8, (9), 10, 11
6, (7), 8, 9, 10
Sup_CWL
5, 6, 7, 9
5, 6, 7, 8
5, 6, 7
2
7.8 *1
85°C < TCASE ≤ 95°C
3.9 *4
Operating One Bank Active-Precharge Current
IDD0
Operating One Bank Active-Read-Precharge
Current
IDD1
-40°C ≤ TCASE ≤ 85°C
Average periodic
refresh Interval
0°C ≤ TCASE ≤ 85°C
tREFI
*
2, 3
7.8 *1
nCK
2, 3
μS
7.8 *1
μS
3.9 *4
3.9 *4
μS
105
95
90
mA
120
115
110
mA
7.8 *
7.8 *
IDD4R
250
220
205
mA
Operating Burst Write Current
IDD4W
230
200
180
mA
Burst Refresh Current
IDD5B
145
140
135
mA
Self-Refresh Current, TOPER = 0 ~ 85°C
IDD6
19
19
19
mA
IDD7
360
340
330
mA
Operating Burst Read Current
Operating Bank Interleave Current
Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)
1. All speed grades support 0°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.
2. For -11, -12 and -15 speed grades, -40°C ≤ TCASE < 0°C is not available.
3. 12I and 15I speed grades support -40°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.
4. For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is don't care).
5. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 nS or lower. SPD settings
must be programmed to match. For example, DDR3-1333 (9-9-9) devices supporting down binning to DDR3-1066 (7-7-7)
should program 13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 (11-11-11)
devices supporting down binning to DDR3-1333 (9-9-9) or DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes for
tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21,
23) also should be programmed accodingly. For example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3-1333
(9-9-9) and 48.125 nS (tRASmin + tRPmin = 35 nS + 13.125 nS) for DDR3-1600 (11-11-11).
Publication Release Date: Jul. 28, 2014
Revision: A04
-7-
W632GG8KB
5. BALL CONFIGURATION
1
2
3
VSS
VDD
NC
VSS
VSSQ
VDDQ
4
5
6
7
8
9
A
NU/TDQS#
VSS
VDD
DQ0
B
DM/TDQS
VSSQ
VDDQ
DQ2
DQS
C
DQ1
DQ3
VSSQ
VSSQ
DQ6
DQS#
D
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
E
DQ7
DQ5
VDDQ
NC
VSS
RAS#
F
CK
VSS
NC
ODT
VDD
CAS#
G
CK#
VDD
CKE
NC
CS#
WE#
H
A10/AP
ZQ
NC
VSS
BA0
BA2
J
NC
VREFCA
VSS
VDD
A3
A0
K
A12/BC#
BA1
VDD
VSS
A5
A2
L
A1
A4
VSS
VDD
A7
A9
M
A11
A6
VDD
VSS
RESET#
A13
N
A14
A8
VSS
Publication Release Date: Jul. 28, 2014
Revision: A04
-8-
W632GG8KB
6. BALL DESCRIPTION
BALL NUMBER
SYMBOL
TYPE
DESCRIPTION
F7, G7
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#.
G9
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates,
internal clock signals and device input buffers and output drivers.
Taking CKE Low provides Precharge Power Down and Self-Refresh
operation (all banks idle), or Active Power Down (row Active in any
bank). CKE is asynchronous for Self-Refresh exit. After VREFCA and
VREFDQ have become stable during the power on and initialization
sequence, they must be maintained during all operations (including
Self-Refresh). CKE must be maintained high throughout read and
write accesses. Input buffers, excluding CK, CK#, ODT and CKE, are
disabled during power down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
H2
CS#
Input
Chip Select: All commands are masked when CS# is registered HIGH.
CS# provides for external Rank selection on systems with multiple
Ranks. CS# is considered part of the command code.
G1
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR3 SDRAM. When enabled, ODT is
applied to each DQ, DQS, DQS# and DM/TDQS, NU/TDQS# (When
TDQS is enabled via Mode Register A11=1 in MR1) signal. The ODT
signal will be ignored if Mode Registers MR1 and MR2 are
programmed to disable ODT and during Self Refresh.
F3, G3, H3
RAS#, CAS#,
WE#
Input
Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
command being entered.
B7
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH coincident with that input data
during a Write access. DM is sampled on both edges of DQS. The
function of DM or TDQS/TDQS# is enabled by Mode Register A11
setting in MR1.
J2, K8, J3
BA0−BA2
Input
Bank Address Inputs: BA0−BA2 define to which bank an Active, Read,
Write, or Precharge command is being applied. Bank address also
determines which mode register is to be accessed during a MRS
cycle.
Input
Address Inputs: Provide the row address for Active commands and the
column address for Read/Write commands to select one location out
of the memory array in the respective bank. (A10/AP and A12/BC#
have additional functions; see below). The address inputs also provide
the op-code during Mode Register Set command.
Row address: A0−A14.
Column address: A0−A9.
Input
Auto-precharge: A10 is sampled during Read/Write commands to
determine whether Auto-precharge should be performed to the
accessed bank after the Read/Write operation.
(HIGH: Auto-precharge; LOW: no Auto-precharge). A10 is sampled
during a Precharge command to determine whether the Precharge
applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by bank addresses.
Input
Burst Chop: A12/BC# is sampled during Read and Write commands to
determine if burst chop (on-the-fly) will be performed.
(HIGH, no burst chop; LOW: burst chopped). See section 9.1
“Command Truth Table” on page 94 for details.
Input
Active Low Asynchronous Reset: Reset is active when RESET# is
LOW, and inactive when RESET# is HIGH. RESET# must be HIGH
during normal operation. RESET# is a CMOS rai to rail signal with DC
high and low at 80% and 20% of VDD, RESET# active is destructive to
data contents.
K3, L7, L3, K2, L8,
L2, M8, M2, N8, M3,
H7, M7, K7, N3, N7
H7
K7
N2
A0−A14
A10/AP
A12/BC#
RESET#
Publication Release Date: Jul. 28, 2014
Revision: A04
-9-
W632GG8KB
B3, C7,C2, C8, E3,
E8, D2, E7
C3, D3
DQ0−DQ7
DQS, DQS#
Input/Output
Data Input/Output: Bi-directional data bus.
Input/Output
Data Strobe: Output with read data, input with write data. Edgealigned with read data, centered in write data. DQS is paired with
DQS# to provide differential pair signaling to the system during read
and write data transfer. DDR3 SDRAM supports differential data
strobe only and does not support single-ended.
B7, A7
TDQS, TDQS#
Output
Termination Data Strobe: When TDQS enabled via Mode Register
A11 = 1 in MR1, the DRAM will enable the same termination
resistance function on TDQS/TDQS# that is applied to DQS/DQS#.
When TDQS disabled via mode register A11 = 0 in MR1, DM/TDQS
will provide the data mask function and TDQS# is not used.
A2, A9, D7, G2, G8,
K1, K9, M1, M9
VDD
Supply
Power Supply: 1.5V ± 0.075V.
A1, A8, B1, D8, F2,
F8, J1, J9, L1, L9,
N1, N9
VSS
Supply
Ground.
B9, C1, E2, E9
VDDQ
Supply
DQ Power Supply: 1.5V ± 0.075V.
B2, B8, C9, D1, D9
VSSQ
Supply
DQ Ground.
E1
VREFDQ
Supply
Reference voltage for DQ.
J8
VREFCA
Supply
Reference voltage for Control, Command and Address inputs.
Supply
External reference ball for output drive and On-Die Termination
Impedance calibration: This ball needs an external 240Ω ± 1%
external resistor (RZQ), connected from this ball to ground to perform
ZQ calibration.
H8
ZQ
A3, F1, F9, H1, H9,
J7
NC
No Connect: No internal electrical connection is present.
Note:
Input only balls (BA0-BA2, A0-A14, RAS#, CAS#, WE#, CS#, CKE, ODT and RESET#) do not supply termination.
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7. BLOCK DIAGRAM
CK, CK#
CLOCK
BUFFER
CKE
CONTROL
CS#
SIGNAL
RAS#
COMMAND
GENERATOR
DECODER
A0
MODE
REGISTER
SENSE
AMPLIFIER
ADDRESS
BUFFER
A9
A11
A12
A13
A14
BA2
BA1
BA0
CELL ARRAY
BANK #0
ROW DECODER
ROW DECODER
A10
COLUMN
DECODER
COLUMN
DECODER
CELL ARRAY
BANK #1
CELL ARRAY
BANK #4
COLUMN
DECODER
ROW DECODER
COLUMN
DECODER
WE#
ROW DECODER
CAS#
CELL ARRAY
BANK #5
SENSE
AMPLIFIER
CK, CK#
ODT
DLL
PREFETCH REGISTER
WRITE
drivers
DM MASK LOGIC
REFRESH
COLUMN
COUNTER
COUNTER
READ
drivers
DQ
BUFFER
DATA CONTROL CIRCUIT
DQ0−DQ7
DQ0−DQ7
DQS, DQS#
ODT
DQS, DQS#
TDQS, TDQS#
CONTROL
TDQS, TDQS#
DM
DM
ZQCL, ZQCS
ZQ CAL
ZQ
COLUMN
DECODER
COLUMN
DECODER
COLUMN
DECODER
COLUMN
DECODER
SENSE
AMPLIFIER
CELL ARRAY
BANK #3
SENSE
AMPLIFIER
CELL ARRAY
BANK #6
SENSE
AMPLIFIER
ROW DECODER
ROW DECODER
CELL ARRAY
BANK #2
ROW DECODER
To ODT/output drivers
VSSQ
ROW DECODER
RZQ
CELL ARRAY
BANK #7
SENSE
AMPLIFIER
NOTE: The cell array configuration is 32768 * 1024 * 8
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8. FUNCTIONAL DESCRIPTION
8.1
Basic Functionality
The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an
eight-bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed
operation. The 8n prefetch architecture is combined with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists
of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding nbit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and
continue for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation
begins with the registration of an Active command, which is then followed by a Read or Write
command. The address bits registered coincident with the Active command are used to select the
bank and row to be activated (BA0-BA2 select the bank; A0-A14 select the row). The address bits
registered coincident with the Read or Write command are used to select the starting column location
for the burst operation, determine if the auto precharge command is to be issued (via A10), and select
BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined
manner. The following sections provide detailed information covering device reset and initialization,
register definition, command descriptions, and device operation.
8.2
RESET and Initialization Procedure
8.2.1 Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power (RESET# is recommended to be maintained below 0.2 * VDD; all other inputs may be
undefined). RESET# needs to be maintained for minimum 200 µS with stable power. CKE is pulled
“Low” anytime before RESET# being de-asserted (min. time 10 nS). The power voltage ramp time
between 300 mV to VDD min. must be no greater than 200 mS; and during the ramp, VDD ≥ VDDQ
and (VDD - VDDQ) < 0.3 Volts.
VDD and VDDQ are driven from a single power converter output, AND
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
In addition, VTT is limited to 0.95 V max once power ramp is finished, AND
VREF tracks VDDQ/2.
OR
Apply VDD without any slope reversal before or at the same time as VDDQ.
Apply VDDQ without any slope reversal before or at the same time as VTT & VREF.
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to
VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500 µS until CKE becomes active. During this time,
the DRAM will start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 nS or 5 tCK (which is larger)
before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to
clock (tIS) must be met. Also, a NOP or Deselect command must be registered (with tIS set up time
to clock) before CKE goes active. Once the CKE is registered “High” after Reset, CKE needs to be
continuously registered “High” until the initialization sequence is finished, including expiration of
tDLLK and tZQinit.
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4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is
asserted. Further, the SDRAM keeps its on-die termination in high impedance state after RESET#
deassertion until CKE is registered HIGH. The ODT input signal may be in undefined state until tIS
before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be
statically held at either LOW or HIGH. If Rtt_Nom is to be enabled in MR1, the ODT input signal
must be statically held LOW. In all cases, the ODT input signal remains static until the power up
initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the
first MRS command to load mode register. (tXPR=max (tXS ; 5 * tCK)
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2,
provide “Low” to BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3,
provide “Low” to BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL
Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to BA1-BA2).
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL
reset command, provide “High” to A8 and “Low” to BA0-2).
10.Issue ZQCL command to starting ZQ calibration.
11.Wait for both tDLLK and tZQinit completed.
12.The DDR3 SDRAM is now ready for normal operation.
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK, CK#
tCKSRX
VDD, VDDQ
T = 200 µs
T = 500 µs
RESET#
Tmin
10 ns
tIS
CKE
VALID
tDLLK
tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
tIS
Command
*1
BA
MRS
MRS
MRS
MRS
MR2
MR3
MR1
MR0
ZQCL
*1
VALID
tIS
ODT
VALID
tIS
Static LOW in case Rtt_Nom is enabled at time Tg, Otherwise static HIGH or LOW
VALID
RTT
TIME BREAK
DON'T CARE
Note:
1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 1 – Reset and Initialization Sequence at Power-on Ramping
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8.2.2 Reset Initialization with Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2 * VDD anytime when reset is needed (all other inputs may be
undefined). RESET needs to be maintained for minimum 100 nS. CKE is pulled “LOW” before
RESET being de-asserted (min. time 10 nS).
2. Follow Power-up Initialization Sequence steps 2 to 11.
3. The Reset sequence is now completed; DDR3 SDRAM is ready for normal operation.
Ta
Tb
Tj
Ti
Th
Tg
Tf
Te
Td
Tc
Tk
CK, CK#
tCKSRX
VDD, VDDQ
T = 100 ns
T = 500 µs
RESET#
Tmin = 10 ns
tIS
CKE
VALID
tDLLK
tZQinit
tMOD
tMRD
tMRD
tMRD
tXPR
tIS
Command
*1
BA
MRS
MRS
MRS
MRS
MR2
MR3
MR1
MR0
ZQCL
*1
VALID
tIS
ODT
VALID
tIS
Static LOW in case Rtt_Nom is enabled at time Tg, Otherwise static HIGH or LOW
VALID
RTT
TIME BREAK
DON'T CARE
Note:
1. From time point “Td” until “Tk” NOP or DES commands must be applied between MRS and ZQCL commands.
Figure 2 – Reset Procedure at Power Stable Condition
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8.3
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode
Registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed
via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not
defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e., written, after
power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by
re-executing the MRS command during normal operation. When programming the mode registers,
even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the
accessed mode register must be redefined when the MRS command is issued. MRS command and
DLL Reset do not affect array contents, which mean these commands can be executed any time after
power-up without affecting the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the
mode register and is the minimum time required between two MRS commands shown in Figure 3.
T0
T1
Command
VALID
VALID
Address
VALID
VALID
T2
Ta0
Ta1
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
VALID
MRS
NOP/DES
NOP/DES
MRS
NOP/DES
NOP/DES
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CK#
CK
CKE
Settings
Old settings
Updating Settings
Rtt_Nom ENABLED prior and/or after MRS command
ODT
New Settings
tMOD
tMRD
ODTLoff+1
VALID
VALID
VALID
Rtt_Nom DISABLED prior and/or after MRS command
ODT
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
TIME BREAK
VALID
DON'T CARE
Figure 3 – tMRD Timing
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The MRS command to Non-MRS command delay, tMOD is required for the DRAM to update the
features, except DLL reset, and is the minimum time required from a MRS command to a non-MRS
command excluding NOP and DES shown in Figure 4.
T0
T1
Command
VALID
VALID
Address
VALID
VALID
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
VALID
MRS
NOP/DES
NOP/DES
NOP/DES
NOP/DES
NOP/DES
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CK#
CK
CKE
Settings
Old settings
Updating Settings
Rtt_Nom ENABLED prior and/or after MRS command
ODT
VALID
VALID
New Settings
tMOD
VALID
ODTLoff+1
Rtt_Nom DISABLED prior and/or after MRS command
ODT
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
TIME BREAK
VALID
DON'T CARE
Figure 4 – tMOD Timing
The mode register contents can be changed using the same command and timing requirements
during normal operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state
with tRP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register.
If the Rtt_Nom Feature is enabled in the Mode Register prior and/or after a MRS command, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state prior to the MRS
command. The ODT signal may be registered high after tMOD has expired. If the Rtt_Nom feature is
disabled in the Mode Register prior and after a MRS command, the ODT signal can be registered
either LOW or HIGH before, during and after the MRS command. The mode registers are divided into
various fields depending on the functionality and/or modes.
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8.3.1 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It
controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for
precharge Power Down, which include various vendor specific options to make DDR3 SDRAM useful
for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#,
BA0, BA1 and BA2, while controlling the states of address pins according to the Figure 5 below.
BA2
BA1
BA0
0*1
0
0
A13
0*1
A8
0
1
BA1 BA0
0
0
0
1
1
0
1
1
A14
A12
PPD
A11
A10
A9
WR
DLL Reset
No
A12 DLL Control for Precharge PD
0
Slow exit (DLL off)
1
Fast exit (DLL on)
A7
DLL
TM
A7
Yes
MRS mode
MR0
MR1
MR2
MR3
A8
0
1
A6
A5
A4
CL
A3
A2
RBT
CL
A10
0
0
1
1
0
0
1
1
A0
A3
Read Burst Type
0
Nibble Sequential
Test
1
Interleave
A9
0
1
0
1
0
1
0
1
WR(cycles)
16*2
5*2
6*2
7*2
8*2
10*2
12*2
14*2
Address Field
BL
Mode
Normal
Write recovery for Auto precharge
A11
0
0
0
0
1
1
1
1
A1
Mode Register 0
A1
0
0
1
1
Burst Length
A0
BL
8 (Fixed)
0
1 BC4 or 8 (on the fly)
0
BC4 (Fixed)
1
Reserved
CAS Latency
A6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Latency
Reserved
Reserved
6
7
8
9
10
11
Reserved
13
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. BA2, A13 and A14 are reserved for future use and must be programmed to “0” during MRS.
2. WR (write recovery for Auto precharge)min in clock cycles is calculated by dividing tWR (in nS) by tCK (in nS) and rounding
up to the next integer: WRmin[cycles] = Roundup(tWR[nS] / tCK(avg)[nS]). The WR value in the mode register must be
programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported CAS Latency, please refer to “Speed
Bins” tables for each frequency.
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
Figure 5 – MR0 Definition
8.3.1.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type
is selected via bit A3 as shown in Figure 5. The ordering of accesses within a burst is determined by
the burst length, burst type, and the starting column address as shown in Table 1. The burst length is
defined by bits A0-A1. Burst length options include fixed BC4, fixed BL8 and ‘on the fly’ which allows
BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/BC#.
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Table 1 – Burst Type and Burst Order
Burst
Length
READ/
WRITE
Starting Column Address
(A2, A1, A0)
Burst type = Sequential
(decimal)
A3 = 0
Burst type = Interleaved
(decimal)
A3 = 1
NOTES
4
Chop
READ
000
0,1,2,3,T,T,T,T
0,1,2,3,T,T,T,T
1, 2, 3
001
1,2,3,0,T,T,T,T
1,0,3,2,T,T,T,T
1, 2, 3
010
2,3,0,1,T,T,T,T
2,3,0,1,T,T,T,T
1, 2, 3
011
3,0,1,2,T,T,T,T
3,2,1,0,T,T,T,T
1, 2, 3
100
4,5,6,7,T,T,T,T
4,5,6,7,T,T,T,T
1, 2, 3
101
5,6,7,4,T,T,T,T
5,4,7,6,T,T,T,T
1, 2, 3
110
6,7,4,5,T,T,T,T
6,7,4,5,T,T,T,T
1, 2, 3
WRITE
8
READ
WRITE
111
7,4,5,6,T,T,T,T
7,6,5,4,T,T,T,T
1, 2, 3
0,V,V
0,1,2,3,X,X,X,X
0,1,2,3,X,X,X,X
1, 2, 4, 5
1,V,V
4,5,6,7,X,X,X,X
4,5,6,7,X,X,X,X
1, 2, 4, 5
000
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2
001
1,2,3,0,5,6,7,4
1,0,3,2,5,4,7,6
2
010
2,3,0,1,6,7,4,5
2,3,0,1,6,7,4,5
2
011
3,0,1,2,7,4,5,6
3,2,1,0,7,6,5,4
2
100
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
2
101
5,6,7,4,1,2,3,0
5,4,7,6,1,0,3,2
2
110
6,7,4,5,2,3,0,1
6,7,4,5,2,3,0,1
2
111
7,4,5,6,3,0,1,2
7,6,5,4,3,2,1,0
2
V,V,V
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
2, 4
Notes:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the
BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being
selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation.
This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Don't Care.
8.3.1.2 CAS Latency
The CAS Latency is defined by MR0 (bits A2, A4, A5 and A6) as shown in Figure 5. CAS Latency is
the delay, in clock cycles, between the internal Read command and the availability of the first bit of
output data. DDR3 SDRAM does not support any half-clock latencies. The overall Read Latency (RL)
is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL. For more information on the
supported CL and AL settings based on the operating clock frequency, refer to section 10.15 “Speed
Bins” on page 134. For detailed Read operation refer to section 8.13 “READ Operation” on page 43.
8.3.1.3 Test Mode
The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values
shown in Figure 5. Programming bit A7 to a ‘1’ places the DDR3 SDRAM into a test mode that is only
used by the DRAM Manufacturer and should NOT be used. No operations or functionality is specified
if A7 = 1.
8.3.1.4 DLL Reset
The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset
function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any
time that the DLL reset function is used, tDLLK must be met before any functions that require the DLL
can be used (i.e., Read commands or ODT synchronous operations).
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8.3.1.5 Write Recovery
The programmed WR value MR0 (bits A9, A10 and A11) is used for the auto precharge feature along
with tRP to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by
dividing tWR (in nS) by tCK(avg) (in nS) and rounding up to the next integer: WRmin[cycles] =
Roundup(tWR[nS]/tCK(avg)[nS]). The WR must be programmed to be equal to or larger than tWR(min).
8.3.1.6 Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power down mode. When MR0 (A12
= 0), or ‘slow-exit’, the DLL is frozen after entering precharge power down (for potential power savings)
and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or
‘fast-exit’, the DLL is maintained after entering precharge power down and upon exiting power down
requires tXP to be met prior to the next valid command.
8.3.2 Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength,
Rtt_Nom impedance, additive latency, Write leveling enable, TDQS enable and Qoff. The Mode
Register 1 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and
BA2, while controlling the states of address pins according to the Figure 6 below.
BA2
BA1
BA0
A14
A13
0*1
0*1
1
BA1
BA0
MR Select
A9
A6
A2
Rtt_Nom*3
A0
0
0
MR0
0
0
0
Rtt_Nom disabled
0
Enable
1
Disable
0*1
A12
A11
A10
A9
A8
Qoff
TDQS
0*1
Rtt_Nom
0*1
A7
A6
Level Rtt_Nom
0
1
MR1
0
0
1
RZQ/4
1
0
MR2
0
1
0
RZQ/2
1
1
MR3
0
1
1
RZQ/6
A7
Write leveling enable
0
Disabled
1
Enabled
1
0
0
RZQ/12*4
1
0
1
RZQ/8*4
1
1
0
Reserved
1
1
1
Reserved
A5
A4
A3
AL
D.I.C
Note: RZQ = 240 ohms
A11
TDQS enable
0
Disable
1
Enable
A12
0
1
Qoff*2
Output buffer enabled
Output buffer disabled*2
A2
A1
A0
Address Field
Rtt_Nom
D.I.C
DLL
Mode Register 1
DLL Enable
A5
A1
Output Driver
Impedance Control
0
0
RZQ/6
0
1
RZQ/7
1
0
Reserved
1
1
Reserved
Note: RZQ = 240 ohms
A4
A3
Additive Latency
0
0
0 (AL disabled)
0
1
CL-1
1
0
CL-2
1
1
Resesved
Notes:
1. BA2, A8, A10, A13 and A14 are reserved for future use and must be programmed to “0” during MRS.
2. Outputs disabled - DQs, DQSs, DQS#s.
3. In Write leveling Mode (MR1 A[7] = 1) with MR1 A[12]=1, all Rtt_Nom settings are allowed; in Write Leveling Mode (MR1 A[7]
= 1) with MR1 A[12]=0, only Rtt_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
4. If Rtt_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
Figure 6 – MR1 Definition
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8.3.2.1 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization,
and upon returning to normal operation after having the DLL disabled. During normal operation (DLL-on)
with MR1 (A0 = 0), the DLL is automatically disabled when entering Self Refresh operation and is
automatically re-enabled upon exit of Self Refresh operation. Any time the DLL is enabled and
subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be
issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for
synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK,
CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation,
except when Rtt_WR is enabled and the DLL is required for proper ODT operation. For more detailed
information on DLL Disable operation refer to section 8.6 “DLL-off Mode” on page 25.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be
disabled by continuously registering the ODT pin low and/or by programming the Rtt_Nom bits
MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set
Rtt_WR, MR2 {A10, A9} = {0,0}, to disable Dynamic ODT externally.
8.3.2.2 Output Driver Impedance Control
The output driver impedance of the DDR3 SDRAM device is selected by MR1 (bits A1 and A5) as
shown in Figure 6.
8.3.2.3 ODT RTT Values
DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The
nominal termination value Rtt_Nom is programmed in MR1. A separate value (Rtt_WR) may be
programmed in MR2 to enable a unique RTT value when ODT is enabled during writes. The Rtt_WR
value can be applied during writes even when Rtt_Nom is disabled.
8.3.2.4 Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command
(either with or without auto-precharge) to be issued immediately after the active command. The
command is held for the time of the Additive Latency (AL) before it is issued inside the device. The
Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write
Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A
summary of the AL register options are shown in Table 2.
Table 2 – Additive Latency (AL) Settings
A4
A3
AL
0
0
0 (AL Disabled)
0
1
CL - 1
1
0
CL - 2
1
1
Reserved
Note:
AL has a value of CL - 1 or CL - 2 as per the CL values programmed in the MR0 register.
8.3.2.5 Write leveling
For better signal integrity, DDR3 memory module adopted fly-by topology for the commands,
addresses, control signals, and clocks. The fly-by topology has the benefit of reducing the number of
stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on
the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS, and tDSH specification.
Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the controller to compensate
for skew. See section 8.9 “Write Leveling” on page 30 for more details.
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8.3.2.6 Output Disable
The DDR3 SDRAM outputs may be enabled/disabled by MR1 (bit A12) as shown in Figure 6. When
this feature is enabled (A12 = 1), all output pins (DQs, DQS, DQS#, etc.) are disconnected from the
device, thus removing any loading of the output drivers. This feature may be useful when measuring
module power, for example. For normal operation, A12 should be set to ‘0’.
8.3.2.7 TDQS, TDQS#
TDQS (Termination Data Strobe) provides additional termination resistance outputs that may be useful
in some system configurations. When enabled via the mode register, the same termination resistance
function is applied to the TDQS/TDQS# pins that is applied to the DQS/DQS# pins.
In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function
only. The data strobe function of RDQS is not provided by TDQS.
The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode
register, the DM function is not supported. When the TDQS function is disabled, the DM function is
provided and the TDQS# pin is not used. See Table 3 for details.
Table 3 – TDQS, TDQS# Function Matrix
MR1 (A11)
DM / TDQS
NU / TDQS#
0 (TDQS Disabled)
DM
Hi-Z
1 (TDQS Enabled)
TDQS
TDQS#
Notes:
1. If TDQS is enabled, the DM function is disabled.
2. When not used, TDQS function can be disabled to save termination power.
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8.3.3 Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance,
and CAS write latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#,
high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the
Figure 7 below.
BA2
BA1
BA0
0*1
1
0
A14
A12
A13
A11
0*1
BA1
BA0
MR Select
0
0
MR0
0
1
MR1
1
0
MR2
1
1
MR3
A10
A9
Rtt_WR
A8
A7
A6
0*1
SRT
ASR
A2
A1
A2
A3
A4
A5
PASR
CWL
A1
A0
A0
Address Field
Mode Register 2
Partial Array Self Refresh for 8 Banks
0
0
0
Full array
0
0
1
Half Array (BA[2:0]=000,001,010 & 011)
Quarter Array (BA[2:0]=000 & 001)
0
1
0
1
1
1/8th Array (BA[2:0]=000)
A6
Auto Self Refresh (ASR)
0
0
Manual SR Reference (SRT)
1
0
0
3/4 Array (BA[2:0]=010,011,100,101,110 & 111)
1
ASR enable
1
0
1
Half Array (BA[2:0]=100,101,110 & 111)
Quarter Array (BA[2:0]=110 & 111)
A7
Self Refresh Temperature (SRT) Range
1
1
0
0
Normal operating temperature range
1
1
1
1
Extended operating temperature range
1/8th Array (BA[2:0]=111)
CAS Write Latency (CWL)
A5
A4
A3
0
0
0
5 (tCK(avg) ≥ 2.5nS)
0
0
1
6 (2.5nS > tCK(avg) ≥ 1.875nS)
RZQ/4
0
1
0
7 (1.875nS > tCK(avg) ≥ 1.5nS)
RZQ/2
0
1
1
8 (1.5nS > tCK(avg) ≥ 1.25nS)
Reserved
1
0
0
9 (1.25nS > tCK(avg) ≥ 1.07nS)
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
A10
A9
Rtt_WR*2
0
0
Dynamic ODT off
(Write does not affect Rtt value)
0
1
1
0
1
1
Notes:
1. BA2, A8, A11~A14 are reserved for future use and must be programmed to “0” during MRS.
2. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not
available.
Figure 7 – MR2 Definition
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8.3.3.1 Partial Array Self Refresh (PASR)
If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified
address range shown in Figure 7 will be lost if Self Refresh is entered. Data integrity will be
maintained if tREFI conditions are met and no Self Refresh command is issued.
8.3.3.2 CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5), as shown in Figure 7. CAS Write Latency is
the delay, in clock cycles, between the internal Write command and the availability of the first bit of
input data.
DDR3 SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined as
Additive Latency (AL) + CAS Write Latency (CWL); WL = AL + CWL. For more information on the
supported CWL and AL settings based on the operating clock frequency, refer to section 10.15
“Speed Bins” on page 134. For detailed Write operation refer to section 8.14 “WRITE Operation” on
page 56.
8.3.3.3 Auto Self Refresh (ASR) and Self Refresh Temperature (SRT)
DDR3 SDRAM must support Self Refresh operation at all supported temperatures. Applications
requiring Self Refresh operation in the Extended Temperature Range must use the ASR function or
program the SRT bit appropriately.
When ASR enabled, DDR3 SDRAM automatically provides Self Refresh power management functions
for all supported operating temperature values. If not enabled, the SRT bit must be programmed to
indicate TOPER during subsequent Self Refresh operation.
ASR = 0, Self Refresh rate is determined by SRT bit A7 in MR2.
ASR = 1, Self Refresh rate is determined by on-die thermal sensor. SRT bit A7 in MR2 is don't care.
8.3.3.4 Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further
enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3
SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10
configure the Dynamic ODT settings. In Write leveling mode, only Rtt_Nom is available. For details on
Dynamic ODT operation, refer to section 8.19.3 “Dynamic ODT” on page 83.
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8.3.4 Mode Register MR3
The Mode Register MR3 controls Multi purpose registers. The Mode Register 3 is written by asserting
low on CS#, RAS#, CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of
address pins according to the Figure 8 below.
BA2
BA1
BA0
0*1
1
1
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
0*1
A2
MPR
A1
A0
MPR Loc
Address Field
Mode Register 3
MPR Address
BA1
BA0
MR Select
0
0
MR0
0
1
MR1
1
0
MR2
1
1
MR3
MPR Operation
A2
MPR
0
Normal operation*3
1
Dataflow from MPR
A1
A0
MPR location
0
0
Predefined pattern*2
0
1
RFU
1
0
RFU
1
1
RFU
Notes:
1. BA2, A3~A14 are reserved for future use and must be programmed to “0” during MRS.
2. The predefined pattern will be used for read synchronization.
3. When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.
Figure 8 – MR3 Definition
8.3.4.1 Multi Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration
bit sequence. To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3
Register with bit A2 = 1. Prior to issuing the MRS command, all banks must be in the idle state (all
banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands
will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or RDA
commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit
A2 = 0). Power Down mode, Self Refresh, and any other non-RD/RDA command is not allowed during
MPR enable mode. The RESET function is supported during MPR enable mode. For detailed MPR
operation refer to section 8.10 “Multi Purpose Register” on page 34.
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8.4
No OPeration (NOP) Command
The No OPeration (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP
(CS# LOW and RAS#, CAS#, and WE# HIGH). This prevents unwanted commands from being
registered during idle or wait states. Operations already in progress are not affected.
8.5
Deselect Command
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR3
SDRAM. The DDR3 SDRAM is effectively deselected. Operations already in progress are not affected.
8.6
DLL-off Mode
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent
operations until A0 bit is set back to “0”. The MR1 A0 bit for DLL control can be switched either during
initialization or later. Refer to section 8.8 “Input clock frequency change” on page 28.
The DLL-off Mode operations listed below are an optional feature for DDR3. The maximum clock
frequency for DLL-off Mode is specified by the parameter tCK(DLL_OFF). There is no minimum
frequency limit besides the need to satisfy the refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS
Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of
both CL=6 and CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK), but not the Data
Strobe to Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller
time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after
the Read command, the DLL-off mode tDQSCK starts (AL+CL - 1) cycles after the read command.
Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK)
and the difference between tDQSCK min and tDQSCK max is significantly larger than in DLL-on mode.
The timing relations on DLL-off mode READ operation is shown in the following Timing Diagram
(CL=6, BL=8):
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
Address
Bank
Col b
RL (DLL_on) = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQS,DQS# (DLL_on)
DQ (DLL_on)
Dout
b
RL (DLL_off) = AL + ( CL – 1 ) = 5
Dout
b+1
Dout
b+3
Dout
b+2
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
tDQSCK(DLL_off)_min
DQS,DQS# (DLL_off)
Dout
b
DQ (DLL_off)
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
tDQSCK(DLL_on)_max
DQS,DQS# (DLL_off)
Dout
b
DQ (DLL_off)
Dout
b+1
Note:
The tDQSCK is used here for DQS, DQS# and DQ to have a simplified diagram;
the DLL_off shift will affect both timings in the same way and the skew between
all DQ, and DQS, DQS# signals will still be tDQSQ.
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
TRANSITIONING DATA
Dout
b+7
DON'T CARE
Figure 9 – DLL-off mode READ Timing Operation
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8.7
DLL on/off switching procedure
DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent
operations until A0 bit is set back to “0”.
8.7.1 DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh, as
outlined in the following procedure:
1. Starting from Idle state (All banks pre-charged, all timings fulfilled, and DRAMs On-die Termination
resistors, RTT, must be in high impedance state before MRS to MR1 to disable the DLL.)
2. Set MR1 bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Enter Self Refresh Mode; wait until (tCKSRE) is satisfied.
5. Change frequency, in guidance with section 8.8 “Input clock frequency change” on page 28.
6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all
tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled
in the mode registers when Self Refresh mode was entered, the ODT signal must continuously be
registered LOW until all tMOD timings from any MRS command are satisfied. If both ODT features
were disabled in the mode registers when Self Refresh mode was entered, ODT signal can be
registered LOW or HIGH.
8. Wait tXS, then set Mode Registers with appropriate values (especially an update of CL, CWL and
WR may be necessary. A ZQCL command may also be issued after tXS).
9. Wait for tMOD, then DRAM is ready for next command.
T0
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
CK#
CK
CKE
VALID*8
Command
MRS*2
*1
NOP
tMOD
SRE*3
SRX*6
NOP
tCKSRE
*4
tCKSRX*5
NOP
tXS
MRS*7
NOP
VALID*8
tMOD
tCKESR
ODT
VALID8
ODT: Static LOW in case Rtt_Nom and Rtt_WR is enabled, otherwise static Low or High
Notes:
1. Starting with Idle state, RTT in Hi-Z state
2. Disable DLL by setting MR1 Bit A0 to 1
3. Enter SR
4. Change Frequency
5. Clock must be stable tCKSRX
6. Exit SR
7. Update Mode register with DLL off parameters setting
8. Any valid command
TIME BREAK
DON'T CARE
Figure 10 – DLL Switch Sequence from DLL-on to DLL-off
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8.7.2 DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh:
1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination
resistors (RTT) must be in high impedance state before Self-Refresh mode is entered.)
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with section 8.8 “Input clock frequency change” on page 28.
4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until
tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features
were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must
continuously be registered LOW until tDLLK timings from subsequent DLL Reset command is
satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was
entered, ODT signal can be registered LOW or HIGH.
6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode Registers with appropriate values (especially an update of CL, CWL and
WR may be necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL
command may also be issued during or after tDLLK.)
9. Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset
before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a
ZQCL command was issued.
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf1
Tg0
Th0
CK#
CK
CKE
VALID
tDLLK
Command
NOP
*1
SRE*2
ODTLoff + 1 x tCK
SRX*5
NOP
tCKSRE
tCKSRX*4
*3
MRS*6
tXS
MRS*7
tMRD
MRS*8
VALID*9
tMRD
tCKESR
ODT
ODT: Static LOW in case Rtt_Nom and Rtt_WR is enabled, otherwise static Low or High
Notes:
1. Starting with idle state
2. Enter SR
3. Change Frequency
4. Clock must be stable tCKSRX
5. Exit SR
6. Set DLL on by MR1 A0 = 0
7. Update Mode registers
8. Any valid command
TIME BREAK
DON'T CARE
Figure 11 – DLL Switch Sequence from DLL Off to DLL On
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8.8
Input clock frequency change
Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during
almost all states of normal operation. This means that, once the clock frequency has been set and is
to be in the “stable state”, the clock period is not allowed to deviate except for what is allowed for by
the clock jitter and SSC (spread spectrum clocking) specifications.
The input clock frequency can be changed from one stable clock rate to another stable clock rate
under two conditions: (1) Self-Refresh mode and (2) Precharge Power-down mode. Outside of these
two modes, it is illegal to change the clock frequency.
8.8.1 Frequency change during Self-Refresh
For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode
and tCKSRE has been satisfied, the state of the clock becomes a don't care. Once a don't care,
changing the clock frequency is permissible, provided the new clock frequency is stable prior to
tCKSRX. When entering and exiting Self-Refresh mode for the sole purpose of changing the clock
frequency, the Self-Refresh entry and exit specifications must still be met as outlined in see section
8.16 “Self-Refresh Operation” on page 67.
The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum
operating frequency specified for the particular speed grade. Any frequency change below the
minimum operating frequency would require the use of DLL_on mode -> DLL_off mode transition
sequence; refer to section 8.7 “DLL on/off switching procedure” on page 26.
8.8.2 Frequency change during Precharge Power-down
The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit
mode or slow exit mode). If the Rtt_Nom feature was enabled in the mode register prior to entering
Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is
in an off state. If the Rtt_Nom feature was disabled in the mode register prior to entering Precharge
power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or
HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency
may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum
and maximum operating frequency specified for the particular speed grade. During the input clock
frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency
is changed, stable new clocks must be provided to the DRAM tCKSRX before Precharge Power-down
may be exited; after Precharge Power-down is exited and tXP has expired, the DLL must be RESET
via MRS. Depending on the new clock frequency, additional MRS commands may need to be issued
to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock
period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is
ready to operate with new clock frequency. This process is depicted in Figure 12 on page 29.
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Previous clock frequency
T0
CK#
CK
T1
T2
New clock frequency
Ta0
Tb0
Tc1
tCK
Td0
tCLb
tCHb
tCL
tCH
Tc0
Te0
tCLb
tCHb
tCKb
tCKSRE
Td1
Te1
tCLb
tCHb
tCKb
tCKb
tCKSRX
tCKE
tIH
tIS
tIH
CKE
tIS
tCPDED
Command
NOP
NOP
NOP
NOP
NOP
Address
MRS
NOP
VALID
DLL Reset
tXP
tAOFPD / tAOF
VALID
tIH
tIS
ODT
DQS, DQS#
High-Z
DQ
High-Z
DM
tDLLK
Enter PRECHARGE
Power-Down Mode
Frequency
Change
Exit PRECHARGE
Power-Down Mode
TIME BREAK
DON'T CARE
Notes:
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down.
2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements.
3. If the Rtt_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must
continuously be registered LOW ensuring RTT is in an off state, as shown in Figure 9. If the Rtt_Nom feature was disabled in
the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be
registered either LOW or HIGH in this case.
Figure 12 – Change Frequency during Precharge Power-down
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8.9
Write Leveling
For better signal integrity, the DDR3 memory module adopted fly-by topology for the commands,
addresses, control signals, and clocks. The fly-by topology has benefits from reducing number of
stubs and their length, but it also causes flight time skew between clock and strobe at every DRAM on
the DIMM. This makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification.
Therefore, the DDR3 SDRAM supports a ‘write leveling’ feature to allow the controller to compensate
for skew.
The memory controller can use the ‘write leveling’ feature and feedback from the DDR3 SDRAM to
adjust the DQS - DQS# to CK - CK# relationship. The memory controller involved in the leveling must
have adjustable delay setting on DQS - DQS# to align the rising edge of DQS - DQS# with that of the
clock at the DRAM pin. The DRAM asynchronously feeds back CK - CK#, sampled with the rising
edge of DQS - DQS#, through the DQ bus. The controller repeatedly delays DQS - DQS# until a
transition from 0 to 1 is detected. The DQS - DQS# delay established though this exercise would
ensure tDQSS specification.
Besides tDQSS, tDSS and tDSH specification also needs to be fulfilled. One way to achieve this is to
combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS DQS# signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH
may have to be better than the absolute limits provided in section 10.16 “AC Characteristics” in
order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is shown in Figure 13.
T0
Source
T1
T2
T3
T4
T5
T6
T7
CK#
CK
Diff_DQS
Tn
Destination
T0
CK#
CK
T2
T1
T3
T4
T5
T6
Diff_DQS
DQ
Diff_DQS
DQ
0 or 1
0
0
0
Push DQS to capture 0-1
transition
0 or 1
1
1
1
Figure 13 – Write Leveling Concept
DQS - DQS# driven by the controller during leveling mode must be terminated by the DRAM based on
ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
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8.9.1 DRAM setting for write leveling & DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set ‘High’ and after finishing leveling, DRAM exits
from write leveling mode if A7 in MR1 set ‘Low’ (Table 4). Note that in write leveling mode, only
DQS/DQS# terminations are activated and deactivated via ODT pin, unlike normal operation (Table 5).
Table 4 – MR setting involved in the leveling procedure
Function
MR1
Enable
Disable
Write leveling enable
A7
1
0
Output buffer mode (Qoff)
A12
0
1
Table 5 – DRAM termination function in the leveling mode
ODT pin @DRAM
DQS/DQS# termination
DQs termination
De-asserted
Off
Off
Asserted
On
Off
Note:
In Write Leveling Mode with its output buffer disabled (MR1 A[7] = 1 with MR1 A[12] = 1) all Rtt_Nom settings are allowed; in
Write Leveling Mode with its output buffer enabled (MR1 A[7] = 1 with MR1 A[12] = 0) only Rtt_Nom settings of RZQ/2, RZQ/4
and RZQ/6 are allowed.
8.9.2 Write Leveling Procedure
The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When
entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode,
only NOP or DESELECT commands are allowed, as well as an MRS command to change Qoff bit
(MR1[A12]) and an MRS command to exit write leveling (MR1[A7]). Upon exiting write leveling mode,
the MRS command performing the exit (MR1[A7]=0) may also change MR1 bits of A12, A11, A9, A6,
A5, A2 and A1. Since the controller levels one rank at a time, the output of other ranks must be
disabled by setting MR1 bit A12 to 1. The Controller may assert ODT after tMOD, at which time the
DRAM is ready to accept the ODT signal.
The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM
has applied on-die termination on these signals. After tDQSL and tWLMRD, the controller provides a
single DQS, DQS# edge which is used by the DRAM to sample CK - CK# driven from controller.
tWLMRD(max) timing is controller dependent.
DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on all the DQ
bits asynchronously after tWLO timing. Either one or all data bits ("prime DQ bit(s)") provide the leveling
feedback. The DRAM's remaining DQ bits are driven Low statically after the first sampling procedure.
There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is
defined from the transition of the earliest DQ bit to the corresponding transition of the latest DQ bit.
There are no read strobes (DQS/DQS#) needed for these DQs. Controller samples incoming DQ and
decides to increment or decrement DQS - DQS# delay setting and launches the next DQS/DQS#
pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the
controller locks DQS - DQS# delay setting and write leveling is achieved for the device. Figure 14
describes the timing diagram and parameters for the overall Write Leveling procedure.
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T1
T2
tWLH
tWLH
tWLS
tWLS
CK#*5
CK
Command
MRS*2
NOP*3
NOP
NOP
NOP
NOP
tDQSL*6
tDQSH*6
NOP
NOP
NOP
NOP
NOP
NOP
tMOD
ODT
tWLDQSEN
Diff_DQS
tDQSL*6
tDQSH*6
*4
One Prime DQ:
tWLMRD
tWLO
tWLO
Prime DQ*1
tWLO
Late Remaining DQs
Early Remaining DQs
tWLO
All DQs are Prime:
tWLMRD
tWLOE
tWLO
tWLO
Late Prime DQs*1
tWLOE
Early Prime DQs*1
tWLO
tWLOE
UNDEFINED DRIVING MODE
tWLO
TIME BREAK
DON'T CARE
Notes:
1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the
remaining DQs must be driven low, as shown in above Figure, and maintained at this state through out the leveling
procedure.
2. MRS: Load MR1 to enter write leveling mode.
3. NOP: NOP or Deselect.
4. Diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with
solid line, DQS# is shown with dotted line.
5. CK, CK#: CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the
max pulse width is system dependent.
Figure 14 – Timing details of Write leveling sequence [DQS - DQS# is capturing CK - CK# low at
T1 and CK - CK# high at T2]
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8.9.3 Write Leveling Mode Exit
The following sequence describes how the Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From
now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the
respective MR command (Te1).
2. Drive ODT pin low (tIS must be satisfied) and continue registering low. (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be
issued after tMRD (Td1).
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Te0
Te1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
VALID
NOP
VALID
CK#
CK
Command
tMRD
Address
MR1
VALID
tIS
VALID
tMOD
ODT
ODTLoff
RTT_DQS_DQS#
tAOFmin
Rtt_Nom
tAOFmax
DQS_DQS#
RTT_DQ
DQ*1
tWLO + tWLOE
result = 1
UNDEFINED DRIVING MODE
TRANSITIONING
TIME BREAK
DON'T CARE
Note:
1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS, DQS# signals capturing CK high just after the T0 state.
Figure 15 – Timing details of Write leveling exit
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8.10 Multi Purpose Register
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration
bit sequence. The basic concept of the MPR is shown in Figure 16.
Memory Core
(all banks precharged)
MR3 [A2]
Multipurpose register
Pre-defined data for Reads
DQ, DM, DQS, DQS#
Figure 16 – MPR Block Diagram
To enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 Register with bit
A2 = 1, as shown in Table 6. Prior to issuing the MRS command, all banks must be in the idle state (all
banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands
will be redirected to the Multi Purpose Register. The resulting operation, when a RD or RDA command
is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown in Table 7. When the
MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued
with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode RDA has the same functionality as a
READ command which means the auto precharge part of RDA is ignored. Power-Down mode, SelfRefresh, and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET
function is supported during MPR enable mode.
Table 6 – MPR Functional Description of MR3 Bits
MR3 A[2]
MR3 A[1:0]
Function
MPR
MPR-Loc
0b
don't care
(0b or 1b)
Normal operation, no MPR transaction
All subsequent Reads will come from DRAM array
All subsequent Write will go to DRAM array
1b
See Table 7
Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]
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8.10.1 MPR Functional Description
One bit wide logical interface via all DQ pins during READ operation.
Register Read:
—DQ[0] drives information from MPR
—DQ[7:1] either drive the same information as DQ [0], or they drive 0b
Addressing during for Multi Purpose Register reads for all MPR agents:
— BA[2:0]: Don't care
— A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
— A[2]: A[2] selects the burst order
For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *)
For Burst Chop 4 cases, the burst order is switched on nibble base
A[2]=0b, Burst order: 0,1,2,3 *)
A[2]=1b, Burst order: 4,5,6,7 *)
— A[9:3]: Don't care
— A10/AP: Don't care
— A12/BC#: Selects burst chop mode on-the-fly, if enabled within MR0
— A11, A13 and A14: Don't care
Regular interface functionality during register reads:
— Support two Burst Ordering which are switched with A2 and A[1:0]=00b
— Support of read burst chop (MRS and on-the-fly via A12/BC#)
— All other address bits (remaining column address bits including A10, all bank address bits) will
be ignored by the DDR3 SDRAM
— Regular read latencies and AC timings apply
— DLL must be locked prior to MPR Reads
Note:
*) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
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8.10.2 MPR Register Address Definition
Table 7 provides an overview of the available data locations, how they are addressed by MR3 A[1:0]
during a MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi
Purpose Register Read.
Table 7 – MPR Readouts and Burst Order Bit Mapping
MR3 A[2]
1b
1b
1b
1b
MR3 A[1:0]
00b
Function
Read Pre-defined Pattern
for System Calibration
01b
10b
11b
RFU
RFU
RFU
Burst
Length
Read
Address
A[2:0]
Burst Order and Data Pattern
BL8
000b
Burst order 0,1,2,3,4,5,6,7
Pre-defined Data Pattern [0,1,0,1,0,1,0,1]
BC4
000b
Burst order 0,1,2,3
Pre-defined Data Pattern [0,1,0,1]
BC4
100b
Burst order 4,5,6,7
Pre-defined Data Pattern [0,1,0,1]
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
BL8
000b
Burst order 0,1,2,3,4,5,6,7
BC4
000b
Burst order 0,1,2,3
BC4
100b
Burst order 4,5,6,7
Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.
8.10.3 Relevant Timing Parameters
The following AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD,
tMOD, and tMPRR. For more details refer to section 10.16 “AC Characteristics” on page 138.
8.10.4 Protocol Example
Protocol Example (This is one example):
Read out pre-determined read-calibration pattern.
Description: Multiple reads from Multi Purpose Register, in order to do system level read timing
calibration based on pre-determined and standardized pattern.
Protocol Steps:
Precharge All.
Wait until tRP is satisfied.
Set MRS, “MR3 A[2] = 1b” and “MR3 A[1:0] = 00b”.
This redirects all subsequent reads and load pre-defined pattern into Multi Purpose Register.
Wait until tMRD and tMOD are satisfied (Multi Purpose Register is then ready to be read). During the
period MR3 A[2] =1, no data write operation is allowed.
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Read:
A[1:0] = ‘00’b (Data burst order is fixed starting at nibble, always 00b here)
A[2] = ‘0’b (For BL=8, burst order is fixed as 0,1,2,3,4,5,6,7)
A12/BC# = 1 (use regular burst length of 8)
All other address pins (including BA[2:0] and A10/AP): don't care
After RL = AL + CL, DRAM bursts out the pre-defined Read Calibration Pattern.
Memory controller repeats these calibration reads until read data capture at memory controller is
optimized.
After end of last MPR read burst, wait until tMPRR is satisfied.
Set MRS, “MR3 A[2] = 0b” and “MR3 A[1:0] = don't care” to the normal DRAM state.
All subsequent read and write accesses will be regular reads and writes from/to the DRAM array.
Wait until tMRD and tMOD are satisfied.
Continue with “regular” DRAM commands, like activate a memory bank for regular read or write
access,...
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T0
Ta
Tb0
Tb1
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
PREA
MRS
READ*1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
Td
CK#
CK
Command
tMPRR
tMOD
tRP
tMOD
BA
3
VALID
3
A[1:0]
0
0*2
VALID
A[2]
1
0*2
0
A[9:3]
00
VALID
00
0
VALID
0
A[11]
0
VALID
0
A12/BC#
0
VALID*1
0
A10/AP
1
VALID
RL
DQS, DQS#
DQ
NOTES:
TIME BREAK
1. RD with BL8 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[2:0].
DON'T CARE
Figure 17 – MPR Readout of pre-defined pattern, BL8 fixed burst order, single readout
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T0
Ta
Tb0
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
T10
PREA
MRS
READ*1
READ*1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
Td
CK#
CK
Command
tRP
tMOD
tCCD
tMPRR
tMOD
BA
3
VALID
VALID
3
A[1:0]
0
0*2
0*2
VALID
A[2]
1
0*2
0*2
0
A[9:3]
00
VALID
VALID
00
0
VALID
VALID
0
A[11]
0
VALID
VALID
0
A12/BC#
0
VALID*1
VALID*1
0
A10/AP
1
VALID
RL
DQS, DQS#
RL
DQ
NOTES:
TIME BREAK
1. RD with BL8 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[2:0].
DON'T CARE
Figure 18 – MPR Readout of pre-defined pattern, BL8 fixed burst order, back-to-back readout
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T0
Ta
Tb0
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
T10
PREA
MRS
READ*1
READ*1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
Td
CK#
CK
Command
tMPRR
tCCD
tMOD
tRP
tMOD
BA
3
VALID
VALID
3
A[1:0]
0
0*2
0*2
VALID
A[2]
1
0*3
1*4
0
A[9:3]
00
VALID
VALID
00
0
VALID
VALID
0
A[11]
0
VALID
VALID
0
A12/BC#
0
VALID*1
VALID*1
0
A10/AP
1
VALID
RL
DQS, DQS#
RL
DQ
TIME BREAK
NOTES:
DON'T CARE
1. RD with BC4 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
Figure 19 – MPR Readout pre-defined pattern, BC4, lower nibble then upper nibble
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T0
Ta
Tb0
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
T10
PREA
MRS
READ*1
READ*1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
Td
CK#
CK
Command
tMPRR
tCCD
tMOD
tRP
tMOD
BA
3
VALID
VALID
3
A[1:0]
0
0*2
0*2
VALID
A[2]
1
1*4
0*3
0
A[9:3]
00
VALID
VALID
00
0
VALID
VALID
0
A[11]
0
VALID
VALID
0
A12/BC#
0
VALID*1
VALID*1
0
A10/AP
1
VALID
RL
DQS, DQS#
RL
DQ
TIME BREAK
NOTES:
DON'T CARE
1. RD with BC4 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
Figure 20 – MPR Readout of pre-defined pattern, BC4, upper nibble then lower nibble
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8.11 ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent
access. The value on the BA0-BA2 inputs selects the bank, and the address provided on inputs A0A14 selects the row. This row remains active (or open) for accesses until a precharge command is
issued to that bank. A PRECHARGE command must be issued before opening a different row in the
same bank.
8.12 PRECHARGE Command
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row
in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after
the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a
READ or WRITE command to a different bank is allowed as long as it does not interrupt the data
transfer in the current bank and does not violate any other timing parameters. Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being
issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle
state) or if the previously open row is already in the process of precharging. However, the precharge
period will be determined by the last PRECHARGE command issued to the bank.
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8.13 READ Operation
8.13.1 READ Burst Operation
During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12
during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled).
A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
A12 = 1, BL8
A12 is used only for burst length control, not as a column address.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
Address*4
Bank
Col n
tRPST
tRPRE
DQS, DQS#
DQ*2
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
CL = 6
RL = AL + CL
TRANSITIONING DATA
DON'T CARE
Notes:
1. BL8, RL = 6, AL = 0, CL = 6.
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
Figure 21 – READ Burst Operation RL = 6 (AL = 0, CL = 6, BL8)
T0
T1
T5
T6
T10
T11
T12
T13
T14
T15
T16
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
Address*4
Bank
Col n
tRPST
tRPRE
DQS, DQS#
DQ*2
Dout
n
AL = 5
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
CL = 6
RL = AL + CL
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Notes:
1. BL8, RL = 11, AL = (CL - 1), CL = 6.
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
Figure 22 – READ Burst Operation RL = 11 (AL = 5, CL = 6, BL8)
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8.13.2 READ Timing Definitions
Read timing is shown in Figure 23 and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK#.
tDQSCK is the actual position of a rising strobe edge relative to CK, CK#.
tQSH describes the DQS, DQS# differential output high time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tQSL describes the DQS, DQS# differential output low time.
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
tDQSQ; both rising/falling edges of DQS, no tAC defined.
CK#
CK
tDQSCK(min)
tDQSCK(min)
tDQSCK(max)
tDQSCK(max)
Rising Strobe
Region
Rising Strobe
Region
tDQSCK
tDQSCK
tQSH
tQSL
tQH
tQH
tDQSQ
DQS#
DQS
tDQSQ
Associated
DQ Pins
Figure 23 – READ Timing Definition
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8.13.2.1 READ Timing; Clock to Data Strobe relationship
Clock to Data Strobe relationship is shown in Figure 24 and is applied when the DLL is enabled and
locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK#.
tDQSCK is the actual position of a rising strobe edge relative to CK, CK#.
tQSH describes the data strobe high pulse width.
Falling data strobe edge parameters:
tQSL describes the data strobe low pulse width.
tLZ(DQS), tHZ(DQS) for preamble/postamble (see section 8.13.2.3 and Figure 26).
RL Measured
to this point
CK/CK#
tDQSCK(min)
tDQSCK(min)
tDQSCK(min)
tDQSCK(min)
tHZ(DQS)min
tQSH
tLZ(DQS)min
tQSL
tQSH
tQSL
tQSH
tQSL
DQS, DQS#
Erly Strobe
tRPST
tRPRE
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
tHZ(DQS)max
tDQSCK(max)
tDQSCK(max)
tDQSCK(max)
tDQSCK(max)
tLZ(DQS)max
tRPST
DQS, DQS#
Late Strobe
tQSH
tQSL
tQSH
tQSH
tQSL
tQSL
tRPRE
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Notes:
1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe
edge can vary between tDQSCK(min) and tDQSCK(max).
2. Not with standing note 1, a rising strobe edge with tDQSCK(max) at T(n) can not be immediately followed by a rising strobe
edge with tDQSCK(min) at T(n+1). This is because other timing relationships (tQSH, tQSL) exist:
if tDQSCK(n+1) < 0:
tDQSCK(n) < 1.0 tCK - (tQSHmin + tQSLmin) - | tDQSCK(n+1) |
3. The DQS, DQS# differential output high time is defined by tQSH and the DQS, DQS# differential output low time is defined by
tQSL.
4. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCK,min (early strobe case) and tLZ(DQS)max and tHZ(DQS)max
are not tied to tDQSCK,max (late strobe case).
5. The minimum pulse width of read preamble is defined by tRPRE(min).
6. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.
7. The minimum pulse width of read postamble is defined by tRPST(min).
8. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
Figure 24 – Clock to Data Strobe Relationship
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8.13.2.2 READ Timing; Data Strobe to Data relationship
The Data Strobe to Data relationship is shown in Figure 25 and is applied when the DLL is enabled
and locked.
Rising data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
tDQSQ describes the latest valid transition of the associated DQ pins.
tQH describes the earliest invalid transition of the associated DQ pins.
tDQSQ; both rising/falling edges of DQS, no tAC defined.
T0
T1
READ
NOP
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
NOP
RL = AL + CL
Address*4
Bank
Col n
tDQSQ(max)
tDQSQ(max)
tRPST
DQS, DQS#
tRPRE
tQH
tQH
Dout
n
DQ*2 (Last data valid)
Dout
n
DQ*2 (first data no longer valid)
Dout
n
All DQs collectively
Dout
n+1
Dout
n+1
Dout
n+1
Dout
n+2
Dout
n+2
Dout
n+2
Dout
n+3
Dout
n+3
Dout
n+3
Dout
n+4
Dout
n+4
Dout
n+4
Dout
n+5
Dout
n+5
Dout
n+5
TRANSITIONING DATA
Dout
n+6
Dout
n+6
Dout
n+6
Dout
n+7
Dout
n+7
Dout
n+7
DON'T CARE
Notes:
1. BL = 8, RL = 6 (AL = 0, CL = 6).
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
5. Output timings are referenced to VDDQ/2, and DLL on for locking.
6. tDQSQ defines the skew between DQS, DQS# to Data and does not define DQS, DQS# to Clock.
7. Early Data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within
a burst.
Figure 25 – Data Strobe to Data Relationship
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8.13.2.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation
tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are
referenced to a specific voltage level that specifies when the device output is no longer driving tHZ(DQS)
and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ). Figure 26 shows a method to calculate the point when
the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ), by measuring
the signal at two different voltages. The actual voltage measurement points are not critical as long as
the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as
singled ended.
tLZ(DQS): CK – CK# rising crossing at RL - 1
tLZ(DQ): CK – CK# rising crossing at RL
tHZ(DQS), tHZ(DQ) with BL8: CK – CK# rising crossing at RL + 4 nCK
tHZ(DQS), tHZ(DQ) with BC4: CK – CK# rising crossing at RL + 2 nCK
CK
CK
CK#
CK#
tLZ
tHZ
VOH - x mV
VTT + 2x mV
VTT + x mV
VOH - 2x mV
tLZ(DQS), tLZ(DQ)
VTT - x mV
tHZ(DQS), tHZ(DQ)
T1
VTT - 2x mV
T2
T2
T1
tLZ(DQS), tLZ(DQ) begin point = 2 * T1 - T2
VOL + 2x mV
VOL + x mV
tHZ(DQS), tHZ(DQ) end point = 2 * T1 - T2
Figure 26 – tLZ and tHZ method for calculating transitions and endpoints
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8.13.2.4 tRPRE Calculation
The method for calculating differential pulse widths for tRPRE is shown in Figure 27.
CK
VTT
CK#
tA
tB
VTT
DQS
Single ended signal, provided
as background information
tC
tD
DQS#
VTT
Single ended signal, provided
as background information
t1
tRPRE_begin
tRPRE
DQS - DQS#
0
Resulting differential signal,
relevant for tRPRE specification
t2
tRPRE_end
Figure 27 – Method for calculating tRPRE transitions and endpoints
8.13.2.5 tRPST Calculation
The method for calculating differential pulse widths for tRPST is shown in Figure 28.
CK
VTT
CK#
tA
DQS
Single ended signal, provided
as background information
VTT
tB
tC
tD
DQS#
VTT
Single ended signal, provided
as background information
tRPST
DQS - DQS#
Resulting differential signal,
relevant for tRPST specification
0
t1
tRPST_begin
t2
tRPST_end
Figure 28 – Method for calculating tRPST transitions and endpoints
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
tCCD
Address*4
Bank
Col b
Bank
Col n
tRPST
tRPRE
DQS, DQS#
DQ*2
Dout
n
RL = 6
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
RL = 6
NOTES: 1. BL8, RL = 6 (CL = 6, AL = 0).
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ commands at T0 and T4.
DON'T CARE
TRANSITIONING DATA
Figure 29 – READ (BL8) to READ (BL8)
T0
T1
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
tCCD = 5
Address*4
Bank
Col b
Bank
Col n
tRPST
tRPRE
DQS, DQS#*5
DQ*2
RL = 6
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
b
Dout
n+7
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
RL = 6
NOTES: 1. BL8, RL = 6 (CL = 6, AL = 0), tCCD = 5.
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ commands at T0 and T5.
5. DQS-DQS# is held logic low at T10.
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 30 – Nonconsecutive READ (BL8) to READ (BL8), tCCD=5
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
tCCD
Address*4
Bank
Col n
Bank
Col b
tRPRE
tRPST
tRPRE
tRPST
DQS, DQS#
Dout
n
DQ*2
RL = 6
Dout
n+1
Dout
n+2
Dout
n+3
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
RL = 6
NOTES: 1. BC4, RL = 6 (CL = 6, AL = 0)
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by either MR0 A[1:0] = 10 or MR0 A[1:0] = 01 and A12 = 0 during READ commands at T0 and T4.
TRANSITIONING DATA
DON'T CARE
Figure 31 – READ (BC4) to READ (BC4)
T0
T1
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T14
T15
T16
NOP
NOP
NOP
CK#
CK
Command*3
READ
Address*4
tWR
tWTR
4 clocks
READ to WRITE Command Delay = RL + tCCD + 2tCK - WL
Bank
Col n
Bank
Col b
tRPST
tRPRE
tWPST
tWPRE
DQS, DQS#
DQ*2
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
RL = 6
Dout
n+5
Dout
n+6
Dout
n+7
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
WL = 5
NOTES: 1. BL8, RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, Din b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0 and WRITE command at T7.
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 32 – READ (BL8) to WRITE (BL8)
Publication Release Date: Dec. 08, 2014
Revision: A04
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T0
T1
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T12
T13
T14
T15
T16
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
READ
tWR
4 clocks
READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
tWTR
*4
Address
Bank
Col b
Bank
Col n
tRPST
tRPRE
tWPST
tWPRE
DQS, DQS#
DQ*2
Dout
n
RL = 6
Dout
n+1
Dout
n+2
Din
b
Dout
n+3
Din
b+1
Din
b+2
Din
b+3
WL = 5
NOTES: 1. BC4, RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, DIN b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T0 and WRITE command at T5.
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 33 – READ (BC4) to WRITE (BC4) OTF
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
tCCD
Address*4
Bank
Col b
Bank
Col n
tRPRE
tRPST
DQS, DQS#
DQ*2
RL = 6
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
RL = 6
NOTES: 1. RL = 6 (CL = 6, AL = 0).
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T4.
TRANSITIONING DATA
DON'T CARE
Figure 34 – READ (BL8) to READ (BC4) OTF
Publication Release Date: Dec. 08, 2014
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
tCCD
Address*4
Bank
Col b
Bank
Col n
tRPRE
tRPST
tRPST
tRPRE
DQS, DQS#
Dout
n
DQ*2
RL = 6
Dout
n+1
Dout
n+2
Dout
n+3
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
RL = 6
NOTES: 1. RL = 6 (CL = 6, AL = 0)
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T0.
BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during READ command at T4.
DON'T CARE
TRANSITIONING DATA
Figure 35 – READ (BC4) to READ (BL8) OTF
T0
T1
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T12
T13
T14
T15
T16
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
READ
tWR
4 clocks
READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
tWTR
Address*4
Bank
Col b
Bank
Col n
tRPST
tRPRE
tWPST
tWPRE
DQS, DQS#
DQ*2
RL = 6
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
WL = 5
NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, Din b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T0.
BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T5.
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 36 – READ (BC4) to WRITE (BL8) OTF
Publication Release Date: Dec. 08, 2014
Revision: A04
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T0
T1
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
NOP
NOP
NOP
READ
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T14
T15
T16
NOP
NOP
NOP
CK#
CK
Command*3
READ
4 clocks
READ to WRITE Command Delay = RL + tCCD + 2tCK - WL
Address*4
Bank
Col n
tWR
tWTR
Bank
Col b
tRPST
tRPRE
tWPST
tWPRE
DQS, DQS#
DQ*2
RL = 6
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
Din
b
Din
b+1
Din
b+2
Din
b+7
WL = 5
NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, Din b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T7.
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 37 – READ (BL8) to WRITE (BC4) OTF
Publication Release Date: Dec. 08, 2014
Revision: A04
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8.13.2.6 Burst Read Operation followed by a Precharge
The minimum external Read command to Precharge command spacing to the same bank is equal to AL + tRTP with tRTP being the Internal Read
Command to Precharge Command Delay. Note that the minimum ACT to PRE timing, tRAS.MIN must be satisfied as well. The minimum value for the
Internal Read Command to Precharge Command Delay is given by tRTP.MIN = max(4 × nCK, 7.5 nS). A new bank active command may be issued to the
same bank if the following two conditions are satisfied simultaneously:
1. The minimum RAS precharge time (tRP.MIN) has been satisfied from the clock at which the precharge begins.
2. The minimum RAS cycle time (tRC.MIN) from the previous bank activation has been satisfied.
Examples of Read commands followed by Precharge are show in Figure 38 and Figure 39.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
NOP
READ
NOP
NOP
NOP
PRE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
NOP
CK#
CK
Command
Bank a,
(or all)
Bank a,
Col n
Address
Bank a,
Row b
tRTP
tRP
RL = AL + CL = 9
DQS, DQS#
BL4 Operation:
DQ
DQS, DQS#
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
BL8 Operation:
DQ
NOTES: 1. RL = 9 (CL = 9, AL = 0)
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T5) and that tRC.MIN is satisfied at the next Active command time (T14).
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
TRANSITIONING DATA
DON'T CARE
Figure 38 – READ to PRECHARGE (RL = 9, AL = 0, CL = 9, tRTP = 4, tRP = 9)
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T0
T1
T2
T10
T11
T16
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
NOP
READ
NOP
NOP
NOP
PRE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ACT
CK#
CK
Command
Bank a,
(or all)
Bank a,
Col n
Address
Bank a,
Row b
tRTP
tRP
AL = CL - 2 = 9
CL = 11
RL = 20
DQS, DQS#
BL4 Operation:
DQ
DQS, DQS#
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
BL8 Operation:
DQ
NOTES: 1. RL = 20 (CL = 11, AL = CL - 2)
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T16) and that tRC.MIN is satisfied at the next Active command time (T27).
Dout
n+4
Dout
n+5
TIME BREAK
Dout
n+6
Dout
n+7
TRANSITIONING DATA
DON'T CARE
Figure 39 – READ to PRECHARGE (RL = 20, AL = CL-2, CL = 11, tRTP = 6, tRP = 11)
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8.14 WRITE Operation
8.14.1 DDR3 Burst Operation
During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12
during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled).
A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
A12 = 1, BL8
A12 is used only for burst length control, not as a column address.
8.14.2 WRITE Timing Violations
8.14.2.1 Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be
initiated to make sure that the DRAM works properly. However, it is desirable; for certain minor
violations, that the DRAM is guaranteed not to “hang up”, and that errors are limited to that particular
operation.
For the following, it will be assumed that there are no timing violations with regards to the Write
command itself (including ODT, etc.) and that it does satisfy all timing requirements not mentioned
below.
8.14.2.2 Data Setup and Hold Violations
Should the data to strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges
associated with a write burst, and then wrong data might be written to the memory location addressed
with this WRITE command.
In the example (Figure 40 on page 57), the relevant strobe edges for write burst A are associated with
the clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5.
Subsequent reads from that location might result in unpredictable read data, however the DRAM will
work properly otherwise.
8.14.2.3 Strobe to Strobe and Strobe to Clock Violations
Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing
requirements (tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst,
then wrong data might be written to the memory location addressed with the offending WRITE
command. Subsequent reads from that location might result in unpredictable read data, however the
DRAM will work properly otherwise.
In the example (Figure 48 on page 61) the relevant strobe edges for Write burst n are associated with
the clock edges: T4, T4.5, T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5 and T9. Any timing requirements
starting or ending on one of these strobe edges need to be fulfilled for a valid burst. For Write burst b
the relevant edges are T8, T8.5, T9, T9.5, T10, T10.5, T11, T11.5, T12, T12.5 and T13. Some edges
are associated withboth bursts.
8.14.2.4 Write Timing Parameters
This drawing is for example only to enumerate the strobe edges that “belong” to a Write burst. No
actual timing violations are shown here. For a valid burst all timing parameters for each edge of a
burst need to be satisfied (not only for one edge - as shown).
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T0
T1
WRITE
NOP
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
NOP
WL = AL + CWL
Address*4
Bank
Col n
tDQSS tDSH
tDQSS (min)
tDSH
tDSH
tDSH
tWPRE(min)
tWPST(min)
DQS, DQS#
tDQSH(min)
tDQSL
tDQSH
tDQSL
tDSS
*2
Din
n
DQ
tDQSH
tDQSL
tDSS
tDQSH
tDQSL
Din
n+2
Din
n+3
tDQSH
tDQSL(min)
tDSS
tDSS
Din
n+4
tDSS
Din
n+6
Din
n+7
DM
tDQSS (nominal)
tDSH
tWPRE(min)
tDSH
tDSH
tDSH
tWPST(min)
DQS, DQS#
tDQSH(min)
tDQSL
tDQSH
tDQSL
tDSS
*2
Din
n
DQ
tDQSH
tDQSL
tDSS
tDQSH
tDSS
Din
n+2
Din
n+3
tDQSL
tDQSH
tDQSL(min)
tDSS
Din
n+4
tDSS
Din
n+6
Din
n+7
DM
tDQSS
tDQSS (max)
tWPRE(min)
tDSH
tDSH
tDSH
tDSH
tWPST(min)
DQS, DQS#
tDQSH(min)
tDQSL
tDQSH
tDSS
Din
n
DQ
tDQSL
tDQSH
tDSS
tDQSL
tDQSH
tDSS
Din
n+2
Din
n+3
tDQSL
tDQSH
tDSS
Din
n+4
tDQSL(min)
tDSS
Din
n+6
Din
n+7
DM
TRANSITIONING DATA
DON'T CARE
Notes:
1. BL8, WL = 5 (AL = 0, CWL = 5)
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
Figure 40 – Write Timing Definition and Parameters
8.14.3 Write Data Mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3 SDRAMs,
consistent with the implementation on DDR2 SDRAMs. It has identical timings on write operations as
the data bits as shown in Figure 40, and though used in a unidirectional manner, is internally loaded
identically to data bits to ensure matched system timing. DM is not used during read cycles, however,
DM can be used as TDQS during write cycles if enabled by the MR1[A11] setting. See section 8.3.2.7
“TDQS, TDQS#” on page 21 for more details on TDQS vs. DM operations.
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8.14.4 tWPRE Calculation
The method for calculating differential pulse widths for tWPRE is shown in Figure 41.
CK
VTT
CK#
t1
tWPRE_begin
DQS - DQS#
0V
tWPRE
Resulting differential signal,
relevant for tWPRE specification
t2
tWPRE_end
Figure 41 – Method for calculating tWPRE transitions and endpoints
8.14.5 tWPST Calculation
The method for calculating differential pulse widths for tWPST is shown in Figure 42.
CK
VTT
CK#
tWPST
DQS - DQS#
Resulting differential signal,
relevant for tWPST specification
0V
t1
tWPST_begin
t2
tWPST_end
Figure 42 – Method for calculating tWPST transitions and endpoints
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
WL = AL + CWL
Address*4
Bank
Col n
tWPST
tWPRE
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
Din
n+4
Din
n+5
Din
n+6
Din
n+7
TRANSITIONING DATA
DON'T CARE
Notes:
1. BL8, WL = 5; AL = 0, CWL = 5.
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
Figure 43 – WRITE Burst Operation WL = 5 (AL = 0, CWL = 5, BL8)
T0
T1
T5
NOP
NOP
T6
T9
T10
T11
T12
T13
T14
T15
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command*3
WRITE
AL = 5
Address*4
CWL = 5
Bank
Col n
tWPST
tWPRE
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
Din
n+4
Din
n+5
Din
n+6
Din
n+7
WL = AL + CWL
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Notes:
1. BL8, WL = 10; AL = CL - 1, CL = 6, CWL = 5.
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
Figure 44 – WRITE Burst Operation WL = 10 (AL = CL-1, CWL = 5, BL8)
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
CK#
CK
Command*3
tWTR*5
Address*4
Bank
Col n
Bank
Col b
tWPRE
tWPST
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
WL = 5
RL = 6
DON'T CARE
TRANSITIONING DATA
TIME BREAK
Notes:
1. BC4, WL = 5, RL = 6.
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0 and READ command at Tn.
5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data
shown at T7.
Figure 45 – WRITE (BC4) to READ (BC4) Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
CK#
CK
Command*3
tWR*5
Address*4
Bank
Col n
tWPRE
tWPST
DQS, DQS#
DQ*2
Din
n
Din
n+1
Din
n+2
Din
n+3
WL = 5
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Notes:
1. BC4, WL = 5, RL = 6.
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0.
5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7. tWR specifies
the last burst write cycle until the precharge command can be issued to the same bank.
Figure 46 – WRITE (BC4) to PRECHARGE Operation
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T0
T1
T2
T3
T4
T5
T6
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T7
T8
T9
T10
NOP
NOP
NOP
NOP
T11
Ta0
Ta1
T14
NOP
PRE
NOP
NOP
CK#
CK
Command*3
4 clocks
Address*4
tWR*5
Bank
Col n
VALID
tWPRE
tWPST
DQS, DQS#
Din
n
DQ*2
WL = 5
NOTES:
Din
n+1
Din
n+2
Din
n+3
1. BC4 on the fly, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 on the fly setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0.
5. The write recovery time (tWR) starts at the rising clock edge T9 (4 clocks from T5).
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 47 – WRITE (BC4) OTF to PRECHARGE Operation
T0
T1
WRITE
NOP
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T11
T12
T13
T14
NOP
NOP
NOP
NOP
CK#
CK
Command*3
tWR
4 clocks
tCCD
tWTR
Address*4
Bank
Col n
Bank
Col b
tWPST
tWPRE
DQS, DQS#
DQ*2
WL = 5
Din
n
Din
n+1
Din
n+2
Din
n+3
Din
n+4
Din
n+5
Din
n+6
Din
n+7
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
WL = 5
NOTES: 1. BL8, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0 and T4.
5. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T13.
TRANSITIONING DATA
DON'T CARE
Figure 48 – WRITE (BL8) to WRITE (BL8)
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T0
T1
WRITE
NOP
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T11
T12
T13
NOP
NOP
NOP
T14
CK#
CK
Command*3
tWTR
Bank
Col b
Bank
Col n
Address*4
NOP
tWR
4 clocks
tCCD
tWPST
tWPRE
tWPST
tWPRE
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
WL = 5
WL = 5
1. BC4, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0 and T4.
5. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge at T13 (4 clocks from T9).
NOTES:
TRANSITIONING DATA
DON'T CARE
Figure 49 – WRITE (BC4) to WRITE (BC4) OTF
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
NOP
CK#
CK
Command*3
tWTR
Address*4
Bank
Col b
Bank
Col n
tWPST
tWPRE
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
Din
n+4
Din
n+5
Din
n+6
Din
n+7
WL = 5
NOTES:
RL = 6
1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
READ command at T13 can be either BC4 or BL8 depending on MR0 A[1:0] and A12 status at T13.
TRANSITIONING DATA
DON'T CARE
Figure 50 – WRITE (BL8) to READ (BC4/BL8) OTF
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T0
T1
T2
T3
T4
T5
T6
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T7
T8
T9
T10
T11
T12
T13
T14
NOP
NOP
NOP
NOP
NOP
NOP
READ
NOP
CK#
CK
Command*3
tWTR
4 clocks
Address*4
Bank
Col b
Bank
Col n
tWPST
tWPRE
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
WL = 5
NOTES:
RL = 6
1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0.
READ command at T13 can be either BC4 or BL8 depending on MR0 A[1:0] and A12 status at T13.
TRANSITIONING DATA
DON'T CARE
Figure 51 – WRITE (BC4) to READ (BC4/BL8) OTF
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ
NOP
NOP
NOP
CK#
CK
Command*3
tWTR
Address*4
Bank
Col b
Bank
Col n
tWPST
tWPRE
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
WL = 5
NOTES:
RL = 6
1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL =5, AL = 0)
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 10.
TRANSITIONING DATA
DON'T CARE
Figure 52 – WRITE (BC4) to READ (BC4)
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
WRITE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T11
T12
T13
NOP
NOP
NOP
T14
CK#
CK
Command*3
NOP
tWR
4 clocks
tCCD
tWTR
Address*4
Bank
Col b
Bank
Col n
tWPST
tWPRE
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
Din
n+4
Din
n+5
Din
n+6
Din
n+7
Din
b
Din
b+1
Din
b+2
Din
b+3
WL = 5
WL = 5
NOTES:
1. WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T4.
TRANSITIONING DATA
DON'T CARE
Figure 53 – WRITE (BL8) to WRITE (BC4) OTF
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
WRITE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
T11
T12
T13
NOP
NOP
NOP
T14
CK#
CK
Command*3
tCCD
NOP
tWR
4 clocks
tWTR
Address*4
Bank
Col b
Bank
Col n
tWPST
tWPRE
tWPST
tWPRE
DQS, DQS#
Din
n
DQ*2
Din
n+1
Din
n+2
Din
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
B+4
Din
b+5
Din
b+6
Din
b+7
WL = 5
WL = 5
NOTES:
1. WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T4.
TRANSITIONING DATA
DON'T CARE
Figure 54 – WRITE (BC4) to WRITE (BL8) OTF
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8.15 Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3 SDRAMs. This command
is non persistent, so it must be issued each time a refresh is required. The DDR3 SDRAM requires
Refresh cycles at an average periodic interval of tREFI. When CS#, RAS# and CAS# are held Low and
WE# High at the rising edge of the clock, the chip enters a Refresh cycle. All banks of the SDRAM
must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh
Command can be applied. The refresh addressing is generated by the internal refresh controller. This
makes the address bits “Don't Care” during a Refresh command. An internal address counter supplies
the addresses during the refresh cycle. No control of the external address bus is required once this
cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the
precharged (idle) state. A delay between the Refresh Command and the next valid command, except
NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as shown in
Figure 55. Note that the tRFC timing parameter depends on memory density.
In general, a Refresh command needs to be issued to the DDR3 SDRAM regularly every tREFI interval.
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of 8 Refresh commands can be postponed during
operation of the DDR3 SDRAM, meaning that at no point in time more than a total of 8 Refresh
commands are allowed to be postponed. In case that 8 Refresh commands are postponed in a row,
the resulting maximum interval between the surrounding Refresh commands is limited to 9 × tREFI
(see Figure 56). A maximum of 8 additional Refresh commands can be issued in advance (“pulled in”),
with each one reducing the number of regular Refresh commands required later by one. Note that
pulling in more than 8 Refresh commands in advance does not further reduce the number of regular
Refresh commands required later, so that the resulting maximum interval between two surrounding
Refresh commands is limited to 9 × tREFI (see Figure 57). At any given time, a maximum of 16 REF
commands can be issued within 2 x tREFI. Self-Refresh Mode may be entered with a maximum of
eight Refresh commands being postponed. After exiting Self-Refresh Mode with one or more Refresh
commands postponed, additional Refresh commands may be postponed to the extent that the total
number of postponed Refresh commands (before and after the Self-Refresh) will never exceed eight.
During Self-Refresh Mode, the number of postponed or pulled-in REF commands does not change.
T0
T1
REF
NOP
Ta0
Ta1
REF
NOP
Tb0
Tb1
Tb2
Tb3
VALID
NOP
VALID
VALID
VALID
Tc0
Tc1
Tc2
Tc3
REF
VALID
VALID
VALID
CK#
CK
Command
NOP
tRFC
NOP
VALID
tRFC(min)
tREFI (max. 9 x tREFI)
DRAM must be idle
DRAM must be idle
NOTES: 1. Only NOP/DES commands allowed after Refresh command registered until tRFC(min) expires.
2. Time interval between two Refresh commands may be extended to a maximum of 9 x tREFI.
TIME BREAK
DON'T CARE
Figure 55 – Refresh Command Timing
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tREFI
9 x tREFI
t
tRFC
8 REF-Commands pulled-in
Figure 56 – Postponing Refresh Commands (Example)
tREFI
9 x tREFI
t
tRFC
8 REF-Commands pulled-in
Figure 57 – Pulling-in Refresh Commands (Example)
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8.16 Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3 SDRAM, even if the rest of the
system is powered down. When in the Self-Refresh mode, the DDR3 SDRAM retains data without
external clocking. The DDR3 SDRAM device has a built-in timer to accommodate Self-Refresh
operation. The Self-Refresh-Entry (SRE) Command is defined by having CS#, RAS#, CAS#, and CKE
held low with WE# high at the rising edge of the clock.
Before issuing the Self-Refresh-Entry command, the DDR3 SDRAM must be idle with all bank
precharge state with tRP satisfied. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc.
satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are
satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) Also, on-die termination must be turned off
before issuing Self-Refresh-Entry command, by either registering ODT pin low “ODTL + 0.5tCK” prior
to the Self-Refresh Entry command or using MRS to MR1 command. Once the Self-Refresh Entry
command is registered, CKE must be held low to keep the device in Self-Refresh mode. During
normal operation (DLL on), MR1 (A0 = 0), the DLL is automatically disabled upon entering SelfRefresh and is automatically enabled (including a DLL-Reset) upon exiting Self-Refresh.
When the DDR3 SDRAM has entered Self-Refresh mode, all of the external control signals, except
CKE and RESET#, are “don't care.” For proper Self-Refresh operation, all power supply and reference
pins (VDD, VDDQ, VSS, VSSQ, VREFCA and VREFDQ) must be at valid levels. VREFDQ supply may be
turned OFF and VREFDQ may take any value between VSS and VDD during Self Refresh operation,
provided that VREFDQ is valid and stable prior to CKE going back High and that first Write operation or
first Write Leveling Activity may not occur earlier than 512 nCK after exit from Self Refresh. The
DRAM initiates a minimum of one Refresh command internally within tCKE period once it enters SelfRefresh mode.
The clock is internally disabled during Self-Refresh Operation to save power. The minimum time that
the DDR3 SDRAM must remain in Self-Refresh mode is tCKESR. The user may change the external
clock frequency or halt the external clock tCKSRE after Self-Refresh entry is registered, however, the
clock must be restarted and stable tCKSRX before the device can exit Self-Refresh operation.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable
prior to CKE going back HIGH. Once a Self-Refresh Exit command (SRX, combination of CKE going
high and either NOP or Deselect on command bus) is registered, a delay of at least tXS must be
satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for
any internal refresh in progress. Before a command that requires a locked DLL can be applied, a delay
of at least tXSDLL must be satisfied.
Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration
commands may be required to compensate for the voltage and temperature drift as described in
section 8.18 “ZQ Calibration Commands” on page 77. To issue ZQ calibration commands,
applicable timing requirements must be satisfied (See Figure 72 - “ZQ Calibration Timing” on page
78).
CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for
Self-Refresh re-entry. Upon exit from Self-Refresh, the DDR3 SDRAM can be put back into SelfRefresh mode after waiting at least tXS period and issuing one refresh command (refresh period of
tRFC). NOP or deselect commands must be registered on each positive clock edge during the SelfRefresh exit interval tXS. ODT must be turned off during tXSDLL.
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The use of Self-Refresh mode introduces the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3
SDRAM requires a minimum of one extra refresh command before it is put back into Self-Refresh
Mode.
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Td0
Te0
Tf0
VALID
VALID
CK#
CK
tIS
tCKSRX
tCKSRE
tCPDED
CKE
tCKESR
tIS
ODT
VALID
ODTL
Command
NOP
SRE
NOP
SRX
NOP*1
Address
tRP
VALID*2
VALID*3
VALID
VALID
tXS
tXSDLL
Enter Self Refresh
Exit Self Refresh
TIME BREAK
DON'T CARE
Notes:
1. Only NOP or DES command.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
Figure 58 – Self-Refresh Entry/Exit Timing
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8.17 Power-Down Modes
8.17.1 Power-Down Entry and Exit
Power-down is synchronously entered when CKE is registered low (along with NOP or Deselect
command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL
operations, DLL locking or read / write operation are in progress. CKE is allowed to go low while any
of other operations such as row activation, precharge or auto-precharge and refresh are in progress,
but power-down IDD spec will not be applied until finishing those operations. Timing diagrams are
shown in Figure 59 through Figure 71 with details for entry and exit of Power-Down.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode
for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC
timing and voltage specification as well as proper DLL operation with any CKE intensive operations as
long as DRAM controller complies with DRAM specifications.
During Power-Down, if all banks are closed after any in-progress commands are completed, the
device will be in precharge Power-Down mode; if any bank is open after in-progress commands are
completed, the device will be in active Power-Down mode.
Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT, CKE and
RESET#. To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or
Deselect commands are needed during the CKE switch off and cycle(s) after, this timing period are
defined as tCPDED. CKE_low will result in deactivation of command and address receivers after tCPDED
has expired.
Table 8 – Power-Down Entry Definitions
Status of DRAM
MRS bit A12
DLL
PD Exit
Relevant Parameters
Active
(A bank or more Open)
Don't Care
On
Fast
tXP to any valid command
Precharged
(All banks Precharged)
0
Off
Slow
tXP to any valid command. Since it is in precharge state,
commands here will be ACT, REF, MRS, PRE or PREA.
tXPDLL to commands that need the DLL to operate, such
as RD, RDA or ODT control line.
Precharged
(All banks Precharged)
1
On
Fast
tXP to any valid command
Also, the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept
enabled during precharge power-down (Fast Exit Mode) or active power-down. In power-down mode,
CKE low, RESET# high, and a stable clock signal must be maintained at the inputs of the DDR3
SDRAM, and ODT should be in a valid state, but all other input signals are “Don't Care.” (If RESET#
goes low during Power-Down, the DRAM will be out of PD mode and into reset state.) CKE low must
be maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the
device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or
Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable
command can be applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Powerdown exit latency is defined in section 10.16 “AC Characteristics” on page 138.
Active Power Down Entry and Exit timing diagram example is shown in Figure 59. Timing Diagrams
for CKE with PD Entry, PD Exit with Read and Read with Auto Precharge, Write, Write with Auto
Precharge, Activate, Precharge, Refresh, and MRS are shown in Figure 60 through Figure 68.
Additional clarifications are shown in Figure 69 through Figure 71.
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T0
T1
T2
VALID
NOP
NOP
Ta0
Ta1
Tb0
Tb1
Tc0
NOP
NOP
NOP
VALID
VALID
VALID
CK#
CK
Command
tPD
CKE
tIS
tIH
tIH
Address
tIS
tCKE
VALID
VALID
tCPDED
tXP
Enter
Power-Down
Mode
Exit
Power-Down
Mode
TIME BREAK
DON'T CARE
Note:
1. VALID command at T0 is ACT, NOP, DES or PRE with still one bank remaining open after completion of the precharge
command.
Figure 59 – Active Power-Down Entry and Exit Timing Diagram
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
RD or
RDA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Ta8
Tb0
Tb1
NOP
NOP
VALID
CK#
CK
Command
tCPDED
tIS
CKE
Address
VALID
VALID
VALID
RL = AL + CL
tPD
DQS, DQS#
DQ BL8
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
DQ BC4
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
tRDPDEN
Power-Down
Entery
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 60 – Power-Down Entry after Read and Read with Auto Precharge
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T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tb1
Tb2
Tc0
Tc1
NOP
NOP
VALID
CK#
CK
Command
NOP
tCPDED
tIS
CKE
Address
VALID
Bank
Col n
VALID
A10
tPD
WR*1
WL = AL + CWL
DQS, DQS#
DQ BL8
Din
b
Din
b+1
Din
b+2
Din
b+3
DQ BC4
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Start Internal
Precharge
tWRAPDEN
Power-Down
Entery
TRANSITIONING DATA
TIME BREAK
DON'T CARE
Note:
1. tWR is programmed through MR0.
Figure 61 – Power-Down Entry after Write with Auto Precharge
T0
T1
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Ta7
Tb0
Tb1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Tb2
Tc0
Tc1
NOP
NOP
VALID
CK#
CK
Command
tCPDED
tIS
CKE
Address
VALID
Bank
Col n
VALID
A10
WL = AL + CWL
tPD
tWR
DQS, DQS#
DQ BL8
Din
b
Din
b+1
Din
b+2
Din
b+3
DQ BC4
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
tWRPDEN
Power-Down
Entery
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 62 – Power-Down Entry after Write
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T0
T1
T2
VALID
NOP
NOP
Ta0
Ta1
Tb0
Tb1
Tc0
NOP
NOP
NOP
VALID
VALID
VALID
CK#
CK
Command
tCPDED
tCKE
tIH
tIS
CKE
tXP
tIS
tPD
Enter
Power-Down
Mode
Exit
Power-Down
Mode
DON'T CARE
TIME BREAK
Figure 63 – Precharge Power-Down (Fast Exit Mode) Entry and Exit
T0
T1
T2
VALID
NOP
NOP
Ta0
Ta1
Tb0
Tb1
Tc0
Td0
NOP
NOP
NOP
VALID
VALID
VALID
VALID
VALID
CK#
CK
Command
tCKE
tCPDED
CKE
tIS
tIH
tIS
tXP
tPD
tXPDLL
Enter
Power-Down
Mode
Exit
Power-Down
Mode
TIME BREAK
DON'T CARE
Figure 64 – Precharge Power-Down (Slow Exit Mode) Entry and Exit
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T0
T1
T2
T3
Ta0
Ta1
Command
VALID
REF
NOP
NOP
NOP
VALID
Address
VALID
VALID
CK#
CK
VALID
tCPDED
tIS
tPD
CKE
VALID
tREFPDEN
TIME BREAK
DON'T CARE
Figure 65 – Refresh Command to Power-Down Entry
T0
T1
T2
T3
Ta0
Ta1
Command
VALID
ACTIVE
NOP
NOP
NOP
VALID
Address
VALID
VALID
CK#
CK
VALID
tCPDED
tIS
tPD
CKE
VALID
tACTPDEN
TIME BREAK
DON'T CARE
Figure 66 – Active Command to Power-Down Entry
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T0
T1
T2
T3
Ta0
Ta1
Command
VALID
PRE or
PREA
NOP
NOP
NOP
VALID
Address
VALID
VALID
CK#
CK
VALID
tCPDED
tIS
tPD
CKE
VALID
tPREPDEN
TIME BREAK
DON'T CARE
Figure 67 – Precharge / Precharge all Command to Power-Down Entry
T0
T1
MRS
NOP
Ta0
Ta1
Tb0
Tb1
CK#
CK
Command
Address
NOP
NOP
VALID
VALID
VALID
tCPDED
tIS
tPD
CKE
VALID
tMRSPDEN
TIME BREAK
DON'T CARE
Figure 68 – MRS Command to Power-Down Entry
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8.17.2 Power-Down clarifications - Case 1
When CKE is registered low for power-down entry, tPD(min) must be satisfied before CKE can be
registered high for power-down exit. The minimum value of parameter tPD(min) is equal to the
minimum value of parameter tCKE(min) as shown in section 10.16 “AC Characteristics” on page 138.
A detailed example of Case 1 is shown in Figure 69.
T0
T1
T2
VALID
NOP
NOP
Ta0
Ta1
Tb0
Tb1
Tb2
NOP
NOP
NOP
VALID
CK#
CK
Command
tPD
CKE
tIS
tIH
tIH
Address
tIS
tIS
tCKE
VALID
tCPDED
tCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Enter
Power-Down
Mode
DON'T CARE
TIME BREAK
Figure 69 – Power-Down Entry/Exit Clarifications - Case 1
8.17.3 Power-Down clarifications - Case 2
For certain CKE intensive operations, for example, repeated ‘PD Exit - Refresh - PD Entry’ sequences,
the number of clock cycles between PD Exit and PD Entry may be insufficient to keep the DLL
updated. Therefore, the following conditions must be met in addition to tCKE in order to maintain
proper DRAM operation when the Refresh command is issued between PD Exit and PD Entry. Powerdown mode can be used in conjunction with the Refresh command if the following conditions are met:
1) tXP must be satisfied before issuing the command.
2) tXPDLL must be satisfied (referenced to the registration of PD Exit) before the next power-down can
be entered. A detailed example of Case 2 is shown in Figure 70.
T0
T1
T2
VALID
NOP
NOP
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
NOP
NOP
NOP
REF
NOP
NOP
CK#
CK
Command
tIS
CKE
tPD
tIS
tIH
Address
tIH
tCKE
VALID
tXP
tXPDLL
tCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Enter
Power-Down
Mode
TIME BREAK
DON'T CARE
Figure 70 – Power-Down Entry/Exit Clarifications - Case 2
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8.17.4 Power-Down clarifications - Case 3
If an early PD Entry is issued after a Refresh command, once PD Exit is issued, NOP or DES with
CKE High must be issued until tRFC(min) from the Refresh command is satisfied. This means CKE can
not be registered low twice within a tRFC(min) window. A detailed example of Case 3 is shown in
Figure 71.
T0
T1
T2
REF
NOP
NOP
Ta0
Ta1
Tb0
Tb1
Tc0
Tc1
Td0
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
tIS
CKE
tPD
tIH
tIS
tIH
tCKE
Address
tXP
tRFC(min)
tCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Enter
Power-Down
Mode
TIME BREAK
DON'T CARE
Figure 71 – Power-Down Entry/Exit Clarifications - Case 3
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8.18 ZQ Calibration Commands
8.18.1 ZQ Calibration Description
ZQ Calibration command is used to calibrate DRAM RON & ODT values over PVT (process, voltage
and temperature). An external resistor (RZQ) between the DRAM ZQ pin and ground is used as a
calibration reference. DDR3 SDRAM needs longer time to calibrate output driver and on-die
termination circuits after power-up and/or any reset, medium time for a full calibration during normal
operation (e.g. after self-refresh exit) and relatively smaller time to perform periodic update calibrations.
ZQCL (ZQ Calibration Long) command is used to perform the initial calibration during power-up
initialization sequence. This command may be issued at any time by the controller depending on the
system environment. ZQCL command triggers the calibration engine inside the DRAM and, once
calibration is achieved, the calibrated values are transferred from the calibration engine to DRAM IO,
which gets reflected as updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full
calibration and the transfer of values. All other ZQCL commands except the first ZQCL command
issued after RESET are allowed a timing period of tZQoper.
ZQCS (ZQ Calibration Short) command is used to perform periodic calibrations to account for voltage
and temperature variations. A shorter timing window is provided to perform the calibration and transfer
of values as defined by timing parameter tZQCS. One ZQCS command can effectively correct a
minimum of 0.5 % (ZQ Correction) of RON and RTT impedance error within 64 nCK for all speed bins
assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature
Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval
between ZQCS commands can be determined from these tables and other application-specific
parameters. One method for calculating the interval between ZQCS commands, given the temperature
(Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is
illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens × Tdriftrate) + (VSens × Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM
temperature and voltage sensitivities.
For example, if TSens = 1.5 %/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15 mV/sec,
then the interval between ZQCS commands is calculated as:
0.5
= 0.133 ≈ 128mS
(1.5 × 1) + (0.15 × 15)
No other activities should be performed on the DRAM channel by the controller for the duration of
tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows accurate calibration of output
driver and on-die termination values. Once DRAM calibration is achieved, the DRAM should disable
ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the
controller. See section 9.1 “Command Truth Table” on Page 94 for a description of the ZQCL and
ZQCS commands.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self
refresh. Upon Self-Refresh exit, DDR3 SDRAM will not perform an IO calibration without an explicit
ZQ calibration command. The earliest possible time for ZQ Calibration command (ZQCS or ZQCL)
after self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of
tZQoper, tZQinit, or tZQCS between the devices.
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8.18.2 ZQ Calibration Timing
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
ZQCL
NOP
NOP
NOP
VALID
VALID
ZQCS
NOP
NOP
NOP
VALID
Address
VALID
VALID
VALID
A10
VALID
VALID
VALID
CK#
CK
Command
CKE
*1
VALID
VALID
*1
VALID
ODT
*2
VALID
VALID
*2
VALID
DQ Bus
*3
ACTIVITIES
*3
Hi-Z
Hi-Z
ACTIVITIES
tZQCS
tZQinit or tZQoper
TIME BREAK
DON'T CARE
Notes:
1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.
Figure 72 – ZQ Calibration Timing
8.18.3 ZQ External Resistor Value, Tolerance, and Capacitive loading
In order to use the ZQ Calibration function, a 240 ohm ± 1% tolerance external resistor must be
connected between the ZQ pin and ground. The single resistor can be used for each SDRAM or one
resistor can be shared between two SDRAMs if the ZQ calibration timings for each SDRAM do not
overlap. The total capacitive loading on the ZQ pin must be limited (See section 10.11 “Input/Output
Capacitance” on page 120).
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8.19 On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off
termination resistance for each DQ, DQS, DQS# and DM (and TDQS, TDQS#, when enabled via
A11=1 in MR1) signal via the ODT control pin. The ODT feature is designed to improve signal integrity
of the memory channel by allowing the DRAM controller to independently turn on/off termination
resistance for any or all DRAM devices. More details about ODT control modes and ODT timing
modes can be found further down in this document:
The ODT control modes are described in section 8.19.1
The ODT synchronous mode is described in section 8.19.2
The dynamic ODT feature is described in section 8.19.3
The ODT asynchronous mode is described in section 8.19.4
The transitions between ODT synchronous and asynchronous are described in section 8.19.4.1
through section 8.19.4.4
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown in Figure 73.
ODT
To other
circuitry
like
RCV,…
VDDQ / 2
RTT
Swtich
DQ, DQS, DM, TDQS
Figure 73 – Functional Representation of ODT
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other
control information, see below. The value of RTT is determined by the settings of Mode Register bits
(see Figure 6 - MR1 Definition on page 19 and Figure 7 - MR2 Definition on page 22). The ODT pin
will be ignored if the Mode Registers MR1 and MR2 are programmed to disable ODT, and in selfrefresh mode.
8.19.1 ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if any of MR1 {A9, A6, A2} or MR2 {A10, A9} are non zero. In this case, the
value of RTT is determined by the settings of those bits (see Figure 6 - MR1 Definition on page 19).
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (unless ODT is disabled by MR).
DRAM does not use any write or read command decode information.
The Termination Truth Table is shown in Table 9.
Table 9 – Termination Truth Table
ODT pin
DRAM Termination State
0
OFF
1
ON, (OFF, if disabled by MR1 {A9, A6, A2} and MR2 {A10, A9} in general)
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8.19.2 Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the powerdown definition, these modes are:
Any bank active with CKE high
Refresh with CKE high
Idle mode with CKE high
Active power down mode (regardless of MR0 bit A12)
Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must
be disabled by continuously registering the ODT pin low and/or by programming the Rtt_Nom bits
MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by
a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock
edge. The ODT latency is tied to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL - 2.
8.19.2.1 ODT Latency and Posted ODT
In Synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also
applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles
defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2;
ODTLoff = CWL + AL - 2. For more details refer to the ODT timing parameters in section 10.16 “AC
Characteristics” on page 138.
Table 10 – ODT Latency
Symbol
Parameter
DDR3-1333, DDR3-1600 & DDR3-1866
ODTLon
ODT turn on Latency
WL - 2 = CWL + AL - 2
ODTLoff
ODT turn off Latency
WL - 2 = CWL + AL - 2
Unit
nCK
8.19.2.2 Timing Parameters
In synchronous ODT mode, the following timing parameters apply (see also Figures 74):
ODTLon, ODTLoff, tAON,min,max, tAOF,min,max.
Minimum RTT turn-on time (tAONmin) is the point in time when the device leaves high impedance and
ODT resistance begins to turn on. Maximum RTT turn on time (tAONmax) is the point in time when the
ODT resistance is fully on. Both are measured from ODTLon.
Minimum RTT turn-off time (tAOFmin) is the point in time when the device starts to turn off the ODT
resistance. Maximum RTT turn off time (tAOFmax) is the point in time when the on-die termination has
reached high impedance. Both are measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered
by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL = 4) or ODTH8 (BL = 8)
after the Write command (see Figure 75). ODTH4 and ODTH8 are measured from ODT registered
high to ODT registered low or from the registration of a Write command until ODT is registered low.
ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL =
4) or ODTH8 (BL = 8) after Write command (T7). ODTH is measured from ODT first registered high to
ODT first registered low, or from registration of Write command with ODT high to ODT registered low.
Note that although ODTH4 is satisfied from ODT registered high at T6, ODT must not go low before
T11 as ODTH4 must also be satisfied from the registration of the Write command at T7.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
CKE
AL = 3
AL = 3
CWL - 2
ODT
ODTH4min
ODTLoff = CWL + AL - 2
ODTLon = CWL + AL - 2
tAOFmin
tAONmin
DRAM_RTT
Rtt_Nom
tAONmax
tAOFmax
DON'T CARE
TRANSITIONING
Figure 74 – Synchronous ODT Timing (AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
NOP
NOP
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
CKE
Command
ODTH4min
ODTH4
ODTH4
ODT
ODTLoff = WL - 2
ODTLoff = WL - 2
ODTLon = WL - 2
ODTLon = WL - 2
tAONmin
tAOFmin
tAONmax
tAOFmin
DRAM_RTT
Rtt_Nom
tAONmax
tAONmin
tAOFmax
tAOFmax
TRANSITIONING
DON'T CARE
Figure 75 – Synchronous ODT (BL = 4, WL = 7)
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8.19.2.3 ODT during Reads
As the DDR3 SDRAM can not terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving
the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble as shown in the example below. As shown in Figure 76 below, at
cycle T15, DRAM turns on the termination when it stops driving, which is determined by tHZ. If DRAM stops driving early (i.e., tHZ is early), then tAONmin
timing may apply. If DRAM stops driving late (i.e., tHZ is late), then DRAM complies with tAONmax timing. Note that ODT may be disabled earlier before the
Read and enabled later after the Read than shown in this example in Figure 76.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
VALID
CK#
CK
ODTLon = CWL + AL - 2
ODTTLoff = CWL + AL - 2
ODT
tAOFmin
RTT
Rtt_Nom
Rtt_Nom
tAONmax
tAOFmax
RL = AL + CL
DQS, DQS#
Dout
b
DQ
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
TRANSITIONING
DON'T CARE
Figure 76 – ODT must be disabled externally during Reads by driving ODT low.
(CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8)
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8.19.3 Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that
the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command.
This requirement is supported by the “Dynamic ODT” feature as described as follows:
8.19.3.1 Functional Description:
The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’. The function is described
as follows:
Two RTT values are available: Rtt_Nom and Rtt_WR.
− The value for Rtt_Nom is preselected via bits A[9,6,2] in MR1.
− The value for Rtt_WR is preselected via bits A[10,9] in MR2.
During operation without write commands, the termination is controlled as follows:
− Nominal termination strength Rtt_Nom is selected.
− Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
When a write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if
Dynamic ODT is enabled, the termination is controlled as follows:
− A latency ODTLcnw after the write command, termination strength Rtt_WR is selected.
− A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by
MRS or selected OTF) after the write command, termination strength Rtt_Nom is selected.
− Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
Table 11 shows latencies and timing parameters which are relevant for the on-die termination control
in Dynamic ODT mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set
Rtt_WR, MR2{A10, A9}={0,0}, to disable Dynamic ODT externally.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered
by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL = 4) or ODTH8 (BL = 8)
after the Write command (see Figure 77). ODTH4 and ODTH8 are measured from ODT registered
high to ODT registered low or from the registration of a Write command until ODT is registered low.
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Table 11 – Latencies and timing parameters relevant for Dynamic ODT
Name and Description
Abbr.
Defined from
Defined to
Definition for all DDR3
speed bins
Unit
ODT turn-on Latency
ODTLon
Registering external
ODT signal high
Turning termination on
ODTLon = WL - 2
tCK
ODT turn-off Latency
ODTLoff
Registering external
ODT signal low
Turning termination off
ODTLoff = WL - 2
tCK
ODT Latency for changing
from Rtt_Nom to Rtt_WR
ODTLcnw
Registering external
write command
Change RTT strength from
Rtt_Nom to Rtt_WR
ODTLcnw = WL - 2
tCK
ODT Latency for change from
Rtt_WR to Rtt_Nom (BL = 4)
ODTLcwn4
Registering external
write command
Change RTT strength from
Rtt_WR to Rtt_Nom
ODTLcwn4 = 4 + ODTLoff
tCK
ODT Latency for change from
Rtt_WR to Rtt_Nom (BL = 8)
ODTLcwn8
Registering external
write command
Change RTT strength from
Rtt_WR to Rtt_Nom
ODTLcwn8 = 6 + ODTLoff
tCK(avg)
Minimum ODT high time after
ODT assertion
ODTH4
Registering ODT
high
ODT registered low
ODTH4 = 4
tCK(avg)
Minimum ODT high time after
Write (BL = 4)
ODTH4
Registering Write
with ODT high
ODT registered low
ODTH4 = 4
tCK(avg)
Minimum ODT high time after
Write (BL =8)
ODTH8
Registering Write
with ODT high
ODT registered low
ODTH4 = 6
tCK(avg)
RTT change skew
tADC
ODTLcnw
ODTLcwn
RTT valid
tADC(min) = 0.3 * tCK(avg)
tADC(max) = 0.7 * tCK(avg)
tCK(avg)
Note: tAOFnom and tADCnom are 0.5 tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw and ODTLcwn)
8.19.3.2 ODT Timing Diagrams
The following pages provide exemplary timing diagrams as described in Table 12:
Table 12 – Timing Diagrams for “Dynamic ODT”
Figure and Page
Description
Figure 77 on page 85
Figure 77, Dynamic ODT: Behavior with ODT being asserted before and after the write
Figure 78 on page 86
Figure 78, Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
Figure 79 on page 86
Figure 79, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 6 clock cycles
Figure 80 on page 87
Figure 80, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5
Figure 81 on page 87
Figure 81, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 4 clock cycles
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T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
WRS4
NOP
NOP
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Address
NOP
VALID
ODTH4
ODTLoff
ODTH4
ODT
ODTLon
ODTLcwn4
tADCmin
tADCmin
tAONmin
RTT
Rtt_Nom
tAONmax
Rtt_WR
ODTLcnw
tAOFmin
Rtt_Nom
tADCmax
tADCmax
tAOFmax
DQS, DQS#
Din
b
DQ
WL
NOTES:
Din
b+1
Din
b+2
Din
b+3
TRANSITIONING
Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the Write command.
In this example, ODTH4 would be satisfied if ODT went low at T8 (4 clocks after the Write command).
DON'T CARE
Figure 77 – Dynamic ODT: Behavior with ODT being asserted before and after the write
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CK#
CK
Command
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
Address
ODTH4
ODTLon
ODTLoff
ODT
tAOFmin
tAONmin
Rtt_Nom
RTT
tAONmax
tAOFmax
DQS, DQS#
DQ
DON'T CARE
TRANSITIONING
Notes:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
Figure 78 – Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
CK#
CK
Command
Address
T0
T1
T2
WRS8
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLcnw
NOP
VALID
ODTH8
ODTLoff
ODTLon
ODT
tAONmin
tAOFmin
Rtt_WR
RTT
ODTLcwn8
tADCmax
tAOFmax
DQS, DQS#
WL
Din
b
DQ
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
TRANSITIONING
DON'T CARE
Note:
1. Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH8 = 6 is exactly satisfied.
Figure 79 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles
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CK#
CK
Command
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLcnw
NOP
Address
WRS4
NOP
VALID
ODTH4
ODTLoff
ODT
ODTLon
tAOFmin
tADCmin
tAONmin
Rtt_Nom
Rtt_WR
RTT
tADCmax
ODTLcwn4
tAOFmax
tADCmax
DQS, DQS#
WL
Din
b
DQ
Din
b+1
Din
b+2
Din
b+3
TRANSITIONING
DON'T CARE
Notes:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
Figure 80 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5
CK#
CK
Command
Address
T0
T1
T2
NOP
WRS4
NOP
T3
T4
T5
T6
T7
T8
T9
T10
T11
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLcnw
VALID
ODTH4
ODTLoff
ODT
ODTLon
tAOFmin
tAONmin
Rtt_WR
RTT
tADCmax
ODTLcwn4
tAOFmax
DQS, DQS#
WL
Din
b
DQ
Din
b+1
Din
b+2
Din
b+3
TRANSITIONING
DON'T CARE
Note:
1. Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH4 = 4 is exactly satisfied.
Figure 81 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 4 clock cycles
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8.19.4 Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit
A12). Based on the power down mode definitions, this is currently Precharge power down mode if DLL is disabled during precharge power down by MR0
bit A12.
In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the external ODT command.
In asynchronous ODT mode, the following timing parameters apply (see Figure 82): tAONPD,min,max, tAOFPD,min,max.
Minimum RTT turn-on time (tAONPDmin) is the point in time when the device termination circuit leaves high impedance state and ODT resistance begins to
turn on. Maximum RTT turn on time (tAONPDmax) is the point in time when the ODT resistance is fully on.
tAONPDmin and tAONPDmax are measured from ODT being sampled high.
Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT resistance. Maximum ODT turn
off time (tAOFPDmax) is the point in time when the on-die termination has reached high impedance. tAOFPDmin and tAOFPDmax are measured from ODT
being sampled low.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
CKE
tIH
tIH
tIS
tIS
ODT
tAOFPDmin
tAONPDmin
RTT
RTT
tAONPDmax
tAOFPDmax
DON'T CARE
TRANSITIONING
Figure 82 – Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition: AL is ignored
In Precharge Power Down, ODT receiver remains active, however no Read or Write command can be issued, as the respective ADD/CMD receivers may
be disabled.
Table 13 – Asynchronous ODT Timing Parameters for all Speed Bins
Symbol
Description
Min.
Max.
Unit
tAONPD
Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
2
8.5
nS
tAOFPD
Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
2
8.5
nS
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8.19.4.1 Synchronous to Asynchronous ODT Mode Transitions
Table 14 – ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period
Description
Min.
Max.
ODT to RTT turnon delay
min{ ODTLon * tCK(avg) + tAONmin; tAONPDmin }
max{ ODTLon * tCK(avg) + tAONmax; tAONPDmax }
min{ (WL - 2) * tCK(avg) + tAONmin; tAONPDmin }
max{ (WL - 2) * tCK(avg) + tAONmax; tAONPDmax }
ODT to RTT turnoff delay
min{ ODTLoff * tCK(avg) +tAOFmin; tAOFPDmin }
max{ ODTLoff * tCK(avg) + tAOFmax; tAOFPDmax }
min{ (WL - 2) * tCK(avg) +tAOFmin; tAOFPDmin }
tANPD
max{ (WL - 2) * tCK(avg) + tAOFmax; tAOFPDmax }
WL -1
8.19.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”,
there is a transition period around power down entry, where the DDR3 SDRAM may show either
synchronous or asynchronous ODT behavior.
The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL -1)
and is counted backwards in time from the clock cycle where CKE is first registered low. tCPDED(min)
starts with the clock cycle where CKE is first registered low. The transition period begins with the
starting point of tANPD and terminates at the end point of tCPDED(min), as shown in Figure 83. If there
is a Refresh command in progress while CKE goes low, then the transition period ends at the later one
of tRFC(min) after the Refresh command and the end point of tCPDED(min), as shown in Figure 84.
Please note that the actual starting point at tANPD is excluded from the transition period, and the actual
end points at tCPDED(min) and tRFC(min), respectively, are included in the transition period.
ODT assertion during the transition period may result in an RTT change as early as the smaller of
tAONPDmin and (ODTLon*tCK(avg) + tAONmin) and as late as the larger of tAONPDmax and (ODTLon*
tCK(avg) + tAONmax). ODT de-assertion during the transition period may result in an RTT change as
early as the smaller of tAOFPDmin and (ODTLoff* tCK(avg) + tAOFmin) and as late as the larger of
tAOFPDmax and (ODTLoff* tCK(avg) + tAOFmax). See Table 14.
Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. Figure 83
shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state
change during the transition period; ODT_C shows a state change after the transition period.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T9
T10
T11
NOP
NOP
T12
CK#
CK
CKE
Command
tCPDED
tCPDEDmin
tANPD
PD entry transition period
Last sync, ODT
tAOFmin
RTT
RTT
ODTLoff
tAOFmax
tAOFPDmax
ODTLoff + tAOFmin
Sync or async, ODT
tAOFPDmin
RTT
RTT
ODTLoff + tAOFmax
First async, ODT
tAOFPDmin
RTT
RTT
PD entry transition period
tAOFPDmax
TRANSITIONING DATA
DON'T CARE
Figure 83 – Synchronous to asynchronous transition during Precharge Power Down
(with DLL frozen) entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4)
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T0
T1
T2
T3
T4
T5
T6
T7
T8
NOP
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T9
T10
T11
T12
T13
Ta0
Ta1
Ta2
Ta3
CK#
CK
CKE
Command
tRFC(min)
tANPD
tCPDEDmin
PD entry transition period
Last sync, ODT
tAOFmin
RTT
RTT
tAOFPDmax
ODTLoff
tAOFmax
ODTLoff + tAOFPDmin
Sync or async, ODT
tAOFPDmin
RTT
RTT
ODTLoff + tAOFPDmax
First async, ODT
tAOFPDmin
RTT
RTT
tAOFPDmax
TIME BREAK
TRANSITIONING
DON'T CARE
Figure 84 – Synchronous to asynchronous transition after Refresh command (AL = 0; CWL = 5; tANPD = WL - 1 = 4)
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8.19.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a transition period around power down
exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3 SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL - 1) and is
counted (backwards) from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODTLon*tCK(avg) + tAONmin) and as late
as the larger of tAONPDmax and (ODTLon*tCK(avg) + tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the
smaller of tAOFPDmin and (ODTLoff*tCK(avg) + tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK(avg) + tAOFmax). See Table 14.
Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. Figure 85 shows the three different cases: ODT_C,
asynchronous response before tANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the
transition period with synchronous response.
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
NOP
NOP
NOP
NOP
NOP
NOP
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Td0
Td1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
CKE
Command
tANPD
tXPDLL
PD exit transition period
Last sync, ODT
tAOFPDmin
RTT
RTT
ODTLoff + tAOFmin
tAOFPDmax
tAOFPDmax
Sync or async, ODT
tAOFPDmin
RTT
RTT
ODTLoff + tAOFmax
ODTLoff
tAOFmax
First async, ODT
tAOFmin
RTT
RTT
TIME BREAK
TRANSITIONING
DON'T CARE
Figure 85 – Asynchronous to synchronous transition during Precharge Power Down
(with DLL frozen) exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9)
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8.19.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap (see Figure 86). In
this case, the response of the DDR3 SDRAMs RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD
entry transition period to the end of the PD exit transition period (even if the entry period ends later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case the response of the DDR3 SDRAMs RTT
to a change in ODT state at the input may be synchronous OR asynchronous from the start of the PD exit transition period to the end of the PD entry
transition period. Note that in the bottom part of Figure 86 it is assumed that there was no Refresh command in progress when Idle state was entered.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
CKE
tANPD
tRFC(min)
PD entry transition period
PD exit transition period
tANPD
tXPDLL
short CKE low transition period
CKE
tANPD
short CKE high transition period
tXPDLL
TIME BREAK
TRANSITIONING
DON'T CARE
Figure 86 – Transition period for short CKE cycles, entry and exit period overlapping (AL = 0, WL = 5, tANPD = WL - 1 = 4)
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9. OPERATION MODE
9.1 Command Truth Table
Notes 1, 2, 3 and 4 apply to the entire Command Truth Table.
Note 5 Applies to all Read/Write commands.
[BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don't Care, V=Valid]
Table 15 – Command Truth Table
CKE
A12/
BC#
V
V
V
V
V
Mode Register Set
MRS
H
H
L
L
L
L
BA
Refresh
REF
H
H
L
L
L
H
Self Refresh Entry
SRE
H
L
A10/
AP
A0A9,
A11
A13A14
Abbr.
Self Refresh Exit
Previous Current CS# RAS# CAS# WE#
Cycle
Cycle
BA0BA2
COMMAND
NOTES
OP Code
L
L
L
H
V
V
V
V
V
H
X
X
X
X
X
X
X
X
L
H
H
H
V
V
V
V
V
7,9,12
SRX
L
H
7,8,9,12
Single Bank Precharge
PRE
H
H
L
L
H
L
BA
V
V
L
V
Precharge all Banks
PREA
H
H
L
L
H
L
V
V
V
H
V
Bank Activate
ACT
H
H
L
L
H
H
BA
Write (Fixed BL8 or BC4)
WR
H
H
L
H
L
L
BA
RFU
V
L
CA
5
Write (BC4, on the Fly)
WRS4
H
H
L
H
L
L
BA
RFU
L
L
CA
5
Row Address (RA)
Write (BL8, on the Fly)
WRS8
H
H
L
H
L
L
BA
RFU
H
L
CA
5
Write with Auto Precharge
(Fixed BL8 or BC4)
WRA
H
H
L
H
L
L
BA
RFU
V
H
CA
5
Write with Auto Precharge
(BC4, on the Fly)
WRAS4
H
H
L
H
L
L
BA
RFU
L
H
CA
5
Write with Auto Precharge
(BL8, on the Fly)
WRAS8
H
H
L
H
L
L
BA
RFU
H
H
CA
5
Read (Fixed BL8 or BC4)
RD
H
H
L
H
L
H
BA
RFU
V
L
CA
5
Read (BC4, on the Fly)
RDS4
H
H
L
H
L
H
BA
RFU
L
L
CA
5
Read (BL8, on the Fly)
RDS8
H
H
L
H
L
H
BA
RFU
H
L
CA
5
Read with Auto Precharge
(Fixed BL8 or BC4)
RDA
H
H
L
H
L
H
BA
RFU
V
H
CA
5
Read with Auto Precharge
(BC4, on the Fly)
RDAS4
H
H
L
H
L
H
BA
RFU
L
H
CA
5
Read with Auto Precharge
(BL8, on the Fly)
RDAS8
H
H
L
H
L
H
BA
RFU
H
H
CA
5
No Operation
NOP
H
H
L
H
H
H
V
V
V
V
V
10
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
X
11
Power Down Entry
PDE
H
L
Power Down Exit
PDX
L
H
ZQ Calibration Long
ZQCL
H
ZQ Calibration Short
ZQCS
H
L
H
H
H
V
V
V
V
V
H
X
X
X
X
X
X
X
X
L
H
H
H
V
V
V
V
V
H
X
X
X
X
X
X
X
X
H
L
H
H
L
X
X
X
H
X
H
L
H
H
L
X
X
X
L
X
6,12
6,12
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Notes:
1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.
The MSB of BA, RA and CA are device density and configuration dependant.
2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any
function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self Refresh Exit is asynchronous.
9. VREF (Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. VREFDQ supply may be turned OFF
and VREFDQ may take any value between VSS and VDD during Self Refresh operation, provided that VREFDQ is valid and
stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than
512 nCK after exit from Self Refresh.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose of the
No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between
operations. A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or
write cycle.
11. The Deselect command performs the same function as No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition.
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9.2
CKE Truth Table
Notes 1-7 apply to the entire CKE Truth Table.
For Power-down entry and exit parameters See 8.17 “Power-Down Modes” on page 69.
CKE low is allowed only if tMRD and tMOD are satisfied.
Table 16 – CKE Truth Table
CURRENT
STATE2
Power Down
Self Refresh
CKE
Previous Cycle 1
(N-1)
Current Cycle 1
(N)
COMMAND (N) 3
RAS#, CAS#, WE#, CS#
ACTION (N) 3
NOTES
L
L
X
Maintain Power Down
14,15
L
H
DESELECT or NOP
Power Down Exit
11,14
L
L
X
Maintain Self Refresh
15,16
L
H
DESELECT or NOP
Self Refresh Exit
8,12,16
Bank(s) Active
H
L
DESELECT or NOP
Active Power Down Entry
11,13,14
Reading
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Writing
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Precharging
H
L
DESELECT or NOP
Power Down Entry
11,13,14,17
Refreshing
H
L
DESELECT or NOP
Precharge Power Down Entry
11
H
L
DESELECT or NOP
Precharge Power Down Entry
11,13,14,18
H
L
REFRESH
Self Refresh
9,13,18
All Banks Idle
Any other state
Refer to section 9.1 “Command Truth Table” on page 94 for more detail with all command signals
10
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
2. Current state is defined as the state of the DDR3 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not
included here.
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. During any CKE transition (registration of CKE H->L or CKE L->H) the CKE level must be maintained until 1nCK prior to
tCKEmin being satisfied (at which time CKE may transition again).
7. DESELECT and NOP are defined in the Command Truth Table.
8. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period.
Read or ODT commands may be issued only after tXSDLL is satisfied.
9. Self Refresh mode can only be entered from the All Banks Idle state.
10. Must be a legal command as defined in the Command Truth Table.
11. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
12. Valid commands for Self Refresh Exit are NOP and DESELECT only.
13. Self Refresh can not be entered during Read or Write operations. For a detailed list of restrictions See section 8.16 “SelfRefresh Operation” on page 67 and See section 8.17 “Power-Down Modes” on page 69.
14. The Power Down does not perform any refresh operations.
15. “X” means “don't care” (including floating around VREF) in Self Refresh and Power Down. It also applies to Address pins.
16. VREF (Both VREFDQ and VREFCA) must be maintained during Self Refresh operation. VREFDQ supply may be turned OFF
and VREFDQ may take any value between VSS and VDD during Self Refresh operation, provided that VREFDQ is valid and
stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than
512 nCK after exit from Self Refresh.
17. If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power Down is entered,
otherwise Active Power Down is entered.
18. ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all
timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all Self Refresh
exit and Power Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).
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9.3
Simplified State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and
the commands to control them. In particular, situations involving more than one bank, the enabling or
disabling of on-die termination, and some other events are not captured in full detail.
CKE_ L
Power
Applied
Power
on
Reset
Procedure
MRS, MPR,
Write
Leveling
Initialization
Self
Refresh
SRE
ZQCL
MRS
From any state
RESET
SRX
ZQCL, ZQCS
REF
ZQ
Calibration
Idle
Refreshing
PDE
ACT
PDX
Active
Power
Down
Precharge
Power
Down
Activating
PDX
CKE_L
CKE_L
PDE
Bank
Active
Write
Read
Write A
Write
Writing
Read A
Read
Read
Reading
Write
Write A
Read A
Write A
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Reading
Precharging
Automatic sequence
Command sequence
Figure 87 – Simplified State Diagram
Table 17 – State Diagram Command Definitions
Abbreviation
Function
Abbreviation
Function
Abbreviation
Function
ACT
Active
Read
RD, RDS4, RDS8
PDE
Enter Power-down
PRE
Precharge
Read A
RDA, RDAS4, RDAS8
PDX
Exit Power-down
PREA
Precharge All
Write
WR, WRS4, WRS8
SRE
Self-Refresh entry
MRS
Mode Register Set
Write A
WRA, WRAS4, WRAS8
SRX
Self-Refresh exit
REF
Refresh
RESET
Start RESET Procedure
MPR
Multi-Purpose Register
ZQCL
ZQ Calibration Long
ZQCS
ZQ Calibration Short
-
-
NOTE: See “Command Truth Table” on page 94 for more details
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10. ELECTRICAL CHARACTERISTICS
10.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
NOTES
Voltage on VDD pin relative to VSS
VDD
-0.4 ~ 1.975
V
1, 3
Voltage on VDDQ pin relative to VSS
VDDQ
-0.4 ~ 1.975
V
1, 3
VIN, VOUT
-0.4 ~ 1.975
V
1
TSTG
-55 ~ 100
°C
1, 2
Voltage on any pin relative to VSS
Storage Temperature
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times. VREFDQ and VREFCA must not greater than 0.6 x VDDQ.
When VDD and VDDQ are less than 500 mV, VREFDQ and VREFCA may be equal to or less than 300 mV.
10.2 Operating Temperature Condition
PARAMETER
SYMBOL
Commercial Operating Temperature Range (for -11/-12/-15)
TOPER
Industrial Operating Temperature Range (for -12I/15I)
TOPER
RATING
UNIT
NOTES
0 ~ 85
°C
1, 2
0 ~95
°C
1, 2, 4
-40 ~ 85
°C
1, 3
-40 ~ 95
°C
1, 3, 4
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement
conditions, please refer to the JEDEC document JESD51-2.
2. During operation, the DRAM case temperature must be maintained between 0 to 95°C for Commercial parts under all
specification parameters.
3. During operation, the DRAM case temperature must be maintained between -40 to 95°C for Industrial parts under all
specification parameters
4. Some applications require operation of the 85°C < TCASE ≤ 95°C operating temperature. Full specifications are provided in
this range, but the following additional conditions apply:
(a) Refresh commands have to be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µS.
(b) If Self-Refresh operation is required in 85°C < TCASE ≤ 95°C operating temperature range, than it is mandatory to either
use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or
enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1b, MR2 A7 is don't care).
10.3 DC & AC Operating Conditions
10.3.1 Recommended DC Operating Conditions
SYM.
VDD
VDDQ
RZQ
PARAMETER
MIN.
TYP.
MAX.
UNIT
NOTES
Supply Voltage
1.425
1.5
1.575
V
1, 2
Supply Voltage for Output
1.425
1.5
1.575
V
1, 2
External Calibration Resistor connected
from ZQ ball to ground
237.6
240.0
242.4
Ω
3
Notes:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The external calibration resistor RZQ can be time-shared among DRAMs in special applications.
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10.4 Input and Output Leakage Currents
SYMBOL
IIL
IOL
PARAMETER
Input Leakage Current
(0V ≤ VIN ≤ VDD)
Output Leakage Current
(Output disabled, 0V ≤ VOUT ≤ VDDQ)
MIN.
MAX.
UNIT
NOTES
-2
2
µA
1
-5
5
µA
2
Notes:
1. All other balls not under test = 0 V.
2. All DQ, DQS and DQS# are in high-impedance mode.
10.5 Interface Test Conditions
Figure 88 represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of
the actual load presented by a production tester. System designers should use IBIS or other
simulation tools to correlate the timing reference load to a system environment. Manufacturers
correlate to their production test conditions, generally one or more coaxial transmission lines
terminated at the tester electronics.
VDDQ
CK, CK#
DUT
DQ
DQS
DQS#
VTT = VDDQ/2
25Ω
Timing reference point
Figure 88 – Reference Load for AC Timings and Output Slew Rates
The Timing Reference Points are the idealized input and output nodes / terminals on the outside of the
packaged SDRAM device as they would appear in a schematic or an IBIS model.
The output timing reference voltage level for single ended signals is the cross point with VTT.
The output timing reference voltage level for differential signals is the cross point of the true (e.g.
DQS) and the complement (e.g. DQS#) signal.
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10.6 DC and AC Input Measurement Levels
10.6.1 DC and AC Input Levels for Single-Ended Command and Address Signals
Table 18 – Single-Ended DC and AC Input Levels for Command and Address
PARAMETER
SYMBOL
DC input logic high
DDR3-1333, DDR3-1600
DDR3-1866
UNIT
NOTES
VDD
V
1, 5
VSS
VREF - 0.100
V
1, 6
Note 2
-
-
V
1, 2, 7
Note 2
VREF - 0.175
-
-
V
1, 2, 8
VIH.CA(AC150)
VREF + 0.150
Note 2
-
-
V
1, 2, 7
AC input logic low
VIL.CA(AC150)
Note 2
VREF - 0.150
-
-
V
1, 2, 8
AC input logic high
VIH.CA(AC135)
-
-
VREF + 0.135
Note 2
V
1, 2, 7
AC input logic low
VIL.CA(AC135)
-
-
Note 2
VREF - 0.135
V
1, 2, 8
AC input logic high
VIH.CA(AC125)
-
-
VREF + 0.125
Note 2
V
1, 2, 7
AC input logic low
VIL.CA(AC125)
-
-
Note 2
VREF - 0.125
V
1, 2, 8
Reference Voltage
for ADD, CMD inputs
VREFCA(DC)
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
MIN.
MAX.
MIN.
MAX.
VIH.CA(DC100)
VREF + 0.100
VDD
VREF + 0.100
DC input logic low
VIL.CA(DC100)
VSS
VREF - 0.100
AC input logic high
VIH.CA(AC175)
VREF + 0.175
AC input logic low
VIL.CA(AC175)
AC input logic high
Notes:
1. For input only pins except RESET#. VREF = VREFCA(DC).
2. See section 10.12 “Overshoot and Undershoot Specifications” on page 121.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than ± 1% VDD (for reference: approx.
± 15 mV).
4. For reference: approx. VDD/2 ± 15 mV.
5. VIH(DC) is used as a simplified symbol for VIH.CA(DC100).
6. VIL(DC) is used as a simplified symbol for VIL.CA(DC100).
7. VIH(AC) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175)
value is used when VREF + 0.175V is referenced, VIH.CA(AC150) value is used when VREF + 0.150V is referenced,
VIH.CA(AC135) value is used when VREF + 0.135V is referenced, and VIH.CA(AC125) value is used when VREF + 0.125V is
referenced.
8. VIL(AC) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175)
value is used when VREF - 0.175V is referenced, VIL.CA(AC150) value is used when VREF - 0.150V is referenced,
VIL.CA(AC135) value is used when VREF - 0.135V is referenced, and VIL.CA(AC125) value is used when VREF - 0.125V is
referenced.
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10.6.2 DC and AC Input Levels for Single-Ended Data Signals
Table 19 – Single-Ended DC and AC Input Levels for DQ and DM
PARAMETER
SYMBOL
DC input logic high
DDR3-1333, DDR3-1600
DDR3-1866
UNIT
NOTES
VDD
V
1, 5
VSS
VREF - 0.100
V
1, 6
Note 2
-
-
V
1, 2, 7
Note 2
VREF - 0.150
-
-
V
1, 2, 8
VIH.DQ(AC135)
VREF + 0.135
Note 2
VREF + 0.135
Note 2
V
1, 2, 7
AC input logic low
VIL.DQ(AC135)
Note 2
VREF - 0.135
Note 2
VREF - 0.135
V
1, 2, 8
Reference Voltage
for DQ, DM inputs
VREFDQ(DC)
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
MIN.
MAX.
MIN.
MAX.
VIH.DQ(DC100)
VREF + 0.100
VDD
VREF + 0.100
DC input logic low
VIL.DQ(DC100)
VSS
VREF - 0.100
AC input logic high
VIH.DQ(AC150)
VREF + 0.150
AC input logic low
VIL.DQ(AC150)
AC input logic high
Notes:
1. VREF = VREFDQ(DC).
2. See section 10.12 “Overshoot and Undershoot Specifications” on page 121.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFDQ(DC) by more than ± 1% VDD (for reference:
approx. ± 15 mV).
4. For reference: approx. VDD/2 ± 15 mV.
5. VIH(DC) is used as a simplified symbol for VIH.DQ(DC100).
6. VIL(DC) is used as a simplified symbol for VIL.DQ(DC100).
7. VIH(AC) is used as a simplified symbol for VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC150) value is used when VREF +
0.150V is referenced, and VIH.DQ(AC135) value is used when VREF + 0.135V is referenced.
8. VIL(AC) is used as a simplified symbol for VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC150) value is used when VREF 0.150V is referenced, and VIL.DQ(AC135) value is used when VREF - 0.135V is referenced.
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The DC-tolerance limits and AC-noise limits for the reference voltages VREFCA and VREFDQ are
illustrated in Figure 89. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands
for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g., 1 sec). This average
has to meet the min/max requirements in Table 18. Furthermore VREF(t) may temporarily deviate from
VREF(DC) by no more than ± 1% VDD.
voltage
VDD
VREF(t)
VREF AC-noise
VREF(DC)max
VREF(DC)
VDD/2
VREF(DC)min
VSS
time
Figure 89 – Illustration of VREF(DC) tolerance and VREF AC-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are
dependent on VREF.
“VREF” shall be understood as VREF(DC), as defined in Figure 89.
This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a
valid high or low level and therefore the time to which setup and hold is measured. System timing and
voltage budgets need to account for VREF(DC) deviations from the optimum position within the dataeye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time
and voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up
to the specified limit (± 1% of VDD) are included in DRAM timings and their associated deratings.
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10.6.3 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)
Table 20 – Differential DC and AC Input Level
PARAMETER
SYMBOL
Differential input high
DDR3-1333, DDR3-1600 & DDR3-1866
UNIT
NOTES
Note 3
V
1
Note 3
-0.200
V
1
VIH.DIFF(AC)
2 x (VIH(AC) - VREF)
Note 3
V
2
VIL.DIFF(AC)
Note 3
2 x (VIL(AC) - VREF)
V
2
MIN.
MAX.
VIH.DIFF
+0.200
Differential input low
VIL.DIFF
Differential input high AC
Differential input low AC
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK# use VIH.CA(AC)/VIL.CA(AC) of ADD/CMD and VREFCA; for DQS, DQS# use VIH.DQ(AC)/VIL.DQ(AC) of DQs and
VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS# need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to
section 10.12 “Overshoot and Undershoot Specifications” on page 121.
tDVAC
Differential Input Voltage (i.e. DQS – DQS#, CK - CK# )
VIHDIFF(AC)min
VIHDIFFmin
0
Half cycle
VILDIFFmax
VILDIFF(AC)max
tDVAC
time
Figure 90 – Definition of differential ac-swing and “time above AC-level” tDVAC
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Table 21 – Allowed time before ringback (tDVAC) for CK - CK# and DQS - DQS#
DDR3-1333/1600
Slew Rate
[V/nS]
tDVAC [pS]
@ VIH/LDIFF(AC) =
350mV
DDR3-1866
tDVAC [pS]
@ VIH/LDIFF(AC) =
300mV
tDVAC [pS]
@ VIH/LDIFF(AC) =
300mV
tDVAC [pS]
@ VIH/LDIFF(AC) =
(CK - CK#) only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
> 4.0
75
-
175
-
134
-
139
-
4.0
57
-
170
-
134
-
139
-
3.0
50
-
167
-
112
-
118
-
2.0
38
-
119
-
67
-
77
-
1.8
34
-
102
-
52
-
63
-
1.6
29
-
81
-
33
-
45
-
1.4
22
-
54
-
9
-
23
-
1.2
Note
-
19
-
Note
-
Note
-
1.0
Note
-
Note
-
Note
-
Note
-
< 1.0
Note
-
Note
Note
-
Note
-
Note:
Rising input differential signal shall become equal to or greater than VIHDIFF(AC) level and Falling input differential signal shall
become equal to or less than VILDIFF(AC) level.
10.6.4 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, CK#, DQS#) has also to comply with
certain requirements for single-ended signals.
CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the AC-levels
(VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle.
DQS, DQS # have to reach VSEHmin / VSELmax (approximately the AC-levels (VIH.DQ(AC) / VIL.DQ(AC) )
for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these AC-levels apply also for the
single-ended signals CK and CK#.
Table 22 – Single-ended levels for CK, DQS, CK#, DQS#
PARAMETER
Single-ended high level for strobes
Single-ended high level for CK, CK#
Single-ended low level for strobes
Single-ended low level for CK, CK#
SYM.
VSEH
VSEL
DDR3-1333, DDR3-1600 & DDR3-1866
UNIT
NOTES
Note 3
V
1, 2
(VDD/2) + 0.175
Note 3
V
1, 2
Note 3
(VDD/2) - 0.175
V
1, 2
Note 3
(VDD/2) - 0.175
V
1, 2
MIN.
MAX.
(VDD/2) + 0.175
Notes:
1. For CK, CK# use VIH.CA(AC) / VIL..CA(AC) of ADD/CMD; for strobes (DQS, DQS#) use VIH.DQ(AC) / VIL.DQ(AC) of DQs.
2. VIH.DQ(AC) / VIL.DQ(AC) for DQs is based on VREFDQ; VIH.CA(AC) / VIL.CA(AC) for ADD/CMD is based on VREFCA; if a
reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS# need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to
section 10.12 “Overshoot and Undershoot Specifications” on page 121.
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VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSEL
VSS or VSSQ
time
Figure 91 – Single-ended requirement for differential signals
Note that, while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD/2; this is nominally the
same. The transition of single-ended signals through the AC-levels is used to measure setup time. For
single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no
bearing on timing, but adds a restriction on the common mode characteristics of these signals.
10.6.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the
requirements in Table 23. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS.
VDD
CK#, DQS#
VIX
VDD/2
VIX
VIX
CK, DQS
VSEH
VSEL
VSS
Figure 92 – VIX Definition
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Table 23 – Cross point voltage for differential input signals (CK, DQS)
PARAMETER
SYMBOL
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK#
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS#
VIX(CK)
DDR3-1333, DDR3-1600 & DDR3-1866
MIN.
MAX.
- 150
150
- 175
175
VIX(DQS)
-150
150
UNIT
NOTES
mV
mV
2
1
mV
2
Note:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK# are monotonic with
a single-ended swing VSEL/VSEH of at least VDD/2 ± 250 mV, and when the differential slew rate of CK - CK# is larger
than 3 V/nS. Refer to Table 22 for VSEL and VSEH standard values.
2. The relation between VIX Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + VIX (Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + VIX (Max)) ≥ 25mV
10.6.6 Slew Rate Definitions for Single-Ended Input Signals
See section 10.16.4 “Address / Command Setup, Hold and Derating” on page 149 for singleended slew rate definitions for address and command signals.
See section 10.16.5 “Data Setup, Hold and Slew Rate Derating” on page 156 for single-ended slew
rate definitions for data signals.
10.6.7 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown
in Table 24 and Figure 93.
Table 24 – Differential Input Slew Rate Definition
Measured
from
to
Description
Differential input slew rate for rising edge
(CK - CK# and DQS - DQS#)
Differential input slew rate for falling edge
(CK - CK# and DQS - DQS#)
Defined by
VIL.DIFFmax
VIH.DIFFmin
[VIH.DIFFmin - VIL.DIFFmax] / ΔTR.DIFF
VIH.DIFFmin
VIL.DIFFmax
[VIH.DIFFmin - VIL.DIFFmax] / ΔTF.DIFF
Note: The differential signal (i.e., CK - CK# and DQS - DQS#) must be linear between these thresholds
Differential input voltage (DQS - DQS#; CK - CK#)
ΔTR.DIFF
VIH.DIFFmin
0
VIL.DIFFmax
ΔTF.DIFF
Figure 93 – Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
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10.7 DC and AC Output Measurement Levels
Table 25 – Single-ended DC and AC Output Levels
PARAMETER
SYMBOL
VALUE
UNIT
NOTES
DC output high measurement level (for IV curve linearity)
VOH(DC)
0.8 x VDDQ
V
DC output mid measurement level (for IV curve linearity)
VOM(DC)
0.5 x VDDQ
V
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.2 x VDDQ
V
AC output high measurement level (for output slew rate)
VOH(AC)
VTT + 0.1 x VDDQ
V
1
AC output low measurement level (for output slew rate)
VOL(AC)
VTT - 0.1 x VDDQ
V
1
Note:
1. The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 34 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.
Table 26 – Differential DC and AC Output Levels
VALUE
PARAMETER
SYMBOL
AC differential output high measurement level (for output
slew rate)
VOH.DIFF(AC)
AC differential output low measurement level (for output
slew rate)
VOL.DIFF(AC)
UNIT
NOTES
+0.2 x VDDQ
V
1
-0.2 x VDDQ
V
1
MIN.
MAX.
Note:
1. The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 34 Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs.
10.7.1 Output Slew Rate Definition and Requirements
The slew rate definition depends if the signal is single-ended or differential. For the relevant AC output
reference levels see above Table 25 and Table 26.
Table 27 – Output Slew Rate
PARAMETER
SYMBOL
DDR3-1333,
DDR3-1600
DDR3-1866
MIN.
MAX.
MIN.
MAX.
UNIT
NOTES
Single-ended Output Slew Rate
SRQse
2.5
5
2.5
5*1
V/nS
1, 2, 3
Differential Output Slew Rate
SRQdiff
5
10
5
12
V/nS
2, 3
Notes:
1. In two cases, a maximum slew rate of 6 V/nS applies for a single DQ signal within a byte lane.
- Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).
- Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e.
from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 5 V/nS applies.
2. Background for Symbol Nomenclature: SR: Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, QueryOutput); se: Single-ended Signals; diff: Differential Signals.
3. For RON = RZQ/7 settings only.
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10.7.1.1 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is
defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 28
and Figure 94.
Table 28 – Single-ended Output Slew Rate Definition
Measured
Description
Defined by
from
to
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)] / ΔTRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)] / ΔTFse
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Single-ended Output Voltage (i.e. DQ)
ΔTRse
VOH(AC)
VTT
VOL(AC)
ΔTFse
Figure 94 –Single-ended Output Slew Rate Definition
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10.7.1.2 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is
defined and measured between VOL.DIFFAC) and VOH.DIFF(AC) for differential signals as shown in Table
29 and Figure 95.
Table 29 – Differential Output Slew Rate Definition
Measured
Description
Defined by
from
to
Differential output slew rate for rising edge
VOL.DIFF(AC)
VOH.DIFF(AC)
[VOH.DIFF(AC) - VOL.DIFF(AC)] / ΔTRdiff
Differential output slew rate for falling edge
VOH.DIFF(AC)
VOL.DIFF(AC)
[VOH.DIFF(AC) - VOL.DIFF(AC)] / ΔTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Outut Voltage (DQS - DQS#)
ΔTRdiff
VOH.DIFF(AC)
0
VOL.DIFF(AC)
ΔTFdiff
Figure 95 – Differential Output Slew Rate Definition
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10.8 34 ohm Output Driver DC Electrical Characteristics
A functional representation of the output buffer is shown in Figure 96. Output driver impedance RON is
selected by bits “D.I.C” A1 and A5 in the MR1 Register. Two different values can be selected via MR1
settings:
RON34 = RZQ / 7 (nominal 34.3 Ω ±10% with nominal RZQ = 240 Ω)
RON40 = RZQ / 6 (nominal 40.0 Ω ±10% with nominal RZQ = 240 Ω)
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu =
RONPd =
VDDQ - VOut
I Out
VOut
I Out
under the condition that RONPd is turned off
under the condition that RONPu is turned off
Chip in Drive Mode
Output Driver
VDDQ
Ipu
RONpu
To other
circuitry
like RCV, ...
DQ
Iout
RONpd
Vout
Ipd
VSSQ
Figure 96 – Output Driver: Definition of Voltages and Currents
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Table 30 – Output Driver DC Electrical Characteristics, assuming RZQ = 240 Ω; entire operating
temperature range; after proper ZQ calibration
RONNom
Resistor
RON34Pd
34 Ω
RON34Pu
RON40Pd
40 Ω
RON40Pu
Mismatch between pull-up and pull-down,
MMPuPd
VOUT
MIN.
NOM.
MAX.
UNIT
NOTES
VOLDC = 0.2 × VDDQ
0.6
1.0
1.1
RZQ/7
1, 2, 3
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/7
1, 2, 3
VOHDC = 0.8 × VDDQ
0.9
1.0
1.4
RZQ/7
1, 2, 3
VOLDC = 0.2 × VDDQ
0.9
1.0
1.4
RZQ/7
1, 2, 3
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/7
1, 2, 3
VOHDC = 0.8 × VDDQ
0.6
1.0
1.1
RZQ/7
1, 2, 3
VOLDC = 0.2 × VDDQ
0.6
1.0
1.1
RZQ/6
1, 2, 3
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/6
1, 2, 3
VOHDC = 0.8 × VDDQ
0.9
1.0
1.4
RZQ/6
1, 2, 3
VOLDC = 0.2 × VDDQ
0.9
1.0
1.4
RZQ/6
1, 2, 3
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/6
1, 2, 3
VOHDC = 0.8 × VDDQ
0.6
1.0
1.1
RZQ/6
1, 2, 3
VOMDC = 0.5 × VDDQ
-10
+10
%
1, 2, 4
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 × VDDQ. Other calibration
schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 × VDDQ and 0.8 × VDDQ.
4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd:
Measure RONPu and RONPd, both at 0.5 * VDDQ:
MMPuPd =
RON Pu - RON Pd
x 100%
RON Nom
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10.8.1 Output Driver Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 31
and Table 32.
ΔT = T - T(@calibration); ΔV= VDDQ - VDDQ(@calibration); VDD = VDDQ
Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization.
Table 31 – Output Driver Sensitivity Definition
MIN.
MAX.
UNIT
RONPU@ VOHDC
0.6 - dRONdTH*|ΔT| - dRONdVH*|ΔV|
1.1 + dRONdTH*|ΔT| + dRONdVH*|ΔV|
RZQ/7
RON@ VOMDC
0.9 - dRONdTM*|ΔT| - dRONdVM*|ΔV|
1.1 + dRONdTM*|ΔT| + dRONdVM*|ΔV|
RZQ/7
RONPD@ VOLDC
0.6 - dRONdTL*|ΔT| - dRONdVL*|ΔV|
1.1 + dRONdTL*|ΔT| + dRONdVL*|ΔV|
RZQ/7
Table 32 – Output Driver Voltage and Temperature Sensitivity
Speed Bin
DDR3-1333
DDR3-1600 & DDR3-1866
UNIT
MIN.
MAX.
MIN.
MAX.
dRONdTM
0
1.5
0
1.5
%/°C
dRONdVM
0
0.15
0
0.13
%/mV
dRONdTL
0
1.5
0
1.5
%/°C
dRONdVL
0
0.15
0
0.13
%/mV
dRONdTH
0
1.5
0
1.5
%/°C
dRONdVH
0
0.15
0
0.13
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization.
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10.9 On-Die Termination (ODT) Levels and Characteristics
10.9.1 ODT Levels and I-V Characteristics
On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of the MR1 Register.
ODT is applied to the DQ, DM and DQS/DQS# pins.
A functional representation of the on-die termination is shown in Figure 97. The individual pull-up and
pull-down resistors (RTTPu and RTTPd) are defined as follows:
RTTPu =
RTTPd =
VDDQ - VOut
I Out
VOut
I Out
under the condition that RTTPd is turned off
under the condition that RTTPu is turned off
Chip in Termination Mode
ODT
VDDQ
Ipu
RTTpu
Iout = IPd - IPu
To other
circuitry
like RCV, ...
DQ
Iout
Vout
RTTpd
Ipd
VSSQ
Figure 97 – On-Die Termination: Definition of Voltages and Currents
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10.9.2 ODT DC Electrical Characteristics
An overview about the specification requirements for RTT and ΔVM is provided in Table 33.
Table 33 – ODT DC Impedance and Mid-Level Requirements
MR1 A9, A6, A2
RTT
Resistor
0, 1, 0
120 Ω
RTT120
0, 0, 1
60 Ω
RTT60
0, 1, 1
40 Ω
RTT40
1, 0, 1
30 Ω
1, 0, 0
20 Ω
Vout
Min.
Nom.
Max.
Unit
Notes
0.9
1.0
1.6
RZQ/2
1, 2, 3, 4
0.9
1.0
1.6
RZQ/4
1, 2, 3, 4
0.9
1.0
1.6
RZQ/6
1, 2, 3, 4
RTT30
0.9
1.0
1.6
RZQ/8
1, 2, 3, 4
RTT20
0.9
1.0
1.6
RZQ/12
1, 2, 3, 4
+5
%
1, 2, 3, 4, 5
VIL(AC) to VIH(AC)
Deviation of VM with respect to VDDQ/2, ΔVM
-5
Notes:
1. With RZQ = 240 Ω.
2. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see the following section ODT temperature and voltage sensitivity.
3. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
4. Measurement definition for RTT :
Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current
I(VIL(AC)) respectively. Calculate RTT as follows:
RTT = [VIH(AC) - VIL(AC)] / [I (VIH(AC)) - I (VIL(AC))]
5. Measurement definition for VM and ΔVM:
Measure voltage (VM) at test pin (midpoint) with no load. Calculate ΔVM as follows:
ΔVM = (2 × VM / VDDQ - 1) × 100%.
10.9.3 ODT Temperature and Voltage sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to Table 34
and Table 35. The following definitions are used:
ΔT = T - T (@calibration);ΔV = VDDQ- VDDQ (@calibration); VDD = VDDQ
Table 34 – ODT Sensitivity Definition
SYMBOL
MIN.
MAX.
UNIT
RTT
0.9 - dRTTdT × |ΔT| - dRTTdV × |ΔV|
1.6 + dRTTdT × |ΔT| + dRTTdV × |ΔV|
RZQ/2,4,6,8,12
Table 35 – ODT Voltage and Temperature Sensitivity
SYMBOL
MIN.
MAX.
UNIT
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
Note: These parameters may not be subject to production test. They are verified by design and characterization
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10.9.4 Design guide lines for RTTPU and RTTPD
Table 36 provides an overview of the ODT DC electrical pull-up and pull-down characteristics. The
values are not specification requirements, but can be used as design guide lines.
Table 36 – ODT DC Electrical Pull-Down and Pull-Up Characteristics, assuming RZQ = 240 Ω ± 1%
entire operating temperature range; after proper ZQ calibration
MR1 A9, A6, A2
RTT
Resistor
Vout
Min. Nom. Max.
Unit
Notes
0, 1, 0
120 Ω, RTT120PD240,
VOLDC = 0.2 × VDDQ
0.6
1.0
1.1
RZQ/TISFPUPD 1, 2, 3, 4, 5
0, 0, 1
60 Ω,
RTT60PD120,
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/TISFPUPD 1, 2, 3, 4, 5
0, 1, 1
40 Ω,
RTT40PD80,
VOHDC = 0.8 × VDDQ
0.9
1.0
1.4
RZQ/TISFPUPD 1, 2, 3, 4, 5
1, 0, 1
30 Ω,
RTT30PD60,
1, 0, 0
20 Ω
RTT20PD40
RTT120PU240,
VOLDC = 0.2 × VDDQ
0.9
1.0
1.4
RZQ/TISFPUPD 1, 2, 3, 4, 5
RTT60PU120,
VOMDC = 0.5 × VDDQ
0.9
1.0
1.1
RZQ/TISFPUPD 1, 2, 3, 4, 5
VOHDC = 0.8 × VDDQ
0.6
1.0
1.1
RZQ/TISFPUPD 1, 2, 3, 4, 5
RTT40PU80,
RTT30PU60,
RTT20PU40
Notes:
1. TISFPUPD: Termination Impedance Scaling Factor for Pull-Up and Pull-Down path:
TISFPUPD = 1 for RTT120PU/PD240
TISFPUPD = 2 for RTT60PU/PD120
TISFPUPD = 3 for RTT40PU/PD80
TISFPUPD = 4 for RTT30PU/PD60
TISFPUPD = 6 for RTT20PU/PD40
2. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see the above section ODT temperature and voltage sensitivity.
3. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
4. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 × VDDQ. Other calibration schemes may be
used to achieve the linearity spec shown above, e.g. calibration at 0.2 × VDDQ and 0.8 × VDDQ.
5. Not a specification requirement, but a design guide line.
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10.10 ODT Timing Definitions
10.10.1 Test Load for ODT Timings
Different than for timing measurements, the reference load for ODT timings is defined in Figure 98.
VDDQ
CK, CK#
DUT
DQ, DM
DQS, DQS#
TDQS, TDQS#
VTT = VSSQ
RTT = 25Ω
VSSQ
Timing reference point
Figure 98 – ODT Timing Reference Load
10.10.2 ODT Timing Definitions
Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table 37 and subsequent figures.
Measurement reference settings are provided in Table 38.
Table 37 – ODT Timing Definitions
Symbol
Begin Point Definition
End Point Definition
Figure
tAON
Rising edge of CK - CK# defined by the end
point of ODTLon
Extrapolated point at VSSQ
Figure 99
tAONPD
Rising edge of CK - CK# with ODT being first
registered high
Extrapolated point at VSSQ
Figure 100
tAOF
Rising edge of CK - CK#defined by the end
point of ODTLoff
End point: Extrapolated point at VRtt_Nom
Figure 101
tAOFPD
Rising edge of CK - CK# with ODT being first
registered low
End point: Extrapolated point at VRtt_Nom
Figure 102
tADC
Rising edge of CK - CK# defined by the end
point of ODTLcnw, ODTLcwn4 or ODTLcwn8
End point: Extrapolated point at VRtt_WR and
VRtt_Nom respectively
Figure 103
Table 38 – Reference Settings for ODT Timing Measurements
Measured Parameter
tAON
tAONPD
tAOF
tAOFPD
tADC
Rtt_Nom Setting
Rtt_WR Setting
VSW1 [V]
VSW2 [V]
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/4
NA
0.05
0.10
RZQ/12
NA
0.10
0.20
RZQ/12
RZQ/2
0.20
0.30
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Begin point: Rising edge of CK – CK#
defined by the end point of ODTL on
CK
VTT
CK#
tAON
TSW2
DQ, DM
DQS, DQS#
TDQS, TDQS#
TSW1
VSW2
VSW1
VSSQ
VSSQ
End point: Extrapolated point at VSSQ
Figure 99 – Definition of tAON
Begin point: Rising edge of CK - CK# with
ODT being first registered high
CK
VTT
CK#
tAONPD
TSW2
DQ, DM
DQS, DQS#
TDQS, TDQS#
TSW1
VSW2
VSSQ
VSW1
VSSQ
End point: Extrapolated point at VSSQ
Figure 100 – Definition of tAONPD
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Begin point: Rising edge of CK - CK#
defined by the end point of ODTLoff
CK
VTT
CK#
tAOF
End point: Extrapolated point at VRtt_Nom
VRtt_Nom
TSW2
DQ, DM
DQS, DQS#
TDQS, TDQS#
VSW2
TSW1
VSW1
VSSQ
Figure 101 – Definition of tAOF
Begin point: Rising edge of CK – CK# with
ODT being first registered low
CK
VTT
CK#
tAOFPD
End point: Extrapolated point at VRtt_Nom
VRtt_Nom
TSW2
DQ, DM
DQS, DQS#
TDQS, TDQS#
VSW2
TSW1
VSW1
VSSQ
Figure 102 – Definition of tAOFPD
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Begin point: Rising edge of CK – CK#
defined by the end point of ODTLcnw
Begin point: Rising edge of CK – CK# defined by
the end point of ODTLcwn4 or ODTLcwn8
CK
VTT
CK#
tADC
tADC
VRtt_Nom
VRtt_Nom
TSW21
End point: Extrapolated point at VRtt_Nom
DQ, DM
DQS, DQS#
TDQS, TDQS#
TSW1
TSW2
VSW2
TSW1
VSW1
VRtt_WR
End point: Extrapolated point at VRtt_WR
VSSQ
Figure 103 – Definition of tADC
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10.11 Input/Output Capacitance
DDR3-1333
DDR3-1600
DDR3-1866
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
CIO
1.4
2.5
1.4
2.3
1.4
Input capacitance
(CK and CK#)
CCK
0.8
1.4
0.8
1.4
Delta of input capacitance
(CK and CK#)
CDCK
0
0.15
0
Delta of Input/Output capacitance
(DQS and DQS#)
CDDQS
0
0.15
Input capacitance
(CTRL, ADD, CMD input-only pins)
CI
0.75
Delta of input capacitance
(All CTRL input-only pins)
CDI_CTRL
Delta of input capacitance
(All ADD/CMD input-only pins)
PARAMETER
SYMBOL
UNIT
NOTES
Input/output capacitance
(DQ, DM, DQS, DQS#, TDQS, TDQS#)
2.2
pF
1, 2, 3
0.8
1.3
pF
2, 3
0.15
0
0.15
pF
2, 3, 4
0
0.15
0
0.15
pF
2, 3, 5
1.3
0.75
1.3
0.75
1.2
pF
2, 3, 6
-0.4
0.2
-0.4
0.2
-0.4
0.2
pF
2, 3, 7, 8
CDI_ADD_CMD
-0.4
0.4
-0.4
0.4
-0.4
0.4
pF
2, 3, 9, 10
Delta of Input/output capacitance
(DQ, DM, DQS, DQS#, TDQS, TDQS#)
CDIO
-0.5
0.3
-0.5
0.3
-0.5
0.3
pF
2, 3, 11
Input/output capacitance of ZQ signal
CZQ
3
3
3
pF
2, 3, 12
Notes:
1. Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS.
2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured
according to JEP147 (Procedure for measuring input capacitance using a vector network analyzer (VNA) with VDD, VDDQ,
VSS, VSSQ applied and all other pins floating (except the ball under test, CKE, RESET# and ODT as necessary).
VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here.
4. Absolute value of CCK-CCK#.
5. Absolute value of CIO(DQS)-CIO(DQS#).
6. CI applies to ODT, CS#, CKE, A0-A14, BA0-BA2, RAS#, CAS#, WE#.
7. CDI_CTRL applies to ODT, CS# and CKE.
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK#)).
9. CDI_ADD_CMD applies to A0-A14, BA0-BA2, RAS#, CAS# and WE#.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#)).
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#)).
12. Maximum external load capacitance on ZQ signal: 5 pF.
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10.12 Overshoot and Undershoot Specifications
10.12.1 AC Overshoot /Undershoot Specification for Address and Control Pins:
Applies to A0-A14, BA0-BA2, CS#, RAS#, CAS#, WE#, CKE, ODT
PARAMETER
DDR3-1333
DDR3-1600
DDR3-1866
UNIT
Maximum peak amplitude allowed for overshoot area
0.4
0.4
0.4
V
Maximum peak amplitude allowed for undershoot area
0.4
0.4
0.4
V
Maximum overshoot area above VDD
0.4
0.33
0.28
V-nS
Maximum undershoot area below VSS
0.4
0.33
0.28
V-nS
10.12.2 AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins:
Applies to CK, CK#, DQ, DQS, DQS#, DM
DDR3-1333
DDR3-1600
DDR3-1866
UNIT
Maximum peak amplitude allowed for overshoot area
0.4
0.4
0.4
V
Maximum peak amplitude allowed for undershoot area
0.4
0.4
0.4
V
Maximum overshoot area above VDDQ
0.15
0.13
0.11
V-nS
Maximum undershoot area below VSSQ
0.15
0.13
0.11
V-nS
PARAMETER
Maximum Amplitude
Overshoot Area
VDD/VDDQ
Volts (V)
VSS/VSSQ
Maximum Amplitude
Undershoot Area
Time (nS)
Figure 104 – AC Overshoot and Undershoot Definition
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10.13 IDD and IDDQ Specification Parameters and Test Conditions
10.13.1 IDD and IDDQ Measurement Conditions
In this section, IDD and IDDQ measurement conditions such as test load and patterns are defined.
Figure 105 shows the setup and test load for IDD and IDDQ measurements.
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the
DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ
currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM.
They can be used to support correlation of simulated IO power to actual IO power as
outlined in Figure 106. In DRAM module application, IDDQ cannot be measured separately
since VDD and VDDQ are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
“0” and “LOW” is defined as VIN ≤ VILAC(max).
“1” and “HIGH” is defined as VIN ≥ VIHAC(min).
“MID-LEVEL” is defined as inputs are VREF = VDD / 2.
Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 39.
Basic IDD and IDDQ Measurement Conditions are described in Table 40.
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 41 through Table 48.
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not
limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0b (Output Buffer enabled in MR1);
Rtt_Nom = RZQ/6 (40 Ohm in MR1);
Rtt_WR = RZQ/2 (120 Ohm in MR2);
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
Define D = {CS#, RAS#, CAS#, WE# } := {HIGH, LOW, LOW, LOW}
Define D# = {CS#, RAS#, CAS#, WE# } := {HIGH, HIGH, HIGH, HIGH}
Table 39 – Timings used for IDD and IDDQ Measurement-Loop Patterns
Speed Bin
DDR3-1333
DDR3-1600
DDR3-1866
CL-nRCD-nRP
9-9-9
11-11-11
13-13-13
Part Number Extension
-15/15I
-12/12I
-11
tCK
1.5
1.25
1.07
nS
CL
9
11
13
nCK
nRCD
9
11
13
nCK
Unit
nRC
33
39
45
nCK
nRAS
24
28
32
nCK
nRP
9
11
13
nCK
nFAW
20
24
26
nCK
nRRD
4
5
5
nCK
nRFC 2 Gb
107
128
150
nCK
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(optional)
IDDQ
IDD
VDD
VDDQ
DDR3
SDRAM
RESET#
CK/CK#
CKE
CS#
RAS#, CAS#, WE#
RTT = 25 Ω
DQS, DQS#
DQ, DM
TDQS, TDQS#
VDDQ / 2
A, BA
ODT
ZQ
VSS
VSSQ
NOTE: DIMM level Output test load condition may be different from above.
Figure 105 – Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
Application specific
memory channel
environment
Channel IO
Power
simulation
IDDQ Test Load
IDDQ
Simulation
IDDQ
Measurement
Correlation
Correlation
Channel IO Power
Number
Figure 106 – Correlation from simulated Channel IO Power to actual Channel IO Power
supported by IDDQ Measurement
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Table 40 – Basic IDD and IDDQ Measurement Conditions
SYM.
DESCRIPTION
IDD0
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 39; BL: 8(1); AL: 0; CS#: High
between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according
to Table 41; Data IO: MID-LEVEL; DM: stable at 0; Bank Activity: Cycling with one bank active at
a time: 0,0,1,1,2,2,... (see Table 41); Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0; Pattern Details: see Table 41
IDD1
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 39; BL: 8(1,6); AL: 0; CS#:
High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially
toggling according to Table 42; DM: stable at 0; Bank Activity: Cycling with one bank active at a
time: 0,0,1,1,2,2,... (see Table 42); Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0; Pattern Details: see Table 42
IDD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 39; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 43; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers(2); ODT Signal: stable at 0; Pattern Details: see Table 43
IDD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 39; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 44; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers(2); ODT Signal: toggling according to Table 44; Pattern Details: see Table 44
IDDQ2NT
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
IDD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 39; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0; Pecharge Power Down Mode: Slow Exit(3)
IDD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 39; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0; Pecharge Power Down Mode: Fast Exit(3)
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 39; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 39; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to Table 43; Data IO:
MID-LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers(2); ODT Signal: stable at 0; Pattern Details: see Table 43
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 39; BL: 8(1); AL: 0; CS#: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM: stable at 0;
Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers(2); ODT
Signal: stable at 0
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Basic IDD and IDDQ Measurement Conditions, continued
SYM.
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
IDD8
DESCRIPTION
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 39; BL: 8(1,6); AL: 0; CS#: High between RD;
Command, Address, Bank Address Inputs: partially toggling according to Table 45; Data IO:
seamless read data burst with different data between one burst and the next one according to Table
45; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks:
0,0,1,1,2,2,... (see Table 45); Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal:
stable at 0; Pattern Details: see Table 45
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 39; BL: 8(1); AL: 0; CS#: High between WR;
Command, Address, Bank Address Inputs: partially toggling according to Table 46; Data IO:
seamless write data burst with different data between one burst and the next one according to
Table 46; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... (see Table 46); Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal:
stable at HIGH; Pattern Details: see Table 46
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 39; BL: 8(1); AL: 0; CS#: High between
REF; Command, Address, Bank Address Inputs: partially toggling according to Table 47; Data
IO: MID-LEVEL; DM: stable at 0; Bank Activity: REF command every nRFC (see Table 47);
Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: stable at 0; Pattern Details:
see Table 47
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled(4); Self-Refresh Temperature Range (SRT):
Normal(5); CKE: Low; External clock: Off; CK and CK#: LOW; CL: see Table 39; BL: 8(1); AL: 0;
CS#, Command, Address, Bank Address, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity:
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers(2); ODT Signal: MIDLEVEL
Self-Refresh Current: Extended Temperature Range
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled(4); Self-Refresh Temperature Range (SRT):
Extended(5); CKE: Low; External clock: Off; CK and CK#: LOW; CL: see Table 39; BL: 8(1); AL: 0;
CS#, Command, Address, Bank Address, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode
Registers(2); ODT Signal: MID-LEVEL
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 39; BL:
8(1,6); AL: CL-1; CS#: High between ACT and RDA; Command, Address, Bank Address Inputs:
partially toggling according to Table 48; Data IO: read data bursts with different data between one
burst and the next one according to Table 48; DM: stable at 0; Bank Activity: two times interleaved
cycling through banks (0, 1, ...7) with different addressing, see Table 48; Output Buffer and RTT:
Enabled in Mode Registers(2); ODT Signal: stable at 0; Pattern Details: see Table 48
RESET# Low Current
RESET#: Low; External clock: Off; CK and CK#: Low; CKE: FLOATING; CS#, Command,
Address, Bank Address, Data IO: FLOATING; ODT Signal: FLOATING
RESET# Low current reading is valid once power is stable and RESET has been Low for at least
1mS
Notes:
1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00b.
2. Output Buffer Enable: set MR1 A[12] = 0b; set MR1 A[5,1] = 01b; Rtt_Nom enable: set MR1 A[9,6,2] = 011b; Rtt_WR
enable: set MR2 A[10,9] = 10b.
3. Pecharge Power Down Mode: set MR0 A12=0b for Slow Exit or MR0 A12=1b for Fast Exit.
4. Auto Self-Refresh (ASR): set MR2 A6 = 0b to disable or 1b to enable feature.
5. Self-Refresh Temperature Range (SRT): set MR2 A7=0b for normal or 1b for extended temperature range.
6. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0b.
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CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[14:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
ACT
0
0
1
1
0
0
0
0
0
0
0
-
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
-
3, 4
D#, D#
1
1
1
1
0
0
0
0
0
0
0
-
0
0
0
-
...
nRAS
Static High
toggling
0
Command
Data2
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 41 – IDD0 Measurement-Loop Pattern1
...
Repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
0
0
Repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
0
0
0
F
0
-
1*nRC+1, 2
D, D
1
0
0
0
0
0
0
0
0
F
0
-
D#, D#
1
1
1
1
0
0
0
0
0
F
0
-
0
-
1*nRC+3, 4
...
1*nRC+nRAS
...
Repeat pattern nRC + 1,...,4 until nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
0
0
0
F
Repeat pattern nRC + 1,...,4 until 2*nRC - 1, truncate if necessary
1
2*nRC
Repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
Repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
Repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
Repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
Repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
Repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
Repeat Sub-Loop 0, use BA[2:0] = 7 instead
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 126 -
W632GG8KB
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[14:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
ACT
0
0
1
1
0
0
0
0
0
0
0
-
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
-
3, 4
D#, D#
1
1
1
1
0
0
0
0
0
0
0
-
0
0
0
00000000
0
0
0
-
...
nRCD
...
nRAS
Static High
toggling
0
Command
Data2
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 42 – IDD1 Measurement-Loop Pattern1
...
Repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
0
0
Repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
0
0
Repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
0
0
0
F
0
-
1*nRC+1, 2
D, D
1
0
0
0
0
0
0
0
0
F
0
-
1*nRC+3, 4
D#, D#
1
1
1
1
0
0
0
0
0
F
0
-
0
00110011
0
-
...
1*nRC+nRCD
...
1*nRC+nRAS
...
Repeat pattern nRC + 1,...,4 until nRC + nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
0
0
0
F
Repeat pattern nRC + 1,...,4 until nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
0
0
0
F
Repeat pattern nRC + 1,...,4 until 2*nRC - 1, truncate if necessary
1
2*nRC
Repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
Repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
Repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
Repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
Repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
Repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
Repeat Sub-Loop 0, use BA[2:0] = 7 instead
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 127 -
W632GG8KB
RAS#
CAS#
WE#
ODT
BA[2:0]
A[14:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D#
1
1
1
1
0
0
0
0
0
F
0
-
D#
1
1
1
1
0
0
0
0
0
F
0
-
Static High
3
toggling
Command
CS#
0
Data2
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 43 – IDD2N and IDD3N Measurement-Loop Pattern1
1
4-7
Repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
Repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
Repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
Repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
Repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-27
Repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
Repeat Sub-Loop 0, use BA[2:0] = 7 instead
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
RAS#
CAS#
WE#
ODT
BA[2:0]
A[14:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D#
1
1
1
1
0
0
0
0
0
F
0
-
D#
1
1
1
1
0
0
0
0
0
F
0
-
Static High
toggling
3
1
Command
CS#
0
Data2
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 44 – IDD2NT and IDDQ2NT Measurement-Loop Pattern1
4-7
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-27
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 128 -
W632GG8KB
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[14:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
RD
0
1
0
1
0
0
0
0
0
0
0
00000000
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2, 3
D#, D#
1
1
1
1
0
0
0
0
0
0
0
-
4
RD
0
1
0
1
0
0
0
0
0
F
0
00110011
5
D
1
0
0
0
0
0
0
0
0
F
0
-
6, 7
D#, D#
1
1
1
1
0
0
0
0
0
F
0
-
1
8-15
Repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
Repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
Repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
Repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
Repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
Repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
Repeat Sub-Loop 0, but BA[2:0] = 7
Static High
Cycle
Number
Data2
0
toggling
Command
Sub-Loop
CKE
CK, CK#
Table 45 – IDD4R and IDDQ4R Measurement-Loop Pattern1
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
RAS#
CAS#
WE#
ODT
BA[2:0]
A[14:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Command
CS#
Static High
toggling
0
Data2
0
WR
0
1
0
0
1
0
0
0
0
0
0
00000000
1
D
1
0
0
0
1
0
0
0
0
0
0
-
2, 3
D#, D#
1
1
1
1
1
0
0
0
0
0
0
-
4
WR
0
1
0
0
1
0
0
0
0
F
0
00110011
5
D
1
0
0
0
1
0
0
0
0
F
0
-
1
1
1
1
1
0
0
0
0
F
0
-
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 46 – IDD4W Measurement-Loop Pattern1
6, 7
D#, D#
1
8-15
Repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
Repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
Repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
Repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
Repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
Repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
Repeat Sub-Loop 0, but BA[2:0] = 7
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are used according to WR Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Publication Release Date: Dec. 08, 2014
Revision: A04
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W632GG8KB
Static High
toggling
1
2
RAS#
CAS#
WE#
ODT
BA[2:0]
A[14:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Command
CS#
0
Data2
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
-
1
1
1
1
0
0
0
0
0
F
0
-
Cycle
Number
Sub-Loop
CKE
CK, CK#
Table 47 – IDD5B Measurement-Loop Pattern1
3, 4
D#, D#
5...8
Repeat cycles 1...4, but BA[2:0] = 1
9...12
Repeat cycles 1...4, but BA[2:0] = 2
13...16
Repeat cycles 1...4, but BA[2:0] = 3
17...20
Repeat cycles 1...4, but BA[2:0] = 4
21...24
Repeat cycles 1...4, but BA[2:0] = 5
25...28
Repeat cycles 1...4, but BA[2:0] = 6
29...32
Repeat cycles 1...4, but BA[2:0] = 7
33...nRFC - 1
Repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 130 -
W632GG8KB
Table 48 – IDD7 Measurement-Loop Pattern1
Command
CS#
RAS#
CAS#
WE#
ODT
BA[2:0]
A[14:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
0
ACT
0
0
1
1
0
0
0
0
0
0
0
-
1
RDA
0
1
0
1
0
0
0
1
0
0
0
00000000
D
1
0
0
0
0
0
0
0
0
0
0
-
Cycle
Number
Sub-Loop
CKE
CK, CK#
ATTENTION: Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
2
...
1
nRRD
ACT
0
0
1
1
0
1
0
0
0
F
0
-
nRRD+1
RDA
0
1
0
1
0
1
0
1
0
F
0
00110011
nRRD+2
D
1
0
0
0
0
1
0
0
0
F
0
-
0
0
0
F
0
-
0
-
Static High
...
toggling
Repeat above D Command until nRRD - 1
Repeat above D Command until 2 * nRRD -1
2
2*nRRD
Repeat Sub-Loop 0, but BA[2:0] = 2
3
3*nRRD
Repeat Sub-Loop 1, but BA[2:0] = 3
4
4*nRRD
5
nFAW
Repeat Sub-Loop 0, but BA[2:0] = 4
6
nFAW+nRRD
Repeat Sub-Loop 1, but BA[2:0] = 5
7
nFAW+2*nRRD
Repeat Sub-Loop 0, but BA[2:0] = 6
8
nFAW+3*nRRD
Repeat Sub-Loop 1, but BA[2:0] = 7
9
nFAW+4*nRRD
10
D
1
0
0
0
0
3
Assert and repeat above D Command until nFAW - 1, if necessary
D
1
0
0
0
0
7
0
0
0
F
Assert and repeat above D Command until 2 * nFAW - 1, if necessary
2*nFAW+0
ACT
0
0
1
1
0
0
0
0
0
F
0
-
2*nFAW+1
RDA
0
1
0
1
0
0
0
1
0
F
0
00110011
D
1
0
0
0
0
0
0
0
0
F
0
-
2*nFAW+2
11
Data2
Repeat above D Command until 2 * nFAW + nRRD - 1
2*nFAW+nRRD
ACT
0
0
1
1
0
1
0
0
0
0
0
-
2*nFAW+nRRD+1
RDA
0
1
0
1
0
1
0
1
0
0
0
00000000
D
1
0
0
0
0
1
0
0
0
0
0
-
0
0
-
2*nFAW+nRRD+2
Repeat above D Command until 2 * nFAW + 2 * nRRD -1
12
2*nFAW+2*nRRD
Repeat Sub-Loop 10, but BA[2:0] = 2
13
2*nFAW+3*nRRD
Repeat Sub-Loop 11, but BA[2:0] = 3
14
2*nFAW+4*nRRD
D
1
0
0
0
0
3
0
0
0
Assert and repeat above D Command until 3 * nFAW - 1, if necessary
15
3*nFAW
Repeat Sub-Loop 10, but BA[2:0] = 4
16
3*nFAW+nRRD
Repeat Sub-Loop 11, but BA[2:0] = 5
17
3*nFAW+2*nRRD
Repeat Sub-Loop 10, but BA[2:0] = 6
18
3*nFAW+3*nRRD
Repeat Sub-Loop 11, but BA[2:0] = 7
19
3*nFAW+4*nRRD
D
1
0
0
0
0
7
0
0
0
0
0
-
Assert and repeat above D Command until 4 * nFAW - 1, if necessary
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are used according to RD Commands, otherwise MID-LEVEL.
2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 131 -
W632GG8KB
10.13.2 IDD Current Specifications
Speed Bin
SYM.
DDR3-1333 DDR3-1600 DDR3-1866
Part Number Extension
-15/15I
-12/12I
-11
DEFINITION
MAX.
MAX.
MAX.
90
95
105
mA
110
115
125
mA
Precharge Standby Current
60
65
75
mA
IDD2NT
Precharge Standby ODT Current
90
95
100
mA
IDD2P0
Precharge Power Down Current Slow Exit
19
19
19
mA
IDD2P1
Precharge Power Down Current Fast Exit
48
50
55
mA
IDD2Q
Precharge Quiet Standby Current
60
65
70
mA
IDD3N
Active Standby Current
65
70
75
mA
IDD3P
Active Power Down Current
50
55
60
mA
IDD4R
Operating Burst Read Current
205
220
250
mA
IDD4W
Operating Burst Write Current
180
200
230
mA
IDD5B
Burst Refresh Current
135
140
145
mA
IDD0
Operating One Bank Active-Precharge Current
IDD1
Operating One Bank Active-Read-Precharge Current
IDD2N
UNIT
IDD6
Self-Refresh Current, TOPER = 0 - 85°C
19
19
19
mA
IDD6ET
Self-Refresh Current, TOPER = 0 - 95°C
21
21
21
mA
330
340
360
mA
19
19
19
mA
IDD7
Operating Bank Interleave Read Current
IDD8
RESET# Low Current
Notes:
1. Max. values for IDD currents consider worst case conditions of process, temperature and voltage.
2. The IDD values must be derated (increased) when operated outside the range 0°C ≤ TCASE ≤ 85°C:
(a) When TCASE < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and
IDD6, IDD6ET and IDD7 must be derated by 7%.
(b) When TCASE > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by
2%; and IDD2P0, IDD2P1 must be derated by 30%.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 132 -
W632GG8KB
10.14 Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the
min/max values may result in malfunction of the DDR3 SDRAM device.
Definition for tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where
each clock period is calculated from rising edge to rising edge.
N
tCK(avg) = tCK j / N
j 1
where
N = 200
Definition for tCK(abs)
tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next
consecutive rising edge. tCK(abs) is not subject to production test.
Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high
pulses.
N
tCH(avg) = tCH j / (N × tCK(avg))
j 1
where
N = 200
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low
pulses.
N
tCL(avg) = tCL j / (N × tCK(avg))
j 1
where
N = 200
Definition for tJIT(per) and tJIT(per,lck)
tJIT(per) is defined as the largest deviation of any signal tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not subject to production test.
Publication Release Date: Dec. 08, 2014
Revision: A04
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Definition for tJIT(cc) and tJIT(cc,lck)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles.
tJIT(cc) = Max of |{tCKi +1 - tCKi}|.
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not subject to production test.
Definition for tERR(nper)
tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not
subject to production test.
10.15 Speed Bins
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRC and tRAS for each corresponding bin.
10.15.1 DDR3-1333 Speed Bin and Operating Conditions
Speed Bin
CL-nRCD-nRP
Part Number Extension
Parameter
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
Internal read command to first data
ACT to internal read or write delay time
Symbol
fCKMAX
tAA
tRCD
PRE command period
tRP
ACT to ACT or REF command period
tRC
ACT to PRE command period
CL = 6
CL = 7
CWL = 5
CWL = 6, 7
CWL = 5
tRAS
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 6
tCK(AVG)
CWL = 7
CWL = 5
CL = 8
CWL = 6
CWL = 7
CWL = 5, 6
CL = 9
CWL = 7
CWL = 5, 6
CL = 10
CWL = 7
Supported CL Settings
Supported CWL Settings
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Sup_CL
Sup_CWL
DDR3-1333
9-9-9
-15/15I
Min.
Max.
667
13.5
20
(13.125) *9
13.5
(13.125) *9
13.5
(13.125) *9
49.5
(49.125) *9
36
9 * tREFI
2.5
3.3
Reserved
Reserved
1.875
< 2.5
(Optional) *9
Reserved
Reserved
1.875
< 2.5
Reserved
Reserved
1.5
< 1.875
Reserved
1.5
< 1.875
6, (7), 8, 9, 10
5, 6, 7
UNIT
NOTES
MHz
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nCK
nCK
1, 2, 3, 4, 6
5
5
1, 2, 3, 4, 6
5
5
1, 2, 3, 4, 6
5
5
1, 2, 3, 4, 6
5
1,2,3,4,6
Note:
Field value contents in blue font or parentheses are optional AC parameter and CL setting. Detail descriptions refer to note 9.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 134 -
W632GG8KB
10.15.2 DDR3-1600 Speed Bin and Operating Conditions
Speed Bin
DDR3-1600
CL-nRCD-nRP
11-11-11
Part Number Extension
-12/12I
UNIT
NOTES
Parameter
Symbol
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
fCKMAX
800
MHz
tAA
13.75
(13.125) *9
20
nS
ACT to internal read or write delay time
tRCD
13.75
(13.125) *9
nS
PRE command period
tRP
13.75
(13.125) *9
nS
ACT to ACT or REF command period
tRC
48.75
(48.125) *9
nS
ACT to PRE command period
tRAS
35
9 * tREFI
nS
CWL = 5
tCK(AVG)
2.5
3.3
nS
1, 2, 3, 4, 7
CWL = 6, 7, 8
tCK(AVG)
Reserved
nS
5
CWL = 5
tCK(AVG)
Reserved
nS
5
CWL = 6
tCK(AVG)
< 2.5
nS
1, 2, 3, 4, 7
*9
nS
5
CWL = 7, 8
tCK(AVG)
Reserved
nS
5
CWL = 5
tCK(AVG)
Reserved
nS
5
CWL = 6
tCK(AVG)
nS
1, 2, 3, 4, 7
CWL = 7, 8
tCK(AVG)
Reserved
nS
5
CWL = 5, 6
tCK(AVG)
Reserved
nS
5
CWL = 7
tCK(AVG)
CWL = 8
Internal read command to first data
CL = 6
CL = 7
CL = 8
CL = 9
CL =10
CL =11
1.875
(Optional)
1.875
1.5
< 2.5
nS
5
(Optional) *9
< 1.875
nS
1, 2, 3, 4, 7
tCK(AVG)
Reserved
nS
5
CWL = 5, 6
tCK(AVG)
Reserved
nS
5
CWL = 7
tCK(AVG)
nS
1, 2, 3, 4, 7
CWL = 8
tCK(AVG)
Reserved
nS
5
CWL = 5, 6, 7
tCK(AVG)
Reserved
nS
5
CWL = 8
tCK(AVG)
nS
1, 2, 3, 4, 7
1.5
< 1.875
1.25
< 1.5
Supported CL Settings
Sup_CL
6, (7), 8, (9), 10, 11
nCK
Supported CWL Settings
Sup_CWL
5, 6, 7, 8
nCK
Note:
Field value contents in blue font or parentheses are optional AC parameter and CL setting. Detail descriptions refer to note 9.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 135 -
W632GG8KB
10.15.3 DDR3-1866 Speed Bin and Operating Conditions
Speed Bin
DDR3-1866
CL-nRCD-nRP
13-13-13
Part Number Extension
-11
UNIT
NOTES
Parameter
Symbol
Min.
Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
fCKMAX
933
MHz
tAA
13.91
20
nS
ACT to internal read or write delay time
tRCD
13.91
nS
PRE command period
tRP
13.91
nS
ACT to ACT or REF command period
tRC
47.91
nS
ACT to PRE command period
tRAS
34
9 * tREFI
nS
CWL = 5
tCK(AVG)
2.5
3.3
nS
1, 2, 3, 4, 8
CWL = 6, 7, 8, 9
tCK(AVG)
Reserved
nS
5
CWL = 5
tCK(AVG)
Reserved
nS
5
CWL = 6
tCK(AVG)
nS
1, 2, 3, 4, 8
CWL = 7, 8, 9
tCK(AVG)
Reserved
nS
5
CWL = 5, 6
tCK(AVG)
Reserved
nS
5
CWL = 7
tCK(AVG)
nS
1, 2, 3, 4, 8
Internal read command to first data
CL = 6
CL = 8
CL =10
CL =13
1.875
1.5
< 2.5
< 1.875
CWL = 8, 9
tCK(AVG)
Reserved
nS
5
CWL = 5, 6, 7, 8
tCK(AVG)
Reserved
nS
5
CWL = 9
tCK(AVG)
nS
1, 2, 3, 4, 8
1.07
< 1.25
Supported CL Settings
Sup_CL
6, 8, 10, 13
nCK
Supported CWL Settings
Sup_CWL
5, 6, 7, 9
nCK
Publication Release Date: Dec. 08, 2014
Revision: A04
- 136 -
W632GG8KB
10.15.4 Speed Bin General Notes
The absolute specification for all speed bins is TOPER and VDD = VDDQ = 1.5V ± 0.075V. In addition
the following general notes apply.
1. Max. limits are exclusive. E.g. if tCK(AVG).MAX value is 2.5 nS, tCK(AVG) needs to be < 2.5 nS.
2. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making
a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as
requirements from CWL setting.
3. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are
synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An
application should use the next smaller standard tCK(AVG) value (2.5, 1.875, 1.5, 1.25 nS or 1.07 nS)
when calculating CL [nCK] = tAA [nS] / tCK(AVG) [nS], rounding up to the next ‘Supported CL’.
4. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3nS or 2.5nS or 1.875 nS or 1.25 nS). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
5. ‘Reserved’ settings are not allowed. User must program a different value.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125
nS or lower. SPD settings must be programmed to match. For example, DDR3-1333 (9-9-9) devices
supporting down binning to DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 (11-11-11) devices supporting
down binning to DDR3-1333 (9-9-9) or DDR3-1066 (7-7-7) should program 13.125 nS in SPD bytes
for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to
13.125 nS, tRCmin (Byte 21, 23) also should be programmed accodingly. For example, 49.125nS
(tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3-1333 (9-9-9) and 48.125 nS (tRASmin + tRPmin =
35 nS + 13.125 nS) for DDR3-1600 (11-11-11).
Publication Release Date: Dec. 08, 2014
Revision: A04
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W632GG8KB
10.16 AC Characteristics
10.16.1 AC Timing and Operating Condition for -11 speed grade
SPEED GRADE
SYMBOL
DDR3-1866 (-11)
PARAMETER
MIN.
MAX.
UNITS
Common Notes
NOTES
1, 2, 3, 4
Clock Input Timing
tCK(DLL-off)
Minimum clock cycle time (DLL-off mode)
tCK(avg)
Average Clock Period
tCH(avg)
Average CK/CK# high pulse width
tCL(avg)
Average CK/CK# low pulse width
tCK(avg)
0.47
0.53
tCK(avg)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
tCH(abs)
Absolute CK/CK# high pulse width
0.43
tCL(abs)
Absolute CK/CK# low pulse width
tJIT(per)
Clock Period Jitter
Clock Period Jitter during DLL locking period
tJIT(cc,lck)
tJIT(duty)
pS
37
tCK(avg)
38
0.43
tCK(avg)
39
-60
60
pS
-50
50
pS
Cycle to Cycle Period Jitter
120
pS
Cycle to Cycle Period Jitter during DLL locking
period
100
pS
Already included in tCH(abs) and
tCL(abs)
pS
Clock Duty Cycle Jitter
tERR(2per)
Cumulative error across 2 cycles
-88
88
pS
tERR(3per)
Cumulative error across 3 cycles
-105
105
pS
tERR(4per)
Cumulative error across 4 cycles
-117
117
pS
tERR(5per)
Cumulative error across 5 cycles
-126
126
pS
tERR(6per)
Cumulative error across 6 cycles
-133
133
pS
tERR(7per)
Cumulative error across 7 cycles
-139
139
pS
tERR(8per)
Cumulative error across 8 cycles
-145
145
pS
tERR(9per)
Cumulative error across 9 cycles
-150
150
pS
tERR(10per) Cumulative error across 10 cycles
-154
154
pS
tERR(11per) Cumulative error across 11 cycles
-158
158
pS
tERR(12per) Cumulative error across 12 cycles
-161
161
pS
tERR(nper)
Cumulative error across n = 13, 14...49, 50
cycles
45
pS
0.53
Absolute Clock Period
tJIT(cc)
nS
0.47
tCK(abs)
tJIT(per,lck)
8
See “Speed Bin” on page 136
Min.: tJIT(per)min * (1 + 0.68 * ln(n))
Max.: tJIT(per)max * (1 + 0.68 * ln(n))
pS
7
Publication Release Date: Dec. 08, 2014
Revision: A04
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W632GG8KB
AC Timing and Operating Condition for -11 speed grade, continued
SPEED GRADE
SYMBOL
DDR3-1866 (-11)
PARAMETER
UNITS
NOTES
85
pS
23
MIN.
MAX.
Data Timing
tDQSQ
DQS, DQS# to DQ skew, per group, per access
tQH
DQ output hold time from DQS, DQS#
0.38
tCK(avg)
18, 23
tLZ(DQ)
DQ low impedance time from CK, CK#
-390
195
pS
17, 23, 24
tHZ(DQ)
DQ high impedance time from CK, CK#
195
tDS(AC135)
tDH(DC100)
tDIPW
pS
17, 23, 24
68
pS
11, 40
Data setup time to
DQS, DQS#
Base specification @ 2 V/nS
135.5
pS
11, 40, 42
Data hold time from
DQS, DQS#
Base specification @ 2 V/nS
70
pS
11, 40
VREF @ 2 V/nS
120
pS
11, 40, 42
pS
10
VREF @ 2 V/nS
DQ and DM Input pulse width for each input
320
Data Strobe Timing
tRPRE
DQS,DQS# differential READ Preamble
0.9
Note 21
tCK(avg) 18, 21, 23
tRPST
DQS,DQS# differential READ Postamble
0.3
Note 22
tCK(avg) 18, 22, 23
tQSH
DQS,DQS# differential output high time
0.4
tCK(avg)
18, 23
tQSL
DQS,DQS# differential output low time
0.4
tCK(avg)
18, 23
tWPRE
DQS,DQS# differential WRITE Preamble
0.9
tCK(avg)
46
tWPST
DQS,DQS# differential WRITE Postamble
0.3
tCK(avg)
46
tDQSCK
DQS,DQS# rising edge output access time from
rising CK, CK#
-195
195
pS
17, 23
tLZ(DQS)
DQS and DQS# low-impedance time from CK,
CK# (Referenced from RL - 1)
-390
195
pS
17, 23, 24
tHZ(DQS)
DQS and DQS# high-impedance time from CK,
CK# (Referenced from RL + BL/2)
195
pS
17, 23, 24
tDQSL
DQS,DQS# differential input low pulse width
0.45
0.55
tCK(avg)
12, 14
tDQSH
DQS,DQS# differential input high pulse width
0.45
0.55
tCK(avg)
13, 14
tDQSS
DQS,DQS# rising edge to CK,CK# rising edge
-0.27
0.27
tCK(avg)
16
tDSS
DQS,DQS# falling edge setup time to CK,CK#
rising edge
0.18
tCK(avg)
15, 16
tDSH
DQS,DQS# falling edge hold time from CK,CK#
rising edge
0.18
tCK(avg)
15, 16
Internal read command to first data
nS
8
ACT to internal read or write delay time
nS
8
nS
8
Command and Address Timing
tAA
tRCD
See “Speed Bin” on page 136
tRP
PRE command period
tRC
ACT to ACT or REF command period
nS
8
tRAS
ACT to PRE command period
nS
8
Publication Release Date: Dec. 08, 2014
Revision: A04
- 139 -
W632GG8KB
AC Timing and Operating Condition for -11 speed grade, continued
SPEED GRADE
SYMBOL
DDR3-1866 (-11)
PARAMETER
MIN.
MAX.
UNITS NOTES
Command and Address Timing
tDLLK
DLL locking time
512
tRTP
Internal READ Command to PRECHARGE
Command delay
max(4nCK, 7.5nS)
8
tWTR
Delay from start of internal write transaction to
internal read command
max(4nCK, 7.5nS)
8, 26
tWR
WRITE recovery time
tMRD
Mode Register Set command cycle time
tMOD
Mode Register Set command update delay
tCCD
CAS# to CAS# command delay
tDAL(min)
tMPRR
15
nS
4
nCK
max(12nCK, 15nS)
WR + roundup(tRP(min)/ tCK(avg))
Multi-Purpose Register Recovery Time
tRRD
ACTIVE to ACTIVE command period for 1KB page
size
tFAW
Four activate window for 1KB page size
8, 26
4
Auto precharge write recovery + precharge time
nCK
1
max(4nCK, 5nS)
27
nCK
nCK
6
nCK
29
8
nS
8
Command and Address
tIS(AC135)
setup time to CK, CK#
Base specification
65
pS
9, 41
VREF @ 1 V/nS
200
pS
9, 41, 42
tIS(AC125)
Command and Address
setup time to CK, CK#
Base specification
150
pS
9, 41
VREF @ 1 V/nS
275
pS
9, 41, 42
tIH(DC100)
Command and Address
hold time from CK, CK#
Base specification
100
pS
9, 41
VREF @ 1 V/nS
200
pS
9, 41, 42
pS
10
tIPW
Control and Address input pulse width for each
input
535
Calibration Timing
tZQinit
Power-up and RESET calibration time
max(512nCK, 640nS)
tZQoper
Normal operation Full calibration time
max(256nCK, 320nS)
max(64nCK, 80nS)
max(5nCK, 170nS)
max(5nCK, 170nS)
tZQCS
Normal operation Short calibration time
33
Reset Timing
tXPR
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
tXS
Exit Self Refresh to commands not requiring a
locked DLL
tXSDLL
Exit Self Refresh to commands requiring a locked
DLL
tDLLK(min)
tCKESR
Minimum CKE low width for Self Refresh entry to
exit timing
tCKE(min) + 1nCK
tCKSRE
Valid Clock Requirement after Self Refresh Entry
(SRE)
max(5 nCK, 10nS)
tCKSRX
Valid Clock Requirement before Self Refresh Exit
(SRX)
max(5 nCK, 10nS)
160
0°C ≤ TCASE ≤ 85°C
85°C < TCASE ≤ 95°C
34
nCK
35
nS
36
7.8
μS
3.9
μS
Refresh Timing
tRFC
REF command to ACT or REF command time
tREFI
Average periodic
refresh Interval
Publication Release Date: Dec. 08, 2014
Revision: A04
- 140 -
W632GG8KB
AC Timing and Operating Condition for -11 speed grade, continued
SPEED GRADE
SYMBOL
DDR3-1866 (-11)
PARAMETER
UNITS NOTES
MIN.
MAX.
max(3nCK, 6nS)
34
max(10nCK, 24nS)
35
max(3nCK, 5nS)
Power Down Timing
tXP
tXPDLL
tCKE
tCPDED
tPD
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
tACTPDEN Timing of ACT command to Power Down entry
2
tCKE(min)
9 * tREFI
1
nCK
27
1
nCK
27
RL + 4 + 1
nCK
nCK
25
tPRPDEN
Timing of PRE or PREA command to Power Down
entry
tRDPDEN
Timing of RD/RDA command to Power Down entry
tWRPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + roundup (tWR(min)/ tCK(avg))
Max.:
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 +
Max.:
nCK
19
tWRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
Min.: WL + 2 + roundup (tWR(min)/ tCK(avg))
Max.:
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
Min.: WL + 2 +
Max.:
nCK
19
nCK
27, 28
WR + 1
WR + 1
tREFPDEN Timing of REF command to Power Down entry
1
tMRSPDEN Timing of MRS command to Power Down entry
tMOD(min)
ODT Timing
ODTH4
ODT high time without write command or with write
command and burst chop 4
4
nCK
30
ODTH8
ODT high time with Write command and burst
length 8
6
nCK
31
tAONPD
Asynchronous RTT turn-on delay (Power Down
with DLL frozen)
2
8.5
nS
32
tAOFPD
Asynchronous RTT turn-off delay (Power Down
with DLL frozen)
2
8.5
nS
32
-195
195
pS
17, 43
tAON
RTT turn-on
tAOF
Rtt_Nom and Rtt_WR turn-off time from ODTLoff
reference
0.3
0.7
tCK(avg) 17, 44
tADC
RTT dynamic change skew
0.3
0.7
tCK(avg)
17
First DQS/DQS# rising edge after write leveling
mode is programmed
40
nCK
5
tWLDQSEN
DQS/DQS# delay after write leveling mode is
programmed
25
nCK
5
tWLS
Write leveling setup time from (CK, CK#) zero
crossing to rising (DQS, DQS#) zero crossing
140
pS
tWLH
Write leveling hold time from rising (DQS, DQS#)
zero crossing to (CK, CK#) zero crossing
140
pS
tWLO
Write leveling output delay
0
7.5
nS
tWLOE
Write leveling output error
0
2
nS
Write Leveling Timing
tWLMRD
Publication Release Date: Dec. 08, 2014
Revision: A04
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W632GG8KB
10.16.2 AC Timing and Operating Condition for -12/12I/-15/15I speed grades
SPEED GRADE
SYMBOL
PARAMETER
DDR3-1600
(-12/12I)
MIN.
DDR3-1333
(-15/15I)
MAX.
MIN.
UNITS
NOTES
MAX.
Common Notes
1, 2, 3, 4
Clock Input Timing
tCK(DLL-off) Minimum clock cycle time (DLL-off mode)
tCK(avg)
Average Clock Period
tCH(avg)
Average CK/CK# high pulse width
tCL(avg)
Average CK/CK# low pulse width
0.47
0.53
tCK(avg)
0.47
0.53
0.47
0.53
tCK(avg)
Min.: tCK(avg)min + tJIT(per)min
Max.: tCK(avg)max + tJIT(per)max
Absolute CK/CK# high pulse width
0.43
tCL(abs)
Absolute CK/CK# low pulse width
tJIT(per)
Clock Period Jitter
tJIT(duty)
pS
37
tCK(avg)
38
39
0.43
0.43
0.43
tCK(avg)
-70
70
-80
80
pS
-60
60
-70
70
pS
Cycle to Cycle Period Jitter
140
160
pS
Cycle to Cycle Period Jitter during DLL locking
period
120
140
pS
Clock Duty Cycle Jitter
Already included in tCH(abs) and tCL(abs)
pS
tERR(2per)
Cumulative error across 2 cycles
-103
103
-118
118
pS
tERR(3per)
Cumulative error across 3 cycles
-122
122
-140
140
pS
tERR(4per)
Cumulative error across 4 cycles
-136
136
-155
155
pS
tERR(5per)
Cumulative error across 5 cycles
-147
147
-168
168
pS
tERR(6per)
Cumulative error across 6 cycles
-155
155
-177
177
pS
tERR(7per)
Cumulative error across 7 cycles
-163
163
-186
186
pS
tERR(8per)
Cumulative error across 8 cycles
-169
169
-193
193
pS
tERR(9per)
Cumulative error across 9 cycles
-175
175
-200
200
pS
tERR(10per) Cumulative error across 10 cycles
-180
180
-205
205
pS
tERR(11per) Cumulative error across 11 cycles
-184
184
-210
210
pS
tERR(12per) Cumulative error across 12 cycles
-188
188
-215
215
pS
tERR(nper)
Cumulative error across n = 13, 14...49, 50
cycles
Min.: tJIT(per)min * (1 + 0.68 * ln(n))
Max.: tJIT(per)max * (1 + 0.68 * ln(n))
45
pS
0.53
tCH(abs)
tJIT(cc,lck)
See “Speed Bin” on
page 134
nS
0.47
Absolute Clock Period
tJIT(cc)
8
See “Speed Bin” on
page 135
tCK(abs)
tJIT(per,lck) Clock Period Jitter during DLL locking period
8
pS
7
Publication Release Date: Dec. 08, 2014
Revision: A04
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W632GG8KB
AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued
DDR3-1600
(-12/12I)
SPEED GRADE
SYMBOL
DDR3-1333
(-15/15I)
UNITS
NOTES
125
pS
23
PARAMETER
MIN.
MAX.
MIN.
MAX.
DQS, DQS# to DQ skew, per group, per access
100
Data Timing
tDQSQ
tQH
DQ output hold time from DQS, DQS#
0.38
0.38
tCK(avg)
18, 23
tLZ(DQ)
DQ low impedance time from CK, CK#
-450
225
-500
250
pS
17, 23, 24
tHZ(DQ)
DQ high impedance time from CK, CK#
225
250
pS
17, 23, 24
tDS(AC150)
Data setup time to
DQS, DQS#
Base specification
10
30
VREF @ 1 V/nS
160
180
tDH(DC100)
Data hold time from
DQS, DQS#
Base specification
45
65
VREF @ 1 V/nS
145
165
tDIPW
DQ and DM input pulse width for each input
pS
11, 40
11, 40, 42
pS
11, 40
11, 40, 42
360
400
pS
10
Data Strobe Timing
tRPRE
DQS,DQS# differential READ Preamble
0.9
Note 21
0.9
Note 21
tCK(avg) 18, 21, 23
tRPST
DQS,DQS# differential READ Postamble
0.3
Note 22
0.3
Note 22
tCK(avg) 18, 22, 23
tQSH
DQS,DQS# differential output high time
0.4
0.4
tCK(avg)
18, 23
tQSL
DQS,DQS# differential output low time
0.4
0.4
tCK(avg)
18, 23
tWPRE
DQS,DQS# differential WRITE Preamble
0.9
0.9
tCK(avg)
46
tWPST
DQS,DQS# differential WRITE Postamble
0.3
0.3
tCK(avg)
46
tDQSCK
DQS,DQS# rising edge output access time from
rising CK, CK#
-225
225
-255
255
pS
17, 23
tLZ(DQS)
DQS and DQS# low-impedance time from
CK, CK# (Referenced from RL - 1)
-450
225
-500
250
pS
17, 23, 24
tHZ(DQS)
DQS and DQS# high-impedance time from
CK, CK# (Referenced from RL + BL/2)
225
250
pS
17, 23, 24
tDQSL
DQS,DQS# differential input low pulse width
0.45
0.55
0.45
0.55
tCK(avg)
12, 14
tDQSH
DQS,DQS# differential input high pulse width
0.45
0.55
0.45
0.55
tCK(avg)
13, 14
tDQSS
DQS,DQS# rising edge to CK,CK# rising edge
-0.27
0.27
-0.25
0.25
tCK(avg)
16
tDSS
DQS,DQS# falling edge setup time to CK,CK#
rising edge
0.18
0.2
tCK(avg)
15, 16
tDSH
DQS,DQS# falling edge hold time from CK,CK#
rising edge
0.18
0.2
tCK(avg)
15, 16
nS
8
nS
8
nS
8
Command and Address Timing
tAA
tRCD
Internal read command to first data
ACT to internal read or write delay time
tRP
PRE command period
See “Speed Bin” on
page 135
See “Speed Bin” on
page 134
tRC
ACT to ACT or REF command period
nS
8
tRAS
ACT to PRE command period
nS
8
tDLLK
DLL locking time
tRTP
Internal READ Command to PRECHARGE
Command delay
max(4nCK,
7.5nS)
tWTR
Delay from start of internal write transaction to
internal read command
max(4nCK,
7.5nS)
512
512
nCK
max(4nCK,
7.5nS)
8
max(4nCK,
7.5nS)
8, 26
Publication Release Date: Dec. 08, 2014
Revision: A04
- 143 -
W632GG8KB
AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued
SPEED GRADE
SYMBOL
PARAMETER
DDR3-1600
(-12/12I)
MIN.
DDR3-1333
(-15/15I)
MAX.
MIN.
UNITS NOTES
MAX.
Command and Address Timing
tWR
WRITE recovery time
15
15
nS
tMRD
Mode Register Set command cycle time
4
4
nCK
tMOD
Mode Register Set command update delay
tCCD
CAS# to CAS# command delay
max(12nCK,
15nS)
tMPRR
Multi-Purpose Register Recovery Time
tRRD
ACTIVE to ACTIVE command period for 1KB
page size
tFAW
Four activate window for 1KB page size
4
Auto precharge write recovery + precharge
tDAL(min)
time
max(12nCK,
15nS)
4
8, 26
WR + roundup(tRP(min)/ tCK(avg))
1
1
max(4nCK,
6nS)
max(4nCK,
6nS)
30
30
nCK
nCK
6
nCK
29
8
nS
8
Command and Address
tIS(AC175)
setup time to CK, CK#
Base specification
45
65
pS
9, 41
VREF @ 1 V/nS
220
240
pS
9, 41, 42
Command and Address
tIS(AC150)
setup time to CK, CK#
Base specification
170
190
pS
9, 41
VREF @ 1 V/nS
320
340
pS
9, 41, 42
Command and Address
hold time from CK, CK#
Base specification
120
140
pS
9, 41
VREF @ 1 V/nS
220
240
pS
9, 41, 42
pS
10
tIH(DC100)
tIPW
Control, address and control input pulse width
for each input
560
620
Calibration Timing
tZQinit
Power-up and RESET calibration time
max(512nCK,
640nS)
max(512nCK,
640nS)
tZQoper
Normal operation Full calibration time
max(256nCK,
320nS)
max(256nCK,
320nS)
Normal operation Short calibration time
max(64nCK,
80nS)
max(64nCK,
80nS)
max(5nCK,
170nS)
max(5nCK,
170nS)
Exit Self Refresh to commands not requiring a
locked DLL
max(5nCK,
170nS)
max(5nCK,
170nS)
tXSDLL
Exit Self Refresh to commands requiring a
locked DLL
tDLLK(min)
tDLLK(min)
tCKESR
Minimum CKE low width for Self Refresh entry
to exit timing
tCKE(min) +
1nCK
tCKE(min) +
1nCK
tCKSRE
Valid Clock Requirement after Self Refresh
Entry (SRE)
max(5 nCK,
10nS)
max(5 nCK,
10nS)
tCKSRX
Valid Clock Requirement before Self Refresh
Exit (SRX)
max(5 nCK,
10nS)
max(5 nCK,
10nS)
tZQCS
33
Reset Timing
tXPR
Exit Reset from CKE HIGH to a valid
command
Self Refresh Timing
tXS
34
nCK
35
36
Refresh Timing
tRFC
tREFI
160
160
nS
-40°C ≤ TCASE ≤ 85°C*
7.8
7.8
μS
0°C ≤ TCASE ≤ 85°C
7.8
7.8
μS
85°C < TCASE ≤ 95°C
3.9
3.9
μS
REF command to ACT or REF command time
Average periodic
refresh Interval
* -40°C ≤ TCASE ≤ 85°C is for 12I/15I grade only.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 144 -
W632GG8KB
AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued
DDR3-1600
(-12/12I)
SPEED GRADE
SYMBOL
PARAMETER
DDR3-1333
(-15/15I)
UNITS NOTES
MIN.
MAX.
MIN.
MAX.
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3nCK,
6nS)
max(3nCK,
6nS)
34
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK,
24nS)
max(10nCK,
24nS)
35
CKE minimum pulse width
max(3nCK,
5nS)
max(3nCK,
5.625nS)
1
1
tCKE(min)
9 * tREFI
tCKE(min)
9 * tREFI
1
1
nCK
27
1
1
nCK
27
RL + 4 + 1
RL + 4 + 1
nCK
Power Down Timing
tXP
tXPDLL
tCKE
tCPDED
tPD
Command pass disable delay
Power Down Entry to Exit Timing
tACTPDEN Timing of ACT command to Power Down entry
tPRPDEN
Timing of PRE or PREA command to Power Down
entry
tRDPDEN
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
tWRPDEN
(BL8OTF, BL8MRS, BC4OTF)
nCK
25
Min.: WL + 4 + roundup (tWR(min)/ tCK(avg))
Max.:
nCK
20
nCK
19
tWRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 +
Max.:
WR + 1
tWRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
Min.: WL + 2 + roundup (tWR(min)/ tCK(avg))
Max.:
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
Min.: WL + 2 +
Max.:
nCK
19
nCK
27, 28
WR + 1
tREFPDEN Timing of REF command to Power Down entry
1
1
tMRSPDEN Timing of MRS command to Power Down entry
tMOD(min)
tMOD(min)
ODT Timing
ODTH4
ODT high time without write command or with write
command and burst chop 4
4
4
nCK
30
ODTH8
ODT high time with Write command and burst
length 8
6
6
nCK
31
tAONPD
Asynchronous RTT turn-on delay (Power Down
with DLL frozen)
2
8.5
2
8.5
nS
32
tAOFPD
Asynchronous RTT turn-off delay (Power Down
with DLL frozen)
2
8.5
2
8.5
nS
32
tAON
RTT turn-on
-225
225
-250
250
pS
17, 43
tAOF
Rtt_Nom and Rtt_WR turn-off time from ODTLoff
reference
0.3
0.7
0.3
0.7
tCK(avg)
17, 44
tADC
RTT dynamic change skew
0.3
0.7
0.3
0.7
tCK(avg)
17
First DQS/DQS# rising edge after write leveling
mode is programmed
40
40
nCK
5
tWLDQSEN
DQS/DQS# delay after write leveling mode is
programmed
25
25
nCK
5
tWLS
Write leveling setup time from (CK, CK#) zero
crossing to rising (DQS, DQS#) zero crossing
165
195
pS
tWLH
Write leveling hold time from rising (DQS, DQS#)
zero crossing to (CK, CK#) zero crossing
165
195
pS
tWLO
Write leveling output delay
0
7.5
0
9
nS
tWLOE
Write leveling output error
0
2
0
2
nS
Write Leveling Timing
tWLMRD
Publication Release Date: Dec. 08, 2014
Revision: A04
- 145 -
W632GG8KB
10.16.3 Timing Parameter Notes
1. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents
one clock cycle of the input clock, counting the actual clock edges.
For example, tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another
Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) +
tERR(4per),min (which is smaller than 4 x tCK(avg)).
2. Timing that is not specified is illegal and after such an event, in order to provide proper operation, the
DRAM must be resetted or powered down and then restarted through the specified initialization
sequence before normal operation can continue.
3. The CK/CK# input reference level (for timing reference to CK / CK#) is the point at which CK and CK#
cross.
The DQS/DQS# input reference level is the point at which DQS and DQS# cross;
The input reference level for signals other than CK/CK#, DQS/DQS# and RESET# is VREFCA and
VREFDQ respectively.
4. Inputs are not recognized as valid until VREFCA stabilizes within specified limits.
5. The max values are system dependent.
6. tCK(avg) refers to the actual application clock period. WR refers to the WR parameter stored in mode
register MR0.
7. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
8. For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [nS] / tCK(avg)
[nS] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock
jitter specifications are met. This means: For DDR3-1333 (9-9-9), of which tRP = 13.5nS, the device will
support tnRP = RU{tRP / tCK(avg)} = 9, as long as the input clock jitter specifications are met, i.e.
Precharge command at Tm and Active command at Tm+9 is valid even if (Tm+9 - Tm) is less than
13.5nS due to input clock jitter.
9. These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#, ODT,
BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec values are
not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are
relative to the clock signal crossing that latches the command/address. That is, these parameters
should be met whether clock jitter is present or not.
10.Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the
consecutive crossing of VREF(DC).
11.These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its
respective data strobe signal (DQS, DQS#) crossing.
12.tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from
one falling edge to the next consecutive rising edge.
13.tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured
from one rising edge to the next consecutive falling edge.
14.tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
15.tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
16.These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock
signal (CK, CK#) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters
should be met whether clock jitter is present or not.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 146 -
W632GG8KB
17.When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(mper),act of the input clock, where 2 VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV
Alternate DC100 Threshold -> VIH(DC)=VREF(DC)+100mV, VIL(DC)=VREF(DC)-100mV
DQS, DQS# Differential Slew Rate
6.0 V/nS 5.0 V/nS 4.0 V/nS 3.0 V/nS 2.0 V/nS 1.8 V/nS 1.6 V/nS 1.4 V/nS
1.2 V/nS
1.0 V/nS
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
4.0
3.5
3.0
2.5
34
29
23
-
25
21
17
-
34
29
23
14
25
21
17
10
34
29
23
14
25
21
17
10
29
23
14
21
17
10
23
14
17
10
14
10
-
-
2.0
-
-
-
-
0
0
0
0
0
0
0
0
0
0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
-
-
-
-
-
-
-23
-
-17
-
-23
-68
-
-17
-50
-
-23
-68
-66
-
-17
-50
-54
-
-23
-68
-66
-64
-
-17
-50
-54
-60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-15
-60
-58
-56
-53
-
-9
-42
-46
-52
-59
-
-52
-50
-48
-45
-43
-
-34
-38
-44
-51
-61
-
-42
-40
-37
-35
-39
-
-30
-36
-43
-53
-66
-
-32
-29
-27
-31
-38
-26
-33
-43
-56
-76
-21
-19
-23
-30
-17
-27
-40
-60
Note: Cell contents ‘-’ are defined as not supported.
Table 58 – Required time tVAC above VIH(AC) {below VIL(AC)} for valid DQ transition
Slew Rate [V/nS]
> 2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
< 0.5
DDR3-1333/1600 (AC150)
tVAC [pS]
Min.
Max.
Min.
Max.
105
105
80
30
13
Note
Note
Note
Note
Note
93
93
70
25
Note
Note
-
-
-
DDR3-1866 (AC135)
tVAC [pS]
Note: Rising input signal shall become equal to or greater than VIH(AC) level and Falling input signal shall become equal to or less than
VIL(AC) level.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 157 -
W632GG8KB
11. PACKAGE SPECIFICATION
Package Outline WBGA78 (8x10.5 mm2, Ball pitch: 0.8mm, Ø =0.45mm)
aaa C 4X
//
E1
bbb C
B
A
eE
E
A1
9
8
7 6
5
4 3
2
1
Pin A1 index
A
Pin A1 index
A
B
eD
C
D
E
F
G
D1
D
H
J
K
L
M
N
THE WINDOW-SIDE
ENCAPSULANT
78xΦb
ccc C
C
SOLDER BALL DIAMETER REFERS.
TO POST REFLOW CONDITION.
ddd
eee
M
M
SYMBOL
A
A1
b
D
E
D1
E1
eE
eD
aaa
bbb
ccc
ddd
eee
C A B
C
Dimension in mm
MIN.
NOM.
MAX.
----1.20
0.40
0.25
--0.40
0.45
0.50
10.60
10.40
10.50
8.10
7.90
8.00
9.60 BSC.
6.40 BSC.
0.80 BSC.
0.80 BSC.
----0.15
--0.20
------0.10
----0.15
----0.08
Dimension in inch
MIN.
NOM.
MAX.
----0.0472
--0.0098
0.0157
--0.0157
0.0197
0.4094 0.4134 0.4173
0.3110 0.3150 0.3189
0.3780 BSC.
0.2519 BSC.
0.0315 BSC.
0.0315 BSC.
--0.0059
----0.0780
------0.0039
0.0059
--------0.0031
Ball Land
1
Ball Opening
Note:
1. Ball land: 0.5mm, Ball opening: 0.4mm, PCB Ball land
suggested ≤ 0.4mm
Publication Release Date: Dec. 08, 2014
Revision: A04
- 158 -
W632GG8KB
12. REVISION HISTORY
VERSION
DATE
PAGE
A01
May 22, 2013
All
Initial formally datasheet
11
Added block diagram
A02
Dec. 24, 2013
A03
Oct. 15, 2014
5~7, 98, 122,
132, 134, 135,
142~145
A04
Dec. 08, 2014
6, 98
7, 134, 135,
137
DESCRIPTION
Added CL = 7, CWL = 6 support for DDR3-1600
and DDR3 1333 speed bins
Removed 12A, 12K, 15A and 15K automotive
grade parts
Commercial operating temperature range change
from 0°C ≤ TCASE ≤ 85°C to 0°C ≤ TCASE ≤ 95°C
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Publication Release Date: Dec. 08, 2014
Revision: A04
- 159 -
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