W641GG2JB-14

W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Table of Contents 1. GENERAL DESCRIPTION .......................................................................................................... 6 2. FEATURES .................................................................................................................................. 7 3. PIN CONFIGURATION ................................................................................................................ 8 3.1 Ballout 1-CS Non-Merged Mode (Top View, MF=0) ............................................................................. 8 3.2 Ballout 2-CS Non-Merged Mode (Top View, MF=0) ............................................................................. 9 3.3 Ballout Merged Mode (Top View, MF=0) ........................................................................................... 10 4. PIN DESCRIPTION .................................................................................................................... 11 4.1 Signal Description.............................................................................................................................. 11 4.2 Addressing ........................................................................................................................................ 12 5. STATE DIAGRAM ..................................................................................................................... 13 5.1 State Diagram for One Activated Bank ............................................................................................... 13 5.1.1 State diagram for one bank ............................................................................................................................. 13 5.1.2 Function Truth Table for more than one Activated Bank .................................................................................. 14 5.1.2.1 Function Truth Table ...................................................................................................................................................14 5.1.3 Function Truth Table for CKE .......................................................................................................................... 15 5.2 Functional Block Diagram in 1-CS Mode ........................................................................................... 16 5.3 Functional Block Diagram in 2-CS Mode ........................................................................................... 17 6. FUNCTIONAL DESCRIPTION ................................................................................................... 18 6.1 System Configurations....................................................................................................................... 18 6.1.1 System Configurations in 1-CS Mode and 2-CS Mode ................................................................................... 18 6.1.2 Initialization in 1– CS mode ............................................................................................................................. 19 6.1.3 Initialization in 2– CS mode ............................................................................................................................. 20 6.1.3.1 Power Up Sequence ...................................................................................................................................................21 .2 Mirror Function .................................................................................................................................... 22 6.2.1 Ball Assignment with Mirror Function .............................................................................................................. 22 6.3 Commands ........................................................................................................................................ 23 6.3.1 Command Overview for 1-CS mode ................................................................................................................ 23 6.3.2 Command Overview for 2-CS mode ................................................................................................................ 24 6.3.3 Description of Command ................................................................................................................................. 25 6.3.4 Minimum delay from RD/A and W R/A to any other command (to another bank) with concurrent AP ............. 28 6.4 Boundary Scan .................................................................................................................................. 28 6.4.1 General Description ......................................................................................................................................... 28 6.4.2 Disabling the scan feature ............................................................................................................................... 28 6.4.2.1 Internal Block Diagram (Reference only) ....................................................................................................................29 6.4.2.2 Boundary Scan Exit Order ...........................................................................................................................................29 6.4.2.3 Scan Pin Description ...................................................................................................................................................30 6.4.2.4 Scan DC Electrical Characteristics and Operating Condition .......................................................................................30 6.4.2.5 Scan Capture Timing ...................................................................................................................................................31 -1- Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.4.2.6 Scan Shift Timing ........................................................................................................................................................31 6.4.2.7 Scan AC Electrical Characteristic ................................................................................................................................32 6.4.3 Scan Initialization ............................................................................................................................................. 32 6.4.3.1 Scan Initialization for Stand-Alone Mode .....................................................................................................................32 6.4.3.2 Scan Initialization for Stand-Alone mode ....................................................................................................................33 6.4.4 Scan Initialization in regular SGRAM operation ............................................................................................... 33 6.4.4.1 Scan Initialization Sequence within regular SGRAM Mode .........................................................................................34 6.4.5 Scan Exit Sequence ........................................................................................................................................ 35 6.4.5.1 Boundary Scan Exit Sequence ...................................................................................................................................35 6.4.5.2 Scan AC Electrical Parameter .....................................................................................................................................35 6.5 Programmable impedance output drivers and active terminations ...................................................... 36 6.5.1 GDDR3 IO Driver and Termination .................................................................................................................. 36 6.5.1.1 Output Deiver simplified schematic .............................................................................................................................37 6.5.1.2 Range of external resistance ZQ .................................................................................................................................37 6.5.1.3 Termination Types and Activation ...............................................................................................................................37 6.5.2 Self Calibration for Driver and Termination ...................................................................................................... 38 6.5.2.1 Termination update Keep Out time after Autorefresh command .................................................................................38 6.5.2.2 Number of Legs used for Terminator and Driver Self Calibration ................................................................................39 6.5.2.3 Self Calibration of PMOS and NMOS Legs .................................................................................................................39 6.5.3 Dynamic Switching of DQ terminations ............................................................................................................ 40 6.5.3.1 ODT Disable Timing during a READ command ..........................................................................................................40 6.5.4 Output impedance and Term ination DC Electrical Characteristics .................................................................. 41 6.5.4.1 DC Electrical Characteristic .........................................................................................................................................41 6.6 Mode Register Set Command (MRS) ................................................................................................. 42 6.6.1 Mode Register Set Command ......................................................................................................................... 42 6.6.2 Mode Registers................................................................................................................................................ 42 6.6.2.1 Mode Register (MRS) .................................................................................................................................................42 6.6.2.2 Mode Register (MRS) .................................................................................................................................................43 6.6.2.3 Mode Register Set Timing...........................................................................................................................................43 6.6.3 Burst Length and Burst Type ........................................................................................................................... 44 6.6.3.1 Burst Length................................................................................................................................................................44 6.6.3.2 Burst type ....................................................................................................................................................................44 6.6.4 CAS Latency .................................................................................................................................................... 44 6.6.5 W rite Latency ................................................................................................................................................... 44 6.6.6 DLL Reset ........................................................................................................................................................ 45 6.6.7 Test mode ........................................................................................................................................................ 45 6.7 Extended Mode Register Set Command (EMRS1) ............................................................................. 45 6.7.1 Extended Mode Register Set Command ......................................................................................................... 46 6.7.2 Extended Mode Register 1 (EMRS1) .............................................................................................................. 46 6.7.2.1 Extended Mode Register 1 (EMRS1) ..........................................................................................................................47 6.7.2.2 Extended Mode Register Set Timing ..........................................................................................................................48 6.7.3 Chip Select Mode ............................................................................................................................................ 48 6.7.4 DLL .................................................................................................................................................................. 48 6.7.5 W rite Recovery ................................................................................................................................................ 48 Publication Release Date: Apr, 22, 2011 Revision A01-002 -2- W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.7.6 Termination Rtt ................................................................................................................................................ 48 6.7.7 Impedance Autocalibration of Output Buffer and Active Terminator ............................................................... 49 6.7.7.1 Impedance Options .....................................................................................................................................................49 6.7.7.2 Timing of Vendor Code and Revision ID Generation on DQ[7:0] ................................................................................49 6.7.8 Output Driver Impedance ................................................................................................................................. 50 6.7.9 Data Termination ............................................................................................................................................. 50 6.7.10 Address command termination ...................................................................................................................... 50 6.8 Extended Mode Register 2 Set Command (EMRS2) .......................................................................... 50 6.8.1 Extended Mode Register 2 Set Command ...................................................................................................... 51 6.8.2 Extended Mode Register 2 (EMRS2) .............................................................................................................. 51 6.8.2.1 Extended Mode Register 2 (EMRS2) ..........................................................................................................................52 6.8.2.2 Impedance Offsets ......................................................................................................................................................52 6.8.2.3 Merged Mode ..............................................................................................................................................................52 6.8.3 OCD Pull Down Offset ..................................................................................................................................... 52 6.8.4 ODT Pull Up Offset .......................................................................................................................................... 52 6.9 Extended Mode Register 3 (EMRS3) ................................................................................................. 53 6.10 Vendor Code and Revision ID .......................................................................................................... 53 6.10.1 Vendor ID Code ............................................................................................................................................. 53 6.11 Bank / Row Activation (ACT) ............................................................................................................ 54 6.11.1 Activating a specific row ................................................................................................................................ 54 6.11.2 Bank Activation Timing .................................................................................................................................. 55 6.11.3 Bank Activation Timing on different rank in 2-CS mode ................................................................................ 55 6.11.4 Four Window Active tFAW ............................................................................................................................. 55 6.11.5 Clock, CKE and command / Address Timings .............................................................................................. 56 6.12 Bank Activations with REFRESH ..................................................................................................... 56 6.12.1 Bank Activations with REFRESH Command ................................................................................................. 56 6.13 Writes (WR) ..................................................................................................................................... 57 6.13.1 W rite - Basic Information ............................................................................................................................... 57 6.13.1.1 Write Command ........................................................................................................................................................58 6.13.1.2 Mapping of W DQS and DM Signals ..........................................................................................................................58 6.13.1.3 Basic Write Burst / DM Timing ..................................................................................................................................59 6.14 Write - Basic Sequence ................................................................................................................... 60 6.15 Write - Consecutive Bursts ............................................................................................................... 61 6.15.1Gapless Bursts................................................................................................................................................ 61 6.15.1.1 Gapless Write Bursts ................................................................................................................................................61 6.15.2 Bursts with Gaps ............................................................................................................................................ 62 6.15.2.1 Consecutive Write Bursts with Gaps .........................................................................................................................62 6.15.3 W rite with Autoprecharge .............................................................................................................................. 63 6.15.4 W rite followed by Read .................................................................................................................................. 64 6.15.5 W rite followed by Read on different ranks in 2-CS mode............................................................................... 65 6.15.6 W rite followed by DTERDIS ........................................................................................................................... 66 6.15.7 W rite with Autoprecharge followed by Read / Read with Autoprecharge on another bank ........................... 67 6.15.8 W rite followed by Precharge on same bank ................................................................................................... 68 Publication Release Date: Apr, 22, 2011 Revision A01-002 -3- W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16 Reads (RD)...................................................................................................................................... 69 6.16.1 Read - Basic Information ............................................................................................................................... 69 6.16.1.1 Read Command ........................................................................................................................................................70 6.16.1.2 Basic Read Burst Timing...........................................................................................................................................71 6.16.2 Read - Basic Sequence ................................................................................................................................. 72 6.16.2.1 Read Burst ................................................................................................................................................................72 6.16.3 Consecutive Read Bursts .............................................................................................................................. 73 6.16.3.1 Gapless Bursts ..........................................................................................................................................................73 6.16.4 Bursts with Gaps ............................................................................................................................................ 74 6.16.4.1 Consecutive Read Bursts with Gaps .........................................................................................................................74 6.16.5 Read followed by DTERDIS........................................................................................................................... 75 6.16.6 Read with Autoprecharge .............................................................................................................................. 76 6.16.7 Read followed by W rite .................................................................................................................................. 77 6.16.8 Read followed by Precharge on the same Bank ............................................................................................ 78 6.17 Data Termination Disable (DTERDIS) .............................................................................................. 79 6.17.1 Data Terminal Disable Command ................................................................................................................. 79 617.1.1 DTERDIS Timing .......................................................................................................................................................80 6.17.2 DTERDIS followed by DTERDIS ................................................................................................................... 81 6.17.3 DTERDIS followed by READ ......................................................................................................................... 82 6.17.4 DTERDIS followed by W rite ........................................................................................................................... 83 6.18 Precharge (PRE/PREALL) ............................................................................................................... 84 6.18.1 Precharge Command .................................................................................................................................... 84 6.18.2 BA2, BA1 and BA0 precharge bank selection within one rank ...................................................................... 85 6.18.3 Precharge Timing .......................................................................................................................................... 85 6.19 Auto Refresh Command (AREF) ...................................................................................................... 86 6.19.1 Auto Refresh Command ................................................................................................................................ 86 6.19.2 Auto Refresh Cycle ........................................................................................................................................ 87 6.20 Self-Refresh .................................................................................................................................... 87 6.20.1 Self-Refresh Entry (SREFEN) ........................................................................................................................ 87 6.20.1.1 Self-Refresh Entry Command ...................................................................................................................................88 6.20.1.2 Self Refresh Entry .....................................................................................................................................................89 6.21 Self-Refresh Exit (SREFEX)............................................................................................................. 89 6.21.1 Self Refresh Exit Command .......................................................................................................................... 90 6.21.2 Self Refresh Exit ............................................................................................................................................ 90 6.22 Power-Down .................................................................................................................................... 91 6.22.1 Power Down Command ................................................................................................................................. 91 6.22.2 Power-Down Mode ........................................................................................................................................ 92 7 ELECTRICAL CHARACTERISTICS ........................................................................................... 93 7.1 Absolute Maximum Ratings and Operation Conditions ....................................................................... 93 7.1.1 Absolute Maxim um Rating ............................................................................................................................... 93 7.2 DC Operation Conditions ................................................................................................................... 93 7.2.1 Recommended Power & DC Operation Conditions ......................................................................................... 93 -4- Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.2.1.1 Power & DC Operation Conditions (0 °C ≤ Tc ≤ 105 °C) ............................................................................................93 7.3 DC & AC Logic Input Levels ............................................................................................................... 94 7.3.1 DC & AC Logic Input Levels (0 °C ≤ Tc ≤ 105 °C) .......................................................................................... 94 7.4 Differential Clock DC and AC Levels .................................................................................................. 95 7.4.1 Differential Clock DC and AC Input conditions (0 °C ≤ Tc ≤ 105°C) ............................................................... 95 7.5 Output Test Conditions ...................................................................................................................... 95 7.6 Pin Capacitances............................................................................................................................... 96 7.6.1 Pin Capacitances (VDDQ = 1.8 V, TA = 25°C, f = 1 MHz) .............................................................................. 96 7.7 Driver current characteristics ............................................................................................................. 96 7.7.1 Driver IV characteristics at 40 Ohms................................................................................................................ 96 7.7.1.1 40 Ohm Driver Pull-Down and Pull-up Characteristics ................................................................................................96 7.7.1.2 Programmed Driver IV Characteristics at 40 Ohm .......................................................................................................97 7.8 Termination current characteristics .................................................................................................... 97 7.8.1 Termination IV Characteristic at 60 Ohms ....................................................................................................... 97 7.8.1.1 60 Ohm Active Termination Characteristic ..................................................................................................................98 7.8.1.2 Programmed Terminator Characteristics at 60 Ohm....................................................................................................98 7.8.2 Termination IV Characteristic at 120 Ohms ..................................................................................................... 99 7.8.2.1 120 Ohm Active Termination Characteristic ................................................................................................................99 7.8.2.2 Programmed Terminator Characteristics of 120 Ohm ................................................................................................100 7.8.3 Termination IV Characteristic at 240 Ohms ................................................................................................... 100 7.8.3.1 240 Ohm Active Termination Characteristic ..............................................................................................................100 7.8.3.2 Programmed Terminator Characteristics at 240 Ohm ...............................................................................................101 7.9 Operating Current Ratings ............................................................................................................... 102 7.10 AC Timings .................................................................................................................................... 103 8. PACKAGE SPECIFICATION ................................................................................................... 106 9. ORDERING INFORMATION .................................................................................................... 107 10. REVISION HISTORY ............................................................................................................. 108 -5- Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 1. GENERAL DESCRIPTION The W 641GG2JB 1-Gbit GDDR3 GRAPHICS SDRAM is a high speed dynamic random-access memory designed for applications requiring high bandwidth. It contains 1,073,741,824 bits. The device can be configured to operate in two different modes: • in 2-CS mode the chip is organized as two 512 Mbit memories of 8 banks each, with 4096 row locations and 512 column locations per bank. • in 1-CS mode the chip is organized as one 1 Gbit memory, with 8192 row locations and 512 column locations per bank. The GDDR3 GRAPHICS SDRAM uses a double data rate architecture to achieve high speed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the GDDR3 GRAPHICS SDRAM effectively consists of a 4n data transfer every two clock cycles at the internal DRAM core and four corresponding n-bit wide, one-half-clockcycle data transfers at the I/O pins. Unidirectional data strobes are transmitted externally, along with data, for use in data capture at the receiver. RDQS is a strobe transmitted by the GDDR3 GRAPHICS SDRAM during READs. W DQS is the data strobe sent by the memory controller during W RITEs. RDQS is edge-aligned with data for READs and W DQS is center-aligned with data for W RITEs. The GDDR3 GRAPHICS SDRAM operates from a differential clock (CLK and CLK#; the crossing of CLK going High and CLK# going Low will be referred to as the positive CLK edge). Commands (address and control signals) are registered at the positive CLK edge. Input data is registered at both edges of W DQS, and output data is referenced to both edges of RDQS, as well as to both edges of CLK. Read and write accesses to the GDDR3 GRAPHICS SDRAM are burst oriented. The burst length can be programmed to 4 or 8 and the two least significant bits of the burst address are ―Don‘t Care‖ and internally set to LOW. Accesses start at a selected location and continue for a total of four or eight locations. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or W RITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or W RITE command are used to select the bank and the starting column location for the burst access. -6- Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 2. FEATURES • • • Density: 1Gbit Power supply (VDD, VDDQ): 1.8V 0.1V Organization: 1 Chip Select x 8 banks x 4M words x 32 bits (1-CS mode) and 2 Chip Select x 8 banks x 2M words x 32 bits (2-CS mode) Eight internal banks per Chip Select for concurrent operation 4n prefetch architecture: 128 bit per array Read or Write access Double-data rate architecture: two data transfers per clock cycle Single ended interface for data, address and command Differential clock inputs CLK, CLK# Commands entered on each positive CLK edge Single ended Read strobe (RDQS) per byte, edge-aligned with Read data Single ended Write strobe (WDQS) per byte, centeraligned with Write data W rite data mask (DM) function DLL aligns DQ and RDQS transitions with CLK clock edges for Reads Burst length (BL): 4 or 8 Sequential burst type only Programmable CAS latency: 7 to 14 • • • • • • • • • • • • • • • • • • • Programmable Write latency: 3 to 7 Auto precharge option for each burst access Pseudo open drain outputs with 40 ODT: nom. values of 60 , 120 pulldown, 40 pullup or 2 4 0 • • • • • • • • • • • • • Programmable termination and driver strength offsets Refresh cycles: 8192 cycles/32ms Auto-refresh and self-refresh modes ODT and output drive strength auto-calibration with external resistor ZQ pin (240 ) Programmable IO interface including on chip termination (ODT) tRAS lockout support Vendor ID for device identification Mirror function with MF pin Boundary Scan function with SEN pin tWR programmable for Writes with Auto-Precharge Calibrated output drive. Active termination support Short RAS to CAS timing for Writes Operating case temperature range: Tcase = 0°C to +105°C Package: 136-ball TFBGA. R oHS Compliant Product -7- Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 3. PIN CONFIGURATION 3.1 Ballout 1-CS Non-Merged Mode (Top View, MF=0) 1 VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ 2 VDD DQ0 DQ2 3 VSS DQ1 DQ3 4 ZQ VSSQ VDDQ VSSQ VDDQ CAS# BA0 CKE VDDQ A0 A11 A3 VDDQ VSSQ VDDQ VSSQ SEN 5 6 A B C D E F G H J K L M N P R T U 7 8 9 MF VSSQ VDDQ VSSQ VDDQ CS0# BA1 WE# VDDQ A4 A7 A9 VDDQ VSSQ VDDQ VSSQ RES 10 VSS DQ9 DQ11 11 VDD DQ8 DQ10 12 VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ WDQS0 RDQS0 DQ4 DQ6 VSSQ A1 A12 A10 VSSQ DQ24 DQ26 DM0 DQ5 DQ7 RAS# RAR A2 DQ25 DQ27 DM3 RDQS1 WDQS1 DM1 DQ13 DQ15 BA2 CLK# A6 DQ17 DQ19 DM2 DQ12 DQ14 VSSQ A5 C LK A8/AP VSSQ DQ16 DQ18 WDQS3 RDQS3 DQ28 DQ30 VDD DQ29 DQ31 VSS RDQS2 WDQS2 DQ21 DQ23 VSS DQ20 DQ22 VDD -8- Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 3.2 Ballout 2-CS Non-Merged Mode (Top View, MF=0) 1 VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ 2 VDD DQ0 DQ2 3 VSS DQ1 DQ3 4 ZQ VSSQ VDDQ VSSQ VDDQ CAS# BA0 CKE VDDQ A0 A11 A3 VDDQ VSSQ VDDQ VSSQ SEN 5 6 A B C D E F G H J K L M N P R T U 7 8 9 MF VSSQ VDDQ VSSQ VDDQ CS0# BA1 WE# VDDQ A4 A7 A9 VDDQ VSSQ VDDQ VSSQ RES 10 VSS DQ9 DQ11 11 VDD DQ8 DQ10 12 VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ WDQS0 RDQS0 DQ4 DQ6 VSSQ A1 RAR A10 VSSQ DQ24 DQ26 DM0 DQ5 DQ7 RAS# CS1# A2 DQ25 DQ27 DM3 RDQS1 WDQS1 DM1 DQ13 DQ15 BA2 CLK# A6 DQ17 DQ19 DM2 DQ12 DQ14 VSSQ A5 C LK A8/AP VSSQ DQ16 DQ18 WDQS3 RDQS3 DQ28 DQ30 VDD DQ29 DQ31 VSS RDQS2 WDQS2 DQ21 DQ23 VSS DQ20 DQ22 VDD -9- Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 3.3 Ballout Merged Mode (Top View, MF=0) 1 VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ 2 VDD DQ0 DQ2 3 VSS DQ1 DQ3 4 ZQ VSSQ VDDQ VSSQ VDDQ CAS# BA0 CKE VDDQ A0 A11 A3 VDDQ VSSQ VDDQ VSSQ SEN 5 6 A B C D E F G H J K L M N P R T U 7 8 9 MF VSSQ VDDQ VSSQ VDDQ CS0# BA1 WE# VDDQ A4 A7 A9 VDDQ VSSQ VDDQ VSSQ RES 10 VSS DQ9 DQ11 11 VDD DQ8 DQ10 12 VDDQ VSSQ VDDQ VSSQ VDDQ VDD VSS VREF VSS VDD VSS VDD VDDQ VSSQ VDDQ VSSQ VDDQ WDQS0 RDQS0 DQ4 DQ6 VSSQ A1 RFU A10 VSSQ DQ24 DQ26 DM0 DQ5 DQ7 RAS# A12/ CS1# A2 DQ25 DQ27 DM3 RDQS1 WDQS1 DM1 DQ13 DQ15 BA2 CLK# A6 DQ17 DQ19 DM2 DQ12 DQ14 VSSQ A5 C LK A8/AP VSSQ DQ16 DQ18 WDQS3 RDQS3 DQ28 DQ30 VDD DQ29 DQ31 VSS RDQS2 WDQS2 DQ21 DQ23 VSS DQ20 DQ22 VDD - 10 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 4. PIN DESCRIPTION 4.1 Signal Description Ball CLK, CLK# Type Input Detailed Function Clock:CLK and CLK# are differential clock inputs. Command and address inputs are latched on the rising edge of CLK. All latencies are referenced to CLK. CLK and CLK# are not internally terminated. Clock Enable:CKE High activates and CKE Low deactivates internal clock, device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operations (all banks idle), or Active Power-Down (row active in any bank). CKE is synchronous for Power-Down entry and exit and for Self Refresh entry. CKE must be maintained High throughout READ, W RITE and bus snoop bursts. Input buffers excluding CLK, CLK# and CKE are disabled during Power-Down. Input buffers excluding CKE are disabled during Self Refresh. The value of CKE latched at power-up with RES going High determines the termination value of the address and command inputs. CKE Input Chip Select:Chip Select: CS# Low enables, and CS# High disables the command decoder. All commands except DTERDIS are masked when CS# is registered High, but internal command execution continues. CS# provides for individual device selection on memory channels with multiple memory devices. CS# is considered part of the command code. In 1-CS mode only CS0# is available. In 2-CS mode both CS0# and CS1# are available, and CS0# is exclusively used for Mode Register or Extended Mode Register programming and self refresh entry. CS0#,CS1# Input RAS#,CAS#, WE# BA0-BA2 Input Command Inputs:Command inputs: RAS#, CAS# and WE# (along with CS0# or CS1#) define the command to be entered. Bank Address Inputs:BA0-BA2 define to which bank an ACTIVE, READ, W RITE or PRECHARGE command Input is being applied. BA0-BA2 also determine which Mode Register or Extended Mode Register is accessed with a MODE REGISTER SET command. Address Inputs:Address inputs: provide the row address for ACTIVE commands and the column address A0-A11 (A12) Input and auto precharge function (A8) for READ and WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 Low, bank selected by BA0- BA2) or all banks (A8 High). The address inputs also provide the op-code during an MODE REGISTER SET command. A12 is the MSB row address in 1-CS mode. DQ0-DQ31 DM0-DM3 I/O Input Data Inputs/Outputs:Data Input/Output: 32 bit data bus Input Data Masks:Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled High along with that input data during a W RITE access. DM is sampled on the rising and falling edges of WDQS. DM0 is associated with DQ0-DQ7, DM1 with DQ8-DQ15, DM2 with DQ16-DQ23 and DM3 with DQ24-DQ31. RDQS0RDQS3 WDQS0WDQS3 ZQ Read Data Strobes: Output with read data. RDQS is edge-aligned with read data. Output RDQS0 is associated with DQ0-DQ7, RDQS1 with DQ8-DQ15, RDQS2 with DQ16-DQ23 and RDQS3 with DQ24-DQ31. Write Data Strobes:WRITE Data strobe: Input with write data. WDQS is center-aligned to the input data. Input WDQS0 is associated with DQ0-DQ7, WDQS1 with DQ8-DQ15, WDQS2 with DQ16-DQ23 and WDQS3 with DQ24-DQ31. Reference ODT Impedance Reference: The ZQ ball is used to control the ODT impedance. - 11 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Reset pin:The RES pin is a Vddq CMOS input. RES is not internally terminated. When RES is at LOW state RES Input the chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High transition of the RES signal is used to latc h the CKE value to set the value of the termination resistors of the address and command inputs. After exiting the full reset a complete initialization is required since the full reset sets the internal settings to default, including mode register bits. Mirror function :MF is a VDDQ CMOS input. This pin must be hardwired on board either to a power or to a MF SEN Input Input Supply Supply Supply Supply Supply ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow for an easier routing on board for a back to back memory arrangement. Scan Enable:SEN is a VDDQ CMOS input. Must be tied to Ground when not in use. Reference voltage for command, address and data inputs. Isolated power for the input and output buffers . Isolated ground for the input and output buffers. Power Supply Ground Reserved Reserved for alternate rank (see ballouts) VREF VDDQ VSSQ V DD VSS RFU RAR 4.2 Addressing 2-CS Mode (CS0#,CS1#) Number of ranks Row Address Column addresses Bank address Auto precharge Page size Refresh 2 A0-A11 A2-A7,A9 BA0-BA2 A8/AP 2 KB 8K/32 mS 1-CS Mode (CS0#) 1 A0-A12 A2-A7,A9 BA0-BA2 A8/AP 2 KB 8K/32 mS - 12 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 5. STATE DIAGRAM 5.1 State Diagram for One Activated Bank The following diagram shows all possible states and transitions for one activated bank. The other 37 banks of the Graphics SDRAM are assumed to be in idle state. 5.1.1 State diagram for one bank Single Bank WR ACTIVE RD ACT PRE RD/A PDEN PDEX WR/A MRS EMRS IDLE SREN SREX PDEN PDEX Precharge POWER- DOWN Active AUTO REFRESH SELF REFRESH All Banks - 13 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 5.1.2 Function Truth Table for more than one Activated Bank If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the chip‘s multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank tRRD, tRTW and tWTR have to be taken always into account. 5.1.2.1 Function Truth Table Current State Ongoing action on bank n ACTIVATE1 WRITE 3 Possible action in parallel on bank m ACT, PRE, W RITE, W RITE/A, READ, READ/A2 ACT, PRE, W RITE, W RITE/A, READ, READ/A4 ACT, PRE, WRITE, W RITE/A, READ6 ACT, PRE, W RITE, W RITE/A, READ, READ/A8 ACT, PRE, W RITE, W RITE/A, READ, READ/A 8 ACT, PRE, W RITE, W RITE/A, READ, READ/A11 WRITE/A ACTIVE READ7) READ/A 9) PRECHARGE10 PRECHARGE ALL ACTIVATE 1) POWER DOWN ENTRY 12 IDLE AUTO REFRESH 13 12 10 12 ACT 15 16 POWER DOWN ENTRY SELF REFRESH ENTRY EXTENDED MRS 14 MODE REGISTER SET (MRS)14 EXTENDED MRS 214 POWER DOWN SELF REFRESH Notes : 1. Action ACTIVATE starts with issuing the command and ends after tRCD. POW ER DOWN EXIT - SELF REFRESH EXIT 2. During action ACTIVATE an ACT command on another bank is allowed considering tRRD or tRRD_RR, a PRE command on another bank is allowed any time. WR, WR/A, RD and RD/A are always allowed. 3. Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge. 4. During action WRITE an ACT or a PRE command on another bank is allowed any time. A new W R or WR/A command on another bank must be separated by at least one NOP from the ongoing W RITE. RD or RD/A are not allowed before tWTR or tWTR_RR is met. 5. Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling W DQS edge. 6. During action W RITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or W R/A command on another bank has to be separated by at least one NOP from the ongoing command. RD is not allowed before or tWTR or tWTR_RR is met. RD/A is not allowed during an ongoing W RITE/A action. 7. Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS. 8. During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to meet tRTW. 9. Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS. 10. Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after tRP. - 14 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 11. During Action ACTIVE an ACT command on another banks is allowed considering tRRD or tRRD_RR. A PRE command on another bank is allowed any time. WR, WR/A, RD and RD/A are always allowed. 12. During POWER DOWN and SELF REFRESH only the EXIT commands are allowed. 13. AUTO REFRESH starts with issuing the command and ends after tRFC. 14. Actions MODE REGISTER SET, EXTENDED MODE REGISTER SET and EXTENDED MODE REGISTER 2 SET start with issuing the command and ends after tMRD. 15. Action POWER DOWN EXIT starts with issuing the command and ends after tXPN. 16. Action SELF REFRESH EXIT starts with issuing the command and ends after tXSC. 5.1.3 Function Truth Table for CKE CKE N-1 L L CKE n L H CURRENT STATE Power Down Self Refresh Power Down Self Refresh All Banks Idle Bank(s) Active All Banks Idle COMMAND X X DESEL or NOP DESEL or NOP DESEL or NOP DESEL or NOP Auto Refresh ACTION Stay in Power Down Stay in Self Refresh Exit Power Down Exit Self Refresh 5 Entry Precharge Power Down Entry Active Power Down Entry Self Refresh H Note s: L 1. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the GDDR3 Graphics RAM immediately prior to clock edge n. 3. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND. 4. All states and sequences not shown are illegal or reserved. 5. DESEL or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 1000 clock cycles is required before applying any other valid command. - 15 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 5.2 Functional Block Diagram in 1-CS Mode A0-A7,A9, A8/AP, A10-A11,A12 BA0-BA2 Address Buffer A8/AP Refresh Counter Row Addresses A0-A12, BA0-BA2 Column Addresses A2-A7,A9 Mode Register Row Address Buffer Column Address Buffer Sense Amplifiers and Data Bus Buffer Sense Amplifiers and Data Bus Buffer Sense Amplifiers and Data Bus Buffer /RAS /CAS /WE RES Control Logic & Timing Generator /CS0 Row Decoder Memory Bank 4 Memory Array Back 0 8192 X512 X32 bit Row Decoder Memory Bank 5 Memory Array Back 1 8192 X512 X32 bit Row Decoder Memory Bank 6 Memory Array Back 2 8192 X512 X32 bit Sense Amplifiers and Data Bus Buffer Row Decoder Memory Bank 7 Memory Array Back 3 8192 X512 X32 bit Column Decoder Column Decoder Column Decoder MF ZQ CKE CLK /CLK DLL Output Buffers Input Buffers DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 DQ24-DQ31 DQ8-DQ15 RDQS1 WDQS1 DM1 DQ16-DQ23 RDQS2 WDQS2 DM2 - 16 - DQ24-DQ31 RDQS3 WDQS3 DM3 DQ0-DQ7 RDQS0 WDQS0 DM0 Publication Release Date: Apr, 22, 2011 Revision A01-002 Column Decoder W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 5.3 Functional Block Diagram in 2-CS Mode A0-A7,A9, A8/AP, A10-A11 BA0-BA2 Address Buffer A8/AP Refresh Counter Row Addresses A0-A11, BA0-BA2 Column Addresses A2-A7,A9 /CS1 Mode Register Row Address Buffer Column Address Buffer Sense Amplifiers and Data Bus Buffer Sense Amplifiers and Data Bus Buffer Sense Amplifiers and Data Bus Buffer /RAS /CAS /WE RES Control Logic & Timing Generator /CS0 Row Decoder Memory Bank 4 Memory Array Back 0 4096 X512 X32 bit Row Decoder Memory Bank 5 Memory Array Back 1 4096 X512 X32 bit Row Decoder Memory Bank 6 Memory Array Back 2 4096 X512 X32 bit Sense Amplifiers and Data Bus Buffer Row Decoder Memory Bank 7 Memory Array Back 3 4096 X512 X32 bit Column Decoder Column Decoder Column Decoder MF ZQ Column Decoder CKE CLK /CLK DLL Output Buffers Input Buffers DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 DQ24-DQ31 DQ8-DQ15 RDQS1 WDQS1 DM1 DQ16-DQ23 RDQS2 WDQS2 DM2 - 17 - DQ24-DQ31 RDQS3 WDQS3 DM3 DQ0-DQ7 RDQS0 WDQS0 DM0 Publication Release Date: Apr, 22, 2011 Revision A01-002 Bank 0 Bank 1 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6. FUNCTIONAL DESCRIPTION This section describe the unitization sequence of the GDRAM. It has been divided in to parts for each of the operations modes (1-CS or 2-CS). In the initialization, and before the choice of the operation mode by Mode Registration Set command, the default mode is 1-CS this implies a common initialization sequence up to point 7. 6.1 System Configurations Figure shows typical system configurations for 1-CS mode and 2-CS mode. 2-CS mode is equivalent to a clamshell configuration with two 512Mbit device s (rank 0 and rank 1) sharing a common interface; it benefits from the single physical pin load of this monolithic solution. In 1-CS mode the device is addressed as a single 8 -bank device, and the MSB row address A12 selects between the upper and lower half of the die. 6.1.1 System Configurations in 1-CS Mode and 2-CS Mode 1-CS Mode 2-CS Mode 1Gbit GDDR3 SDRAM 512Mbit GDDR3 SDRAM (Rank 0) Controller CS0# CLK,CLK# ADDR/CMD DQ0-DQ31 DM0-DM3 WDQS0-WDQS3 RDQS0-RDQS3 1Gbit GDDR3 SDRAM Controller CS0# CS1# CLK,CLK# ADDR/CMD DQ0-DQ31 DM0-DM3 WDQS0-WDQS3 RDQS0-RDQS3 512Mbit GDDR3 SDRAM (Rank 1) - 18 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.1.2 Initialization in 1– CS mode The GDDR3 GRAPHICS SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation or permanent damage to the device.The following sequence is highly recommended for Power-Up: 1. Apply power (VDD, VDDQ, VREF). Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF. Maintain RES = Low and CS0 = High to ensure that all the DQ outputs will be in HiZ state, all active terminations off and the DLL off. All other pins may be undefined. 2. Maintain stable conditions for 200 μs minimum for the GDDR3 to power up. 3. After clock is stable, set CKE to High or Low. After tATS minimum set RES to high. On the rising edge of RES, the CKE value is latched to determine the address and command bus termination value. If CKE is sampled LOW the address termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination is set to ZQ. 4. After tATH minimum, set CKE to high. 5. Wait a minimum of 700 cycles to calibrate and update the address and command termination impedances. Issue DESELECT on the command bus during these 700 cycles. 6. Apply a PRECHARGE ALL command by holding CS0 low and wait for tRP to expire. 7. Issue an Extended Mode Register Set command to set the mode to 1-CS and activate the DLL. The mode selection will be done using the bank address BA2 that will be set to low level for 1-CS mode (in Dual Rank Mode). 8. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters. 9. Wait 1000 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the impedance calibration is already completed, the DLL mimic circuitry can use the actual programmed driver impedance value. 10. Issue a PRECHARGE ALL command to each of the programmed ranks or issue single bank precharge commands to each of the 8 banks to place the chip in an idle state. 11. Issue or more AUTO REFRESH commands. - 19 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.1.3 Initialization in 2– CS mode The GDDR3 GRAPHICS SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation or permanent damage to the device.The following sequence is highly recommended for Power-Up: 1. Apply power (VDD, VDDQ, VREF). Apply VDD before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF. Maintain RES = Low and CS0 = High to ensure that all the DQ outputs will be in HiZ state, all active terminations off and the DLL off. All other pins may be undefined. 2. Maintain stable conditions for 200 μs minimum for the GDDR3 to power up. 3. After clock is stable, set CKE to High or Low. After tATS minimum set RES to high. On the rising edge of RES, the CKE value is latched to determine the address and command bus termination value. If CKE is sampled LOW the address termination value is set to ZQ / 2. If CKE is sampled HIGH, the address and command bus termination is set to ZQ 4. After tATH minimum, set CKE to high. 5. Wait a minimum of 700 cycles to calibrate and update the address and command termination impedances. Issue DESELECT on the command bus during these 700 cycles. 6. Apply a PRECHARGE ALL command by holding CS0 low and wait for tRP to expire. 7. Issue an Extended Mode Register Set command to set the mode to 2-CS and activate the DLL. The mode selection will be done using the bank address BA2 that will be set to high level for 2-CS mode (in Single Rank Mode). 8. Issue an Mode Register Set command after tMRD is met to reset the DLL and define the operating parameters. 9. Wait 1000 cycles of clock input to lock the DLL. No Read command can be applied during this time. Since the impedance calibration is already completed, the DLL mimic circuitry can use the actual programmed driver impedance value. 10. Issue a PRECHARGE ALL command to each of the programmed ranks or issue single bank precharge commands to each of the 16 banks in 2-CS Mode, to place the chip in an idle state. 11. Issue or more AUTO REFRESH commands. - 20 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.1.3.1 Power Up Sequence VDD VDDQ VREF tATS tATH RES CKE CKE# CLK Com DM CODE CODE DES DES PA EMR MRS PA ARF ARF ACT RA All Banks RA All Banks A8 BA0, BA1 RDQS WDQS DQ min. 200 uS VDD and CLK stable 700 cycles tRP tMRD CODE CODE BA0=H, BA1=L BA0=L, BA1=L RA tMRD tRP tRFC tRFC 1000 cycles MRS:MRS command With DLL Reset EMR: EMRS command DES:Deselect PA: PREALL command ARF: AUTO REFRESH command A.C.: Any command Don’t Care - 21 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM .2 Mirror Function The GDDR3 GRAPHICS SDRAM provides a mirror function (MF) pin to change the physical location of the command and address pins assisting in routing devices back to back. The MF ball should be tied directly to VSSQ or VDDQ depending on the control line orientation desired. The pins affected by this Mirror Function mode are listed in Table . The CS1# and A12 pins are not affected by Mirror Function. 6.2.1 Ball Assignment with Mirror Function Signal Ball F4 F9 G4 G9 H2 Signal Ball H3 H4 H9 H10 H11 Signal Ball K2 K3 K4 K9 K10 Signal Ball K11 L4 L9 M4 M9 MF=0 CAS# CS0# BA0 BA1 A1 MF=1 CS0# CAS# BA1 BA0 A5 MF=0 RAS# CKE WE# BA2 A5 MF=1 BA2 WE# CKE RAS# A1 MF=0 A10 A2 A0 A4 A6 MF=1 A8/AP A6 A4 A0 A2 MF=0 A8/AP A11 A7 A3 A9 MF=1 A10 A7 A11 A9 A3 - 22 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.3 Commands In the following table CKEn refers to the positive edge of CLK corresponding to the clock cycle when the command is given to the Graphics SDRAM. CKEn-1 refers to the previous positive edge of CLK. For all command and address inputs CKEn is implied. All input states or sequences not shown are illegal or reserved. 6.3.1 Command Overview for 1-CS mode A2-7 A9-11/12 RAS# CAS# CS0# Note 1 1 ,2 1 ,3 1 ,4 1 ,4 1 ,5 1 ,6 1 ,7 1 ,8 1 ,9 WE# CKE n -1 CKE n BA0 BA1 BA2 Operation Code Device Delselect DESEL H H H H H H H H H H H H H H H L H L H H H L L L L L L L L L L L L H L X L X L X H H H L L L L H H H H L L L X H X L X XX XL HH L L L L L L L L H H L H L L L H L L L L H HH X X X 0 1 0 X X X 0 0 1 X X X 0 0 A8 X X X OPCODE X X X OPCODE OPCODE Data Terminator Disable No Operation Mode Register Set Extended Mode Register Set Bank Activate Read Read w/ Autoprecharge W rite Write w/ Autoprecharge Precharge Precharge All Auto Refresh Power Down Mode Entry Power Down Mode Exit Self Refresh Entry Self Refresh Exit DTERDIS NOP MRS EMRS ACT RD RD/A WR WR/A PRE PREALL AREF PW DNEN PW DNEX SREFEN SREFEX H H H H H H H H H H H H H H L H L Extended Mode Register Set 2 EMRS2 HH BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA X X X X X X X X X X X X X X X X X X Row Adress L H L H L H X X X X X Col. Col. Col. Col. X X X X X X X H BA BA BA XX HH XX L H XX Notes : 1. X represents ―Don‘t Care‖. 2. This command is invoked when a Read is issued on another DRAM rank placed on the same command bus. Cannot be in power-down or selfrefresh state. The Read command will cause the data termination to be disabled. 3. BA0 - BA2 provide bank address, A0 - A11, A12 provide the row address. 4. BA0 - BA2 provide bank address, A2 - A7, A9 provide the column address, A8/AP controls Auto Precharge. 5. Auto Refresh and Self Refresh Entry differ only by the state of CKE. 6. PWDNEN is selected by issuing a DESEL or NOP at the first positive CLK edge following the HIGH to LOW transition of CKE. 7. First possible valid command after tXPN. During tXPN only NOP or DESEL commands are allowed. 8. Self Refresh is selected by issuing AREF at the first positive CLK edge following the HIGH to LOW transition of CKE. 9. First possible valid command after tXSC. During tXSC only NOP or DESEL commands are allowed. - 23 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.3.2 Command Overview for 2-CS mode A2-7 A9-11 X X X Col. Col. Col. Col. Col. Col. Col. Col. X X X X X X X X X X X X X 1 ,6 1 ,5 1 1 1 ,4 1 ,4 1 ,4 RAS# CAS# CS0# CS1# Operation Code Ranks Device Deselect DESEL H H H H H H H H H H H H H H H H H H H H H H H H H H L H L H H H L X L L L L H L H L H L H L H L H L L H L L H L H X L X L X L HX H H X L X X X H L H L H L H L H L H L L H L L H L L H L X X L X H H L L L L L H H H H H H H H L L L L L L L L L X H X L X X X H L H L L L H H L L L L L L L L H H H H H H L L L X H X L X X L H H H L L L H H H H H H L L L L L L L L L L H H H X H X H X X X X 0 1 0 X X X 0 0 1 X X X 0 0 X X X Data Terminator Disable No Operation Mode Register Set Extended Mode Register Set Bank Activate Read Read w/ Autoprecharge Write Write w/ Autoprecharge Precharge DTERDIS NOP MRS EMRS ACT RD RD/A WR WR/A PRE MemBlock 1 MemBlock 2 MemBlock 1 MemBlock 2 MemBlock 1 MemBlock 2 MemBlock 1 MemBlock 2 MemBlock 1 MemBlock 2 MemBlock 1 MemBlock 2 Both H H H H H H H H H H H H H H H H H H H H H H H H H OPCODE OPCODE OPCODE 1 ,3 Extended Mode Register Set 2 EMRS2 BA BA BA Row Address BA BA BA Row Address BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA BA X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X L L H H L L H H L L L H H H X X X X X X X Precharge All PREALL MemBlock 1 MemBlock 2 Both Auto Refresh AREF MemBlock 1 MemBlock 2 Both Power Down Mode Entry PWDNEN Power Down Mode Exit Self Refresh Entry Self Refresh Exit PWDNEX SREFEN SREFEX L H L - 24 - Publication Release Date: Apr, 22, 2011 Revision A01-002 Note 1 1 ,2 1 ,4 1 ,7 1 ,8 1 ,9 WE# CKE n -1 CKE BA0 BA1 BA2 A8 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Notes : 1. X represents ―Don‘t Care‖. 2. This command is invoked when a Read is issued on another DRAM rank placed on the same command bus. Cannot be in power-down or selfrefresh state. The Read command will cause the data termination to be disabled. Refer to Figure (Self Calibration of PMOS and NMOS legs) for timing. 3. BA0 - BA2 provide bank address, A0 - A11, A12 provide the row address. 4. BA0 - BA2 provide bank address, A2 - A7, A9 provide the column address, A8/AP controls Auto Precharge. 5. Auto Refresh and Self Refresh Entry differ only by the state of CKE. 6. PWDNEN is selected by issuing a DESEL or NOP at the first positive CLK edge following the HIGH to LOW transition of CKE. 7. First possible valid command after tXPN. During tXPN only NOP or DESEL commands are allowed. 8. Self Refresh is selected by issuing AREF at the first positive CLK edge following the HIGH to LOW transition of CKE. 9. First possible valid command after tXSC. During tXSC only NOP or DESEL commands are allowed. 6.3.3 Description of Command Command DESEL Description The DESEL function prevents new commands from being executed by the Graphics SDRAM. The Graphics SDRAM is effectively deselected. Operations in progress are not affected. The NOP command is used to perform a no operation to the Graphics SDRAM, which is selected (corresponding CS is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. The Mode Register is loaded via address inputs A0 - A11. For more details see “Mode Register Set Command (MRS)‖ . The MRS command can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. The Extended Mode Register is loaded via address inputs A0 - A11. For more details see section Extended Mode Register Commands EMRS1-3 . The EMRS commands can only be issued when all banks are idle and no bursts are in progress. A subsequent executable command cannot be issued until tMRD is met. The ACT command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 - BA2 inputs selects the bank, and the address provided in inputs A0 - A11/A12 selects the row. This row remains active (or open) for accesses until a precharge (PRE, RD/A, or W R/A command) is issued to that bank. A precharge must be issued before opening a different row in the same bank. The RD command is used to initiate a burst read access to an active row. The value on the BA0 - BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The row will remain open for subsequent accesses. For RD commands the value on A8 is set LOW . The RD/A command is used to initiate a burst read access to an active row. The value on the BA0 - BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end of the read burst. The same individualbank precharge function is performed like it is described for the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. The user must not issue a new ACT command to the same bank until the precharge time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the earliest possible time as described in section ―Reads (RD)‖ . NOP MRS EMRS ACT RD RD/A - 25 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM The W R command is used to initiate a burst write access to an active row. The value on the BA0 - BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The row will remain open for subsequent accesses. For W R commands the value on A8 is set LOW . WR Input data appearing on the DQs is written to the memory array depending on the value on the DM input appearing coincident with the data. If a given DM signal is registered LOW , the corresponding data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed for that byte / column location. The WR/A command is used to initiate a burst write access to an active row. The value on the BA0, BA1and BA2 inputs selects the bank, and the address provided on inputs A2-A7, A9 selects the column location. The value on input A8 is set HIGH. The row being accessed will be precharged at the end of the write burst. The same individual-bank precharge function is performed which is described for the PRE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. The user is not allowed to issue a new ACT to the same bank until the precharge time (tRP) is completed. This time is determined as if an explicit PRE command was issued at the earliest possible time as described in section ―Writes (WR)‖ . Input data appearing on the DQs is written to the memory array depending on the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW , the corresponding data will be written to the memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. The PRE command is used to deactivate the open row in a particular bank. The bank will be available for a subsequent row access a specified time (tRP) after the PRE command is issued. Inputs BA0 - BA2 select the bank to be precharged. A8/AP is set to LOW. Once a bank has been precharged, it is in the idle state and must be activated again prior to any RD or W R commands being issued to that bank. A PRE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. The PREALL command is used to deactivate all open rows in the memory device. The banks will be available for a subsequent row access a specified time (tRP) after the PREALL command is issued. Once the banks have been precharged, they are in the idle state and must be activated prior to any read or write commands being issued. The PREALL command will be treated as a NOP for those banks where there is no open row, or if a previously open row is already in the process of precharging. PREALL is issued by a PRE command with A8/AP set to HIGH. The AREF is used during normal operation of the GDDR3 Graphics RAM to refresh the memory content. The refresh addressing is generated by the internal refresh controller. This makes the address bits ―Don‘t Care‖ during an AREF command. The GDDR3 GRAPHICS SDRAM requires AREF cycles at an average periodic interval of tREFI(max). To improve efficiency a maximum number of eight AREF commands can be posted to one memory device (with tRFC from AREF to AREF) as described in section ―Auto Refresh Command (AREF)‖. This means that the maximum absolute interval between any AREF command is 8 x tREFI(max). This maximum absolute interval is to allow the GDDR3 Graphics RAM output drivers and internal terminators to recalibrate, compensating for voltage and temperature changes. All banks must be in the idle state before issuing the AREF command. They will be simultaneously refreshed and return to the idle state after AREF is completed. tRFC is the minimum required time between an AREF command and a following ACT/AREF command. WR/A PRE PREALL AREF - 26 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM The Self Refresh function can be used to retain data in the GDDR3 Graphics RAM even if the rest of the system is powered down. W hen entering the Self Refresh mode by issuing the SREFEN command, the GDDR3 Graphics RAM retains data without external clocking. The SREFEN command is initiated like an AREF command except CKE is disabled (LOW). The DLL is automatically disabled upon entering Self Refresh mode and automatically enabled and reset upon exiting Self Refresh. (1000 cycles must then occur before a RD or DTERDIS command can be issued) The active terminations remain enabled during Self Refresh. Input signals except CKE are ―Don‘t Care‖. If two GDDR3 Graphics RAMs share the same Command and Address bus, Self Refresh may be entered only for the two devices at the same time. In 2-CS mode, both memories may only enter Self-Refresh, in parallel. The SREFEX command is used to exit the Self Refresh mode. The DLL is automatically enabled and reset upon exiting. The procedure for exiting Self Refresh requires a sequence of commands. First CLK and CLK# must be stable prior to CKE going from LOW to HIGH. Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXSC is satisfied. This time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and output calibration is to apply NOPs for 1000 cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. SREFEN SREFEX The PW DNEN command enables the power down mode. It is entered when CKE is set low together with a NOP/DESEL. The CKE signal is sampled at the rising edge of the clock. Once the power down mode is initiated, all of the receiver circuits except CLK and CKE are gated off to reduce power consumption. The DLL remains active (unless disabled before with EMRS). All banks can be set to idle state or stay active. During PW DNEN Power Down Mode, refresh operations cannot be performed; therefore the refresh conditions of the chip have to be considered and if necessary Power Down state has to be left to perform an Auto Refresh cycle. If two GDDR3 Graphics RAMs share the same Command and Address bus, Power down may be entered only for the two devices at the same time. PW DNEX A CKE HIGH value sampled at a low to high transition of CLK is required to exit power down mode. Once CKE is HIGH, the GDDR3 Graphics RAM must receive only NOP/DESEL commands until tXPN is satisfied. After tXPN any command can be issued, but it has to comply with the state in which the power down mode was entered. Data Termination Disable (Bus snooping for RD commands): The Data Termination Disable Command is detected by the device by snooping the bus for RD commands excluding CS. The GDDR3 Graphics RAM will disable its Data terminators when a RD command is detected. The terminators are disabled starting at CL - 1 clocks after the RD command is detected and the duration is 4 clocks. In a 2CS system, both DRAM devices will snoop the bus for RD commands to either device and both will disable their terminators if a RD command is detected. The command and address terminators are always enabled. See Figure (ODT Disable Timing during a READ command) for an example of when the data terminators are disabled during a RD command. DTERDIS - 27 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.3.4 Minimum delay from RD/A and W R/A to any other command (to another bank) with concurrent AP Minimum delay to another bank (with concurrent auto precharge) (WL + 2) × tCK + tWTR 2 × tCK From Command To Command RD or RD/A Note WR/A WR or W R/A PRE ACT RD or RD/A WR or W R/A PRE ACT tCK tCK 2 × tCK (CL + 4 - W L) × tCK RD/A tCK tCK 6.4 Boundary Scan 6.4.1 General Description The 1-Gbit GDDR3 incorporates a modified boundary scan test mode. This mode doesn‘t operate in accordance with IEEE Standard 1149.1-1990. To save the current GDDR3 ball-out, this mode will scan the parallel data input and output the scanned data through the W DQS0 pin controlled by SEN. Note: Both pads CS1# and A12 will be activated and could be accessed during Boundary Scan. 6.4.2 Disabling the scan feature It is possible to operate the GDDR3 without using the boundary scan feature. SEN (at U-4 of 136- ball package) should be tied LOW (VSS) to prevent the device from entering the boundary scan mode. The other pins which are used for scan mode, RES, MF, WDQS0 and CS will be operating at normal GDDR3 functionalities when SEN is deasserted. - 28 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.4.2.1 Internal Block Diagram (Reference only) Tie to logic 0 DM0 Pins under test D DQ CK D DQ CK Dedicated Scan D FF Per signal under test DQ5 DQ4 D DQ CK The following lists the rest of the signals on the scan chain: DQ[3:0],DQ[31:6],RDQS[3:1],DM[3:1], CAS#,WE#,CKE,BA[2:0],A[11:0],CK, CK# and ZQ Two RFU‘s (J-2 and J-3 on 136-ball package) will be on The scan chain and will read as a logic ―0‖ DQ CK The following lists the signals not on the scan chain: VDD,VSS,VDDQ,VSSQ,VDDA,VSSA and VREF RDQS0 RES (SSH,Scan Shift) CS# (SCK,Scan Clock) WDQS0 (SOUT,Scan Out) SEN, Scn Enable MF (SOE#, Output Enable) D Puts device into scan mode and re-maps pins to scan functionality 6.4.2.2 Boundary Scan Exit Order BIT# 1 2 3 4 5 6 7 8 9 10 11 12 BALL D-3 C-2 C-3 B-2 B-3 A-4 B-10 B-11 C-10 C-11 D-10 D-11 BIT# 13 14 15 16 17 18 19 20 21 22 23 24 BALL E-10 F-10 E-11 G-10 F-11 G-9 H-9 H-10 H-11 J-11 J-10 L -9 BIT# 25 26 27 28 29 30 31 32 33 34 35 36 BALL K-11 K-10 K-9 M-9 M-11 L-10 N-11 M-10 N-10 P-11 P-10 R-11 BIT# 37 38 39 40 41 42 43 44 45 46 47 48 BALL R-10 T-11 T-10 T-3 T-2 R-3 R-2 P-3 P-2 N-3 M-3 N-2 BIT# 49 50 51 52 53 54 55 56 57 58 59 60 BALL L -3 M-2 M-4 K-4 K-3 K-2 L -4 J -3 J -2 H-2 H-3 H-4 BIT# 61 62 63 64 65 66 67 BALL G-4 F -4 F -2 G-3 E-2 F -3 E-3 - 29 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Notes : 1. W hen the device is in scan mode, the mirror function will be disabled and none of the pins are remapped. 2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode. 3. An unconnected CS1# and A12 on the board will be read as undefined. 6.4.2.3 Scan Pin Description PACKAGE BALL V-9 F -9 D-2 V-4 SYMBOL NORMAL FUNCTION RES CS WDQS0 SEN TYPE DESCRIPTION Scan Shift: Capture the data input from the pad at logic LOW and shift the data on the chain at logic HIGH. Scan Clock: Not a true clock, could be a single pulse or series of pulses. All scan inputs will be referenced to rising edge of the scan clock Scan Enable: Logic HIGH enables the device into scan mode and will be disabled at logic LOW . Must be tied to GND when not in use. SSH SCK SOUT SEN Input Input Output Scan Output Input A-9 SOE MF Scan Output Enable: Enables (registered LOW) and disables (registered HIGH) SOUT data. This pin will be tied to VDD or GND through a resistor Input (typically 1 KΩ for normal operation). Tester needs to overdrive this pin to guarantee the required input logic level in scan mode. Notes : 1. W hen SEN is asserted, no commands are to be executed by the GDDR3. This applies both to user commands and manufacturing commands which may exist while RES is deasserted. 2. The Scan Function can be used right after bringing up VDD / VDDQ of the device. No initialization sequence of the device is required. After leaving the Scan Function it is required to run through the complete initialization sequence. 3. In Scan Mode all terminations for CMD/ADD and DQ, DM, RDQS and W DQS are switched off. 4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE‘s should be provided to top and bottom devices to access the scanned output. W hen either of the devices is in scan mode, SOE for the other device which is not in a scan will be disabled. 6.4.2.4 Scan DC Electrical Characteristics and Operating Condition PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Notes : 1. The parameter applies only when SEN is asserted. 2. All voltages referenced to GND. Symbol Min. M ax. — Units Note 1,2 1 ,2 VIH(DC) VIL(DC) VREF+0.15 — VREF-0.15 V - 30 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.4.2.5 Scan Capture Timing SCK tSES SEN SSH Low tSCS SOE# Pins Under Test tSDS tSDH VALID Don‘t care 6.4.2.6 Scan Shift Timing SCK tSES SEN SSH tSCS tSCS SOE# SOUT Scan Out Bit 0 Scan Out Bit 1 Scan Out Bit 2 Scan Out Bit 3 tSAC tSOH Don’t care - 31 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.4.2.7 Scan AC Electrical Characteristic Parameter/Condition Clock Clock cycle time Scan Command Time Scan enable setup time Scan enable hold time Scan command setup time for SSH, SOE and SOUT Scan command hold time for SSH, SOE and SOUT Scan Capture Time Scan capture setup time Scan capture hold time Scan Shift Time Scan clock to valid scan output Scan clock to scan output hold Notes: 1. The parameter applies only when SEN is asserted. 2. Scan Enable should be issued earlier than other Scan Commands by 6 ns. Symbol Min. 40 20 20 14 14 10 10 — 1 .5 Max. — — — — — — — 10 — Units ns ns ns ns ns ns ns ns ns Note tSCK tSES tSEH tSCS tSCH 1 1 ,2 2 1 1 tSDS tSDH tSAC tSOH 1 1 1 1 6.4.3 Scan Initialization The Initialization sequence for the boundary scan functionality depends on the intended SGRAM operation mode. There are two modes to distinguish. The first mode is the Stand-Alone mode. In the Stand-Alone mode the SGRAM is supposed to support the Boundary Scan functionality only, the user does not intend to operate the DRAM in its ordinary functionality after or prior to the entering of the Boundary Scan functionality. The purpose of the Stand-Alone mode could be a connectivity test at the manufacturing site. The second mode is the regular SGRAM functionality. W ith this common mode the boundary scan functionality can be enabled after the SGRAM has been initialized by the regular power-up and SGRAM Initialization sequence. W hen the boundary scan functionality is left the regular SGRAM initialization sequence has to be re-iterated. 6.4.3.1 Scan Initialization for Stand-Alone Mode The SGRAM needs to follow the given sequence to support the boundary scan functionality in the Stand-Alone mode. There is no external clock for the whole sequence needed. Sequence Flow: 1. External Voltages (VDD/VDDQ/VREF) need to be stable for 200μs, SEN has to be kept low. 2. Bring SEN up to high state to enter boundary scan functionality. 3. Operate boundary scan functionality according to the scan features given in Chapter. 4. Boundary scan can be exited by bringing SEN low or simply by switching power off. The Scan initialization sequence for the Stand-Alone Mode is shown in Figure. - 32 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.4.3.2 Scan Initialization for Stand-Alone mode VDD VDDQ VREF CLK/ CLK# SSH [RES] SEN SCK[CS#] SOE[MF] tSCS tSCS tSES tSDS tSDH VALID tSCS tSCH tSCS tSCH SOUT[WDQS] Pins Under Test T = 200 us Power-up : VDD / VDDQ / VREF stable tSDS tSDH ScanOut Bit 0 VALID Boundary Scan Mode Don‘t care 6.4.4 Scan Initialization in regular SGRAM operation The Initialization sequence of the boundary scan functionality in regular SGRAM operation has to follow the given sequence. Sequence Flow: 1. External Voltages (VDD/VDDQ/VREF) need to be stable for 200 μs, RES has to be kept low, external clock has to be stable prior to RES goes high 2. Bring RES high and keep clock stable for 700tcks, CKE will be latched by rising RES edge, keep tATH/tATS 3. Bring SEN up to high state to enter boundary scan functionality 4. Operate boundary scan functionality accordingly to the scan features given in Chapter. 5. Boundary scan can be exited by bringing SEN low 6. W ait tSN for bringing up RES, prior to bringing RES to high state external has to be stable 7. After RES is at high state wait 700tck 8. Continue with regular Initialization sequence (PRE-ALL, EMRS, MRS) - 33 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM The steps 1 and 2 are necessary to enable the termination for the command/address pins. They are part of the regular SGRAM Initialization. They are required if the user wants to issue commands between to entering of the boundary scan functionality and the power-up sequence. The entering of the boundary scan mode is resetting the command/address termination values and all EMRS/MRS settings. Therefore they have to be initialized again after the boundary scan functionary has been left. Figure (Boundary Scan Exit Sequence)shows the scan initialization sequence for regular SGRAM operation. 6.4.4.1 Scan Initialization Sequence within regular SGRAM Mode VDD VDDQ VREF CLK/CLK# SSH [RES] tATS tATH tSCS tSDS tSDH VALID tSES tSCH tSDS tSDH VALID tSCS tSCH CKE SEN SCK[CS#] SOE[MF] tSCS tSCS SOUT[WDQS] Pins Under Test T = 200 us Power-up : VDD stable RESET at power - up 700 tCK tSDS tSDH ScanOut Bit 0 VALID Boundary Scan Mode Don‘t care - 34 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.4.5 Scan Exit Sequence Figure shows the Scan exit Sequence. This figure show the exiting of the boundary scan functionality in conjugation with the appended regular SGRAM initialization sequence to bring the SGRAM again in a well defined state. 6.4.5.1 Boundary Scan Exit Sequence Stable clock CLK/ CLK# tRESL RES tATS tATH Standard Power up sequence Starting with PRE ALL CKE tSN SEN SOUT invalid 700 tCK 6.4.5.2 Scan AC Electrical Parameter Limit Values Parameter Symbol Min Max. Unit 20 20 Note tRESL tSN tRESL tSN ns ns - 35 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.5 Programmable impedance output drivers and active terminations 6.5.1 GDDR3 IO Driver and Termination The GDDR3 GRAPHICS SDRAM is equipped with programmable impedance output buffers and active terminations. This allows the user to match the driver impedance to the system impedance. To adjust the impedance of DQ[0:31] and RDQS[0:3], an external precision resistor (ZQ) is connected between the ZQ pin and VSS. The value of the resistor must be six times the value of the desired impedance. For example, a 240 Ω resistor is required for an output impedance of 40 Ω. The range of ZQ is 210 Ω to 270 Ω, giving an output impedance range of 35 Ω to 45 Ω (one sixth the value of ZQ within 10%). The value of ZQ is used to calibrate the internal DQ termination resistors of DQ[0:31], W DQS[0:3] and DM[0:3]. The two termination values that are selectable using EMRS[3:2] are ZQ / 4 and ZQ / 2. The value of ZQ is also used to calibrate the internal address command termination resistors. The inputs terminated in this manner are A[0:11], A[12],CKE#, CS0#, CS1#, RAS#, CAS#, W E#. The two termination values that are selectable upon por up (CKE latched LOW to HIGH transition of RES) are ZQ / 4 and ZQ / 2.. RES, MF , CLK and CLK# are not internally terminated. If no resistance is connected to ZQ, an internal default value of 240 Ω will be used. In this case, no calibration will be performed. - 36 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.5.1.1 Output Deiver simplified schematic VDDQ Read to other Rank Output Data Read to other Enable DQ VSSQ 6.5.1.2 Range of external resistance ZQ Parameter External resistance value 6.5.1.3 Termination Types and Activation Ball CLK, CLK#, RDQS[0:3], ZQ, RES, MF CKE, CS0#, CS1#, RAS#, CAS#, W E#, BA0 - BA2 , A[0:11], A[12] DM[0:3], W DQS[0:3] DQ[0:31] Termination type No termination Add / CMDs DQ DQ Always ON Always ON CMD bus snooping Termination activation Symbol ZQ Min. 210 Nom. 240 Max. 270 Units Ω Note - 37 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.5.2 Self Calibration for Driver and Termination The output impedance is updated during all AREF commands. These updates are used to compensate for variations in supply voltage and temperature. Impedance updates do not affect device operation. No activity on the Address, command and data bus is allowed during a minimum Keep Out time tKO after the Autorefresh command has been issued. 6.5.2.1 Termination update Keep Out time after Autorefresh command CLK# CLK Com. Add. DQ ARF : Autorefresh Don’t care Keep Out time ARF NOP tKO To guarantee optimum driver impedance after power-up, the GDDR3 GRAPHICS SDRAM needs 700 cycles after the clock is applied and stable to calibrate the impedance upon power-up. The user can operate the part with fewer than 700 cycles, but optimal output impedance will not be guaranteed. The GDDR3 Graphics RAM proceeds in the following manner for Self Calibration: The PMOS device is calibrated against the external ZQ resistor value. First one PMOS leg is calibrated against ZQ. The number of legs used for the terminators (DQ and ADD/CMD) and the PMOS driver is represented in Table . Next, one NMOS leg is calibrated against the already calibrated PMOS leg. The NMOS driver uses 6 NMOS legs. - 38 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.5.2.2 Number of Legs used for Terminator and Driver Self Calibration CKE (at RES) 0 ADD / CMD Terminator DQ 1 00 10 11 PMOS NMOS Termination ZQ/2 ZQ EMRS[3:2] Disabled ZQ/4 ZQ/2 ZQ/6 ZQ/6 0 4 2 6 6 1 Number of Legs 2 1 Note Driver Note : 1. EMRS[3:2] = 00 disables the ADD and CMD terminations as well. Figure represents a simplified schematic of the calibration circuits. First, the strength control bits are adjusted in such a way that the VDDQ voltage is divided equally between the PMOS device and the ZQ resistor. The best bit pattern will cause the comparator to switch the PMOS Match signal output value. In a second step, the NFET is calibrated against the already calibrated PFET. In the same manner, the best control bit combination will cause the comparator to switch the NMOS Match signal output value. 6.5.2.3 Self Calibration of PMOS and NMOS Legs VDDQ VDDQ NMOS Calibration Strength Control [2:0] VSSQ PMOS Calibration VDDQ / 2 ZQ Match VDDQ / 2 VSSQ VSSQ Strength Control [2:0] - 39 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.5.3 Dynamic Switching of DQ terminations The GDDR3 Graphics RAM will disable its data terminators when a READ or DTERDIS command is detected. The terminators are disabled starting at CL - 1 Clocks after the READ / DTERDIS command is detected and the duration is 4 clocks. In a two rank system, both devices will snoop the bus for a READ / DTERDIS command to either device and both will disable their terminators if a READ / DTERDIS command is detected. The address and command terminators are always enabled. 6.5.3.1 ODT Disable Timing during a READ command 0 1 2 3 4 5 6 7 8 9 CLK# CLK Com. RD N/D N/D N/D N/D N/D N/D N/D N/D N/D Add. B/C CAS Iatency = 5 RDQS DQ D0 D1 D2 D3 DQ Termination Data Terminations are disabled Dx : Data from B / C Com. : Command Addr. : Address B / C B / C : Bank / Column address RD : READ N / D : NOP or Deselect Don‘t care - 40 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.5.4 Output impedance and Term ination DC Electrical Characteristics The Driver and Termination impedances are determined by applying VDDQ/2 nominal at the corresponding input/output and by measuring the current flowing into or out of the device. VDDQ is set to the nominal value. IOH is the current flowing out of DQ when the Pull-Up transistor is activated and the DQ termination disabled. IOL is the current flowing into DQ when the Pull-Down transistor is activated and the DQ termination disabled. ITCAH(ZQ) is the current flowing out of the Termination of Commands and Addresses for a ZQ termination value. 6.5.4.1 DC Electrical Characteristic Limit Values Parameter ZQ Value M in. 240 Max. 25.0 25.0 4.2 mA mA mA 1,2 1,2 1,2 Unit Note IOH IOL ITCAH(ZQ) ZQ/6 ZQ/6 ZQ 20.5 20.5 3.4 Notes : 1. Measurement performed with VDDQ (nominal) and by applying VDDQ/2 at the corresponding Input / Output. 0° C ≤ Tc ≤105° C 2. for 1.8 V VDD/VDDQ power supply - 41 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.6 Mode Register Set Command (MRS) The Mode Register stores the data for controlling the operation modes of the memory. It programs CAS latency, test mode, DLL Reset, the value of the Write Latency and the Burst length. The Mode Register must be written after power up to operate the SGRAM. During a Mode Register Set command the address inputs are sampled and stored in the Mode Register. The mode Register content can only be set or changed when the chip is in idle state. For non -READ commands following a Mode Register Set a delay of tMRD must be met. To apply an MRS command, CS0 has to be used. 6.6.1 Mode Register Set Command CLK# CLK CKE CS# RAS# CAS# WE# A0-A11 BA0 BA1, BA2 (High) COD 0 0 COD: Code to be loaded into the register. = Don't Care 6.6.2 Mode Registers Three Mode Registers MRS, EMRS1 and EMRS2 define the specific mode of op eration. All Mode Registers are initialized upon power-up as indicated below. All functions controlled by Mode Register EMRS3 and some high -speed options in the other registers as outlined below shall be deactivated or deleted such that programming of the respective register bits has no effect. 6.6.2.1 Mode Register (MRS) The Mode Register controls operating modes such as Burst Length, Burst Type, CAS latency, Write Latency, DLL Reset and Test Mode as shown in Figure . The register is programmed via the MODE REGISTER SET command with BA0=0, BA1=0 and BA2=0. - 42 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.6.2.2 Mode Register (MRS) BA2 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 WL DLL TM CAS Latency Test Mode BT BL Burst Length A2 0 0 A1 1 1 All others A0 0 1 BL 4* 8 RFU Write Latency A1 0 1 1 1 1 A10 1 0 0 1 1 A9 1 0 1 0 1 WL 3* 4 5 6 7 DLL Reset A8 0 1 DLL Reset No* Yes A7 0 1 mode Normal* Test mode CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency 8* 9 10 11 12 13 14 7 A3 0 1 Burst Type BT Sequential* RFU Note: The DLL Reset bit is self-clearing * Default value at power-up 6.6.2.3 Mode Register Set Timing CLK# CLK Command PA NOP MRS NOP NOP A.C. NOP RD tRP tMRD tMRDR MRS : MRS command PA : PREALL command A.C. : Any other command as READ RD : READ command Don't Care - 43 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.6.3 Burst Length and Burst Type 6.6.3.1 Burst Length Read and write accesses to the GDDR3 GRAPHICS SDRAM are burst-oriented, with a burst length of 4 or 8 as programmed inbits A0-A2. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning t hat the burst will wrap within the block if a boundaryis reached. The block is uniquely selected by address bits A2-A7,A9. The access order within a burst is fixed, and address bits A0 and A1 are ignored as shown in Table. The only supported burst type is sequential. 6.6.3.2 Burst type Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3). This device does not support the burst interleave mode. 6.6.3.2.1 Burst Definition Burst Length A2 4 8 — 0 1 Column Address A1 X X X A0 X X X Order of Accesses within a Burst 0 -1 -2 -3 0-1-2-3-4-5-6-7 4-5-6-7-0-1-2-3 The value applied at the balls A0 and A1 for the column address is ―Don‘t care‖. 6.6.4 CAS Latency The READ latency, or CAS latency, is the delay between the registration of a READ command and the avai lability of the first piece of output data. The latency is set using bits A4-A6. If a READ command is registered at clock edge n, and the latency is m clocks, the d ata will be available nominally coincident with clock edge n + m. The high-speed option for CAS latencies of 13 to 20 shall be deleted or deactivated. 6.6.5 W rite Latency The WRITE latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of input data. The latency is set using bits A9 -A11. If a WRITE command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coinciden t with clock edge n + m. - 44 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.6.6 DLL Reset The normal operating mode is selected by issuing a MODE REGISTER SET comma nd with bit A8 set to zero, and bits A0-A7 and A9-A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0-A7 and A9-A12 set to the desired values. The regis ter bit is self clearing meaning that it returns back to the value ‗0‘ after the DLL reset function has been issued. 6.6.7 Test mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to ‗0‘, and bitsA0 -A6 and A8A11 set to the desired values. Programming bit A7 to ‗1‘ places the device into a test mode that isonly to be used by the DRA M manufacturer. No functional operation is specified with test mode enabl ed. 6.7 Extended Mode Register Set Command (EMRS1) The Extended Mode Register is used to control multiple operation modes of the device. The most important one is the organization as a 1-CS or a 2-CS device. Furthermore, it is used to set the output driver impedance value, the termination impedance value, the Write Recovery time value for Write with Autoprecharge. It is used as well to enable/disable the DLL, to issue the Vendor ID. There is no default value for the Extended Mode Register. Therefore it must be written after power up to operate the GDDR3 Gra phics RAM. The Extended Mode Register can be programmed by performing a normal Mode Register Set operation and setting the BA0 bit to HIGH. All other bits of the EMR register are reserved and should be set to LOW. The Extended Mode Register must be loaded when all banks are idle and no burst are in progress. The controller must wait the specified time tMRD before initiating any subsequent operation (Figure : Extended Mode Register 1). The timing of the EMRS command operation is equivalent to the timing of the MRS command operation.To apply an EMRS command, CS0 has to be used. - 45 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.7.1 Extended Mode Register Set Command CLK# CLK CKE CS# RAS# CAS# WE# A0-A11 BA0 BA1 BA2 (High) COD 1 0 Mode COD: Code to be loaded into the register. = Don't Care 6.7.2 Extended Mode Register 1 (EMRS1) The Extended Mode Register 1 controls operating modes such as output driver impedance, data termination, address/command termination, DLL on/off, Write recovery and Vendor ID as shown in Figure. It also selects between 1-CS mode and 2-CS mode configuration. The register is programmed via the MODE REGISTER SET command with BA0=1, BA1=0 and BA2 set to the desired configuration. - 46 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.7.2.1 Extended Mode Register 1 (EMRS1) BA2 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode 0 1 RFU Vendor ID ADD/CMD Ternination WR DLL Write Recovery Data Termination OCD Impedance BA2 0 1 Chip Select Mode A10 0 1 Vendor ID A6 0 1 DLL On (*) Off A1 0 0 1 1 A0 0 1 0 1 OCD Impedance 1-CS 2-CS Off (*) On Autocal (*) 35 ohms 40 ohms 45 ohms A9 0 0 1 1 A8 0 1 0 1 ADD/CMD Ternination A7 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Write Recovery A3 0 0 1 1 A2 0 1 0 1 Data Termination ZQ/4 ZQ/2 ZQ/2 (*) ZQ (*) = Default value at power-up 11 4 5 6 7 8 9 10 (*) disabled RFU ZQ/4 ZQ/2 (*) Notes : 1. Default termination values at Power Up. 2. The ODT disable function disables all terminators on th device. 3. If the user activates bits in the extended mode register in an optional field, either the optional field is activated (if option implemented in the device) or no action is taken by the device (if option not implemented). 4. WR (write recovery time for auto precharge) in clock cycles is calculated by dividing tWR (in ns) and rounding up to the next integer (WR[cycles] = tWR[ns] / tCK[ns]). The mode register must be programmed to this value. - 47 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.7.2.2 Extended Mode Register Set Timing CLK# CLK Command PA NOP EMRS NOP NOP A.C. tRP tMRD EMRS : Extended MRS command PA A.C. : PREALL command : Any command Don't Care 6.7.3 Chip Select Mode Mode 1-CS Mode, non-merged 2-CS Mode 1-CS Mode, merged EMRS1[BA2] 0 0 1 1 EMRS2[A5] 0 1 0 1 Pin for CS1# NA J -3 NA Pin for A12 J -2 NA J -3 6.7.4 DLL The DLL is enabled by default. If DLL -off operation is desired, the DLL must be disabled by setting bit A6 to '1'. Once enabled, the DLL requires 1000 cycles to lock. 6.7.5 W rite Recovery The programmed WR value is used for the auto precharge feature along with tRP to determine tDAL. W R must be programmed with a value greater than or equal to [RU{tWR/tCK}], where RU stands for round up, tWR is the analog value and tCK is the operating clock cycle time. The high-speed option for Write Recovery values of 11 to 20 shall be deleted or deactivated. 6.7.6 Termination Rtt The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports ZQ / 4 and ZQ / 2 termination values. The termination may also be disabled for testing and other purposes. Data -, address - and command - termination are disabled in parallel. The Termination Rtt are controlled independently from the Output Driver Impedance values. - 48 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.7.7 Impedance Autocalibration of Output Buffer and Active Terminator GDDR3 GRAPHICS SDRAMs offer autocalibrating impedance output buffers and on -die terminations (ODT). This enables auser to match the driver impedance and terminations to the system within a given range. To adjust the impedance, an external precision resistor shall be connected between the ZQ pin and VSSQ. A nominal resistor value of 240 is equivalent to 40 Pulldown, 40 Pullup and 60 ODT nominal impedances. If no resistance is connected to the ZQ pin, a default value of 240 is assumed and no calibration is performed. The output driver and on-die termination impedances are updated during all REFRESH commands to compensate for variations in supply voltage and temperature. The impedance updates are transparent to the system. Table provides an overview of the ODT settings controlled by EMRS1. 6.7.7.1 Impedance Options Signal CLK,CLK#,RES,MF,SEN CKE,CS0#,CS1#,RAS#,CAS#,WE#,BA0BA2,A0-A12 DM0-DM3,WDQS0-WDQS3 DQ0-DQ31 RDQS0-RDQS3 ODT Activation No ODT Always on Always on Always on except for Reads (bus snooping) No ODT EMRS1 Control Bits A8-A9 A2-A3 A2-A3 - 6.7.7.2 Timing of Vendor Code and Revision ID Generation on DQ[7:0] 0 1 2 3 4 5 6 7 8 9 10 CLK# CLK Com. A[9:0],A11 A10 tRIDon tRIDoff EMRS N/D N/D N/D N/D N/D EMRS N/D N/D N/D N/D Add Add RDQS DQ[7:0] Vender Code and Revision ID EMRS : Extended Mode Register Set Command Add : Address N / D : NOP or Deselect Don‘t care - 49 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.7.8 Output Driver Impedance Bits A0 and A1 define the driver strength. The Auto Calibration setting enables the Auto-Calibration functionality for the Pulldown, Pullup and Termination over process, temperature and voltage changes. The 35 Ω, 40Ω and 4Ω5 options enable factory settings for the Pulldown, Pullup driver strength and termination. With any of those options enabled, driver strength and termination are expected to change with process, voltage and temperature. AC timings are only guaranteed with Auto Calibration. 6.7.9 Data Termination Bits A2 and A3 define the data termination value for the on-die termination (ODT) for the DQ pins in combination with the driver strength setting. The termination can be set to a value of ZQ/4 or ZQ/2; it may also be turned off. 6.7.10 Address command termination Bits A8 and A9 define the address/command termination. The termination can be set to a value of ZQ/4, ZQ/2 or ZQ. The setting overwrites the value defined upon power-up initialization. 6.8 Extended Mode Register 2 Set Command (EMRS2) The Extended Mode Register 2 is used to control OCD/ODT impedance offsets. It can be programmed by performing a normal Mode Register Set operation and setting the BA1 bit to HIGH and BA0, BA2 bits to LOW. The Extended Mode Register 2 must be loaded when all banks are idle and no burst are in progress. The controller must wait the specified time tMRD before initiating any subsequent operation. The timing of the EMRS2 command operation is equivalent to the timing of the MRS command operation. - 50 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.8.1 Extended Mode Register 2 Set Command CLK# CLK CKE CS# RAS# CAS# WE# A0-A11 COD BA1 1 COD : Code to be loaded into the register BA0,2 0 Don‘t care 6.8.2 Extended Mode Register 2 (EMRS2) The Extended Mode Register 2 controls output driver and termination offs ets and Merged Mode as shown in Figure. The register is programmed via the MODE REGISTER SET command with BA0=0, BA1=1 and BA2=0. The Application Mode function (mid range vs. high speed) on bit A0 and the temperature sensor self refresh function on bit A1 shall be deleted or deactivated. - 51 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.8.2.1 Extended Mode Register 2 (EMRS2) BA 2 BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 OCD Pulldown Offset ODT Pullup Offset Merged Mode Reserved A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 OCD PD Offset 0 (*) +1 +2 +3 RFU -3 -2 -1 A8 0 0 0 0 1 1 1 1 A7 0 0 1 1 0 0 1 1 A6 0 1 0 1 0 1 0 1 ODT PU Offset 0 (*) +1 +2 +3 RFU -3 -2 -1 A5 0 1 Merged Mode Non-Merged (*) Merged (*) = Default value at power-up 6.8.2.2 Impedance Offsets The driver and termination impedances may be offset individually for output driver and data termination. The offset impedance step values correspond to a nominal value of TBD. With negative offset steps the drive strengths will be decreased and Ron will be increased. With positive offset steps the drive strengths will be increased and Ron will be decreased. 6.8.2.3 Merged Mode Merged Mode combines the specific pins of 1-CS Mode (A12) and 2-CS Mode (CS1#) on a single physical pin (J-3). 6.8.3 OCD Pull Down Offset The 1G GDDR3 add the ability to add an offset to the Output impedance driver set using the bit A[1:0] of the EMRS. A range from -3 to +3 can be chosen using A[11:9]. Each steps correspond to an approximate change of 1 Ohms. The offset will be applied also on Autocal value if selected. The offset will be applied also on Autocal value if selected. W ith negative offset steps the Driver Strength will be decreased and the Ron will be increased. With positive offset steps the Driver Strength will be increased and Ron will be decreased. 6.8.4 ODT Pull Up Offset The 1G GDDR3 add the ability to add an offset to the ODT set using the bit A[3:2] of the EMRS. A range from -3 to +3 can be chosen using A[8:6]. Each steps correspond to an approximate change of 1.5 Ohms. W ith negative offset steps the Termination value will be increased. With positive offset steps the Termination value will be decreased. - 52 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.9 Extended Mode Register 3 (EMRS3) All functions originally controlled by EMRS3 like alternate CL/WR, RDBI , WDBI and Multi-Cycle Preamble (MPR) shall be deleted or deactivated, or shall be permanentely set (autocal enabled, nominal VINT). 6.10 Vendor Code and Revision ID When the Vendor Code function is enabled by bit A10, the GDDR3 GRAPHICS SDRAM will provide the vendor code on DQ[3:0] and the revision identification on DQ[7:4] as shown in Table. The Revision ID shall be made programmable on a single metal layer ( TBD). 6.10.1 Vendor ID Code Default Revision ID (DQ7-DQ4) 0000 Manufacturer ID (DQ3-DQ0) 1000 - 53 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.11 Bank / Row Activation (ACT) Before a READ or W RITE command can be issued to a bank, a row in that bank must be opened. This is accomplished via the ACT command, which selects both the bank and the row to be activated.After opening a row by issuing an ACT command, a READ command may be issued after tRCDRD to that row or a WRITE command after tRCDW R. A subsequent ACT command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACT commands to the same bank is defined by tRC. A subsequent ACT command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACT commands to ACT commands to banks in the same rank is defined by tRRD, and to banks in different ranks by tRRD_RR (see Figure:Bank Activation Timing on different rank in 2-CS mode).There is a minimum time tRAS between opening and closing a row. For the 1-CS Mode (1Gb) an additional address bit is available (A12). Internally this additional address bit is converted into a selection signal for one or the other internal rank representing the first or the second half of the 512 Mb. Subsequent column accesses to the activated bank are steered to the internal rank as selected by A12 during activation of the bank. 6.11.1 Activating a specific row CLK# CLK CKE CS# RAS# CAS# WE# A0-A11 RA RA : Row address BA : Bank Address Don‘t care BA0-BA2 BA - 54 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.11.2 Bank Activation Timing CLK# CLK Com. A0-A11 BA0,BA1 ACT Row B.Y tRCD tRAS tRC tRRD R/W Col B.Y PRE A8 B.Y ACT Row B.Y ACT Row B.X Row: Row Address Col: Column Address B.X: Bank X B.Y: Bank Y R/W: READ or WRITE command PRE: PRECHARGE command ACT: ACTIVATE command Don‘t care 6.11.3 Bank Activation Timing on different rank in 2-CS mode CLK# CLK Com. A0-A11 BA0,BA1 ACT Row B.Y tRCD tRAS tRC tRRD_RR=1 R/W Col B.Y PRE A8 B.Y ACT_0 ACT_1 Row B.Y Row B.X Row: Row Address Col: Column Address B.X: Bank X B.Y: Bank Y R/W: READ or WRITE command PRE: PRECHARGE command ACT_0: ACTIVATE command Rank 0 ACT_1: ACTIVATE command Rank 1 Don‘t care For eight bank GDDR3 devices, there may be a need to limit the number of activates in a rolling window to ensure that the instantaneous current supplying capability of the devices is not exceeded. To reflect the true capability of the DRAM instantaneous current supply, the parameter tFAW (four activate window) is defined. No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up the next integer value. As an example of the rolling window, if (tFAW / tCK) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clocks n+1 through n+9. tFAW is only valid within one rank. There is no further restriction between ranks. 6.11.4 Four Window Active tFAW CLK# CLK CMD ACT tRRD ACT tRRD ACT tRRD tFAW ACT ACT tRRD ACT tRRD ACT tRRD ACT tFAW+3*tRRD ACT:ACTIVATE command Don‘t care - 55 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.11.5 Clock, CKE and command / Address Timings tCK tCH tCL CLK# CLK tIPW CMD, ADDR, CKE tIS tIH Don‘t care Setup and Hold Timing for CKE is equal to CMD and ADDR Setup and Hold Timing. 6.12 Bank Activations with REFRESH 6.12.1 Bank Activations with REFRESH Command Operating Mode 1-CS Mode 2X REF Mode off on off on Bank Refreshed per REF Command 4 even or 4 odd banks in all 4 quedrants All 8 banks in all 4 quadrants 4 even or 4 odd banks in selected rank (rank 0 or rank 1) or in both ranks All 8 banks in selected rank (rank 0 or rank 1) or in both ranks Effective tRET 32ms 16ms 32ms 16ms 2-CS Mode - 56 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.13 Writes (WR) 6.13.1 W rite - Basic Information Write bursts are initiated with a WR command, as shown in Figure. The column and bank addresses are provided with the W R command, and Auto Precharge is either enabled or disabled for that access. The length of the burst initiated with a W R command is four or eight depending on the mode register setting. There is no interruption of WR bursts. The two least significant address bits A0 and A1 are ―Don‘t Care‖. For W R commands with Autoprecharge the row being accessed is precharged tWR/A after the completion of the burst. If tRAS(min) is violated the begin of the internal Autoprecharge will be performed one cycle after tRAS(min) is met. WR, the write recovery time for write with Autoprecharge can be programmed in the Mode Register. Choosing high values for WR will prevent the chip to delay the internal Autoprecharge in order to meet tRAS(min). During W R bursts data will be registered with the edges of WDQS. The write latency can be programmed during Extended Mode Register Set. The first valid data is registered with the first valid rising edge of W DQS following the WR command. The externally provided W DQS must switch from HIGH to LOW at the beginning of the preamble. There is also a postamble requirement before the WDQS returns to HIGH. The WDQS signal can only transition when data is applied at the chip input and during pre- and postambles. tDQSS is the time between WR command and first valid rising edge of WDQS. Nominal case is when W DQS edges are aligned with edges of external CLK. Minimum and maximum values of tDQSS define early and late W DQS operation. Any input data will be ignored before the first valid rising W DQS transition. tDQSL and tDQSH define the width of low and high phase of WDQS. The sum of tDQSL and tDQSH has to be tCK. Back to back W R commands are possible and produce a continuous flow of input data. For back to back W R, tCCD has to be met. Any W R burst may be followed by a subsequent RD command. Figure (W rite followed by Read) shows the timing requirements for a W R followed by a RD. In this case the delay between the W R command and the following RD may be zero for access across the two 8 bank segments (tWTR_RR = 1 tCK) as shown in Figure (W rite followed by Read on different ranks in 2-CS mode). A W R may also be followed by a PRE command to the same bank. tWR has to be met as shown in Figure (W rite followed by Precharge on same bank). Setup and hold time for incoming DQs and DMs relative to the WDQS edges are specified as tDS and tDH. DQ and DM input pulse width for each input is defined as tDIPW. The input data is masked if the corresponding DM signal is high. All iming parameters are defined with graphics DRAM terminations on. - 57 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.13.1.1 W rite Command CLK# CLK CKE CS# RAS# CAS# WE# A2-A7,A9 A0,A1 A10-A11 A8 BA0,BA1 CA AP CA : Colimn address BA : Bank Address Don‘t care BA 6.13.1.2 Mapping of W DQS and DM Signals WDQS WDQS0 WDQS1 WDQS2 WDQS3 Data mask signal DM0 DM1 DM2 DM3 Controlled DQs DQ0 - DQ7 DQ8 - DQ15 DQ16 - DQ23 DQ24 - DQ31 - 58 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.13.1.3 Basic Write Burst / DM Timing CLK# CLK nominal WDQS tDQSS tWPRE tDQSH tDS tDH tDQSL tDQSH tDS tDH tWPST Preamble Postamble tDQSS nominal WDQS tDIPW DQ D0 D1 tDS tDH D2 D3 DMx Data masked min(tDQSS) tDIPW Data masked early WDQS WDQS late WDQS WDQS max(tDQSS) Don‘t care DMx:Represents one DM line Note: W DQS can only transition when data is applied at the chip input and during pre- and postambles. - 59 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.14 Write - Basic Sequence CLK# CLK Com. Addr. 0 1 2 3 4 5 6 7 8 WR N/D DES DES DES DES DES DES DES B/C WL = 3 WDQS DQ WL = 4 WDQS DQ D0 D1 D2 D3 D0 D1 D2 D3 Com. Addr. WR N/D NOP NOP NOP NOP NOP NOP NOP B/C WL = 3 WDQS DQ WL = 4 WDQS DQ B / C: Bank / Column address WR : WRITE NOP : No Operation D0 D1 D2 D3 D0 D1 D2 D3 DES : Deselect N/D : NOP or DES Com. : Command Addr. : Address B / C D# : Data to B / C WL : Write Latency Don’t care Notes : 1. Shown with nominal value of tDQSS. 2. WDQS can only transition when data is applied at the chip input and during pre- and postambles. 3. When NOPs are applied on the command bus, the W DQS and the DQ busses remain stable High. 4. When DESs are applied on the command bus, the status of the WDQS and DQ busses is unknown. - 60 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.15 Write - Consecutive Bursts 6.15.1Gapless Bursts 6.15.1.1 Gapless Write Bursts 0 CLK# CLK Com. WR N/D WR N/D DES DES DES DES DES DES 1 2 3 4 5 6 7 8 9 Addr. B/Cx B/Cy WL = 3 WDQS DQ Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3 WL = 4 WDQS DQ Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3 WR : WRITE DES : Deselect N/D : NOP or DES B / Cx: Bank / Column address B / Cy: Bank / Column address WL : Write Latency Don‘t care Dx# : Data to B / Cx Dy# : Data to B / Cy Com. : Command Addr. : Address B / C Notes : 1. Shown with nominal value of tDQSS. 2. The second W R command may be either for the same bank or another bank. 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles. - 61 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.15.2 Bursts with Gaps 6.15.2.1 Consecutive Write Bursts with Gaps 0 CLK# CLK Com. Addr. WR N/D N/D WR N/D DES DES DES DES DES DES 1 2 3 4 5 6 7 8 9 10 B/Cx B/Cy WL = 3 WDQS DQ Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3 WL = 4 WDQS DQ Dx0 Dx1 Dx2 Com. : Command Addr. : Address B / C WL : Write Latency Dx3 Dy0 Dy1 Dy2 Dy3 DES : Deselect N/D : NOP or DES WR : WRITE B / Cx: Bank / Column address B / Cy: Bank / Column address Dx# : Data to B / Cx Dy# : Data to B / Cy Don’t care Notes : 1. Shown with nominal value of tDQSS. 2. The second W R command may be either for the same bank or another bank. 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles. - 62 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.15.3 W rite with Autoprecharge 0 CLK# CLK Com. A9 , A 7 -A 2 A8 WR/A 1 2 3 4 5 6 7 8 9 10 N/D DES DES DES DES DES DES DES DES DES B/C WL = 3 WDQS tWR/A=3 tRP DQ D0 D1 D2 D3 tRASMIN satisifed Begin of Autoprecharge WL = 4 WDQS tWR/A=3 tRP DQ D0 D1 D2 D3 tRASMIN satisifed Com. : Command Addr. : Address B / C WL : Write Latency Don‘t care Begin of Autoprecharge B / C: Bank / Column address WR/A : WRITE with auto-precharge D# : Data to B / C DES : Deselect N/D : NOP or DES Notes : 1. Shown with nominal value of tDQSS. 2. tWR/A starts at the first rising edge of CLK after the last valid edge of WDQS. 3. tRP starts after tWR/A has been expired. 4. When issuing a W R/A command please consider that the tRAS requirement also must be met at the beginning of tRP. 5. tWR/A ≥ tWR. 6. WDQS can only transition when data is applied at the chip input and during pre- and postambles. - 63 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.15.4 W rite followed by Read 0 CLK# CLK Com. WR 1 2 3 4 5 6 7 8 9 N/D DES DES DES DES DES DES RD N/D Addr. B/C B/C WL = 3 WDQS DQ D0 D1 D2 D3 tWTR Com. WR N/D DES DES DES DES DES DES DES RD Addr. B/C B/C WL = 4 WDQS DQ D0 D1 D2 D3 D# : Data to B / C Com. : Command Addr. : Address B / C WL : Write Latency Don‘t care tWTR B / C: Bank / Column address WR : WRITE RD : READ DES : Deselect N/D : NOP or DES Notes : 1. Shown with nominal value of tDQSS. 2. The RD command may be either for the same bank or another bank. 3. WDQS can only transition when data is applied at the chip input and during pre- and postambles. - 64 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.15.5 W rite followed by Read on different ranks in 2-CS mode 0 CLK# CLK Com. DES 1 2 3 4 5 6 7 11 12 13 14 15 WR_0 RD_1 N/D DES DES DES DES DES DES DES DES DES tWTR_RR=1 CL = 9 Addr. B/C B/C WL = 3 WDQS RDQS DQ Com. DES WR RD N/D D0 DES D1 D2 DES D3 DES DES DES D0 DES D1 D2 DES D3 DES DES tWTR_RR=1 CL = 9 Addr. B/C B/C WL = 4 WDQS RDQS DQ D0 D1 D2 D3 D# : Data to B / C Com. : Command Addr. : Address B / C WL : Write Latency Don‘t care D0 D1 D2 D3 B / C: Bank / Column address WR_0 : WRITE on Rank 0 RD_1 : READ on Rank 1 DES : Deselect N/D : NOP or DES Notes : 1. tWTR_RR is defined between write and read command on different rank. 2. Shown with nominal value of tDQSS. 3. The RD command may be either for the same bank or another bank. 4. WDQS can only transition when data is applied at the chip input and during pre- and postamble. - 65 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.15.6 W rite followed by DTERDIS 0 CLK# CLK Com. Addr. WR WR 1 2 3 4 5 6 7 8 9 10 DTD DES DES DES DES DES DES DES DES DES B/C CL = 7 WL = 3 WDQS DQ Com. Addr. D0 WR N/D DTD DES D1 D2 DES D3 DES DES DES DES DES DES B/C WL = 4 WDQS DQ D0 CL = 7 D1 D2 D3 B / C: Bank / Column address WR : WRITE DTD : DTERDIS D# : Data to B / C Com. : Command Addr. : Address B / C WL : Write Latency CL : CAS Latency DES : Deselect N/D : NOP or Deselect Don‘t care Data Termination off Notes : 1. Shown with nominal value of tDQSS. 2. WDQS can only transition when data is applied at the chip input and during pre- and postambles. 3. A margin of one clock has been introduced in order to make sure that the data termination are still on when the last Write data reaches the memory. 4. The minimum distance between Write and DTERDIS is one clock. - 66 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.15.7 W rite with Autoprecharge followed by Read / Read with Autoprecharge on another bank 0 CLK# CLK Com. A9 , A2-A7 A8 WR/A N/D DES DES DES DES DES DES RD RD/A DES 1 2 3 4 5 6 7 8 9 B/C B/C tWTR tWTR WL = 3 WDQS tWR/A tRP DQ D0 D1 D2 D3 Begin of Autoprecharge Com. A9, A 2 -A 7 A8 WR/A N/D DES DES DES DES DES DES DES RD RD/A B/C B/C tWTR WL = 4 WDQS tWR/A tRP DQ D0 D1 D2 D3 Com. : Command Addr. : Address B / C WL : Write Latency Don‘t care 0 : RD, 1 : RD/A Begin of Autoprecharge B / C: Bank / Column address WR/A : WRITE with Autoprecharge RD RD/A : READ or READ with Autoprecharge D# : Data to B / C DES : Deselect N/D : NOP or Deselect Notes : 1. Shown with nominal value of tDQSS. 2. The RD command is only allowed for another activated bank. 3. tWR/A is set to 4 in this example. 4. WDQS can only transition when data is applied at the chip input and during pre- and postambles. - 67 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.15.8 W rite followed by Precharge on same bank 0 CLK# CLK WR 1 2 3 4 5 6 7 8 9 10 Com. Addr. N/D DES DES DES DES DES DES DES PRE DES B/C B WL = 3 WDQS tWTR tRP DQ D0 D1 D2 D3 DES Com. WR N/D DES DES DES DES DES DES DES PRE Addr. B/C B WL = 4 WDQS tWTR tRP DQ D0 D1 D2 D3 Addr. : Address B / C WL : Write Latency Don‘t care B / C: Bank / Column address WR : WRITE PRE : PRECHARGE Dx# : Data to B / Cx Dy# : Data to B / Cy N/D : NOP or Deselect DES : Deselect Com. : Command Notes : 1. Shown with nominal value of tDQSS. 2. WR and PRE commands are to same bank. 3. tRAS requirement must also be met before issuing PRE command. 4. WDQS can only transition when data is applied at the chip input and during pre- and postambles. - 68 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16 Reads (RD) 6.16.1 Read - Basic Information Read bursts are initiated with a RD command, as shown in Figure (Basic Read Burst Timing). The column and bank addresses are provided with the RD command and Autoprecharge is either enabled or disabled for that access. The length of the burst initiated with a RD command is 4 or 8. There is no interruption of RD bursts. The two least significant start address bits are ―Don‘t Care‖. If Autoprecharge is enabled, the row being accessed will start internal precharge at the latter of either the completion of bits prefetch or one cycle after tRAS(min) is met. During RD bursts the memory device drives the read data edge aligned with the RDQS signal which is also driven by the memory. After a programmable CAS latency of 7, 8, 9 or 10 the data is driven to the controller. RDQS leaves HIGH state one cycle before its first rising edge (RD preamble tRPRE). After the last falling edge of RDQS a postamble of tRPST is performed. tAC is the time between the positive edge of CLK and the appearance of the corresponding driven read data. The skew between RDQS and the crossing point of CLK/CLK# is specified as tDQSCK. tAC and tDQSCK are defined relatively to the positive edge of CLK. tDQSQ is the skew between a RDQS edge and the last valid data edge belonging to the RDQS edge. tDQSQ is derived at each RDQS edge and begins with RDQS transition and ends with the last valid transition of DQs. tQHS is the data hold skew factor and tQH is the time from the first valid rising edge of RDQS to the first conforming DQ going non-valid and it depends on tHP and tQHS. tHP is the minimum of tCL and tCH. tQHS is effectively the time from the first data transition (before RDQS) to the RDQS transition. The data valid window is derived for each RDQS transition and is defined as tQH minus tDQSQ. After completion of a burst, assuming no other commands have been initiated, data will go HIGH and RDQS will go HIGH. Back to back RD commands are possible producing a continuous flow of output data. For back to back RD, tCCD has to be met. Any RD burst may be followed by a subsequent W R command. The minimum required number of NOP commands between the RD command and the W R command (tRTW) depends on the programmed CAS latency and the programmed W rite latency tRTW(min)= (CL+4-W L) , the timing requirements for RD followed by a WR with some combinations of CL and WL. A RD may also be followed by a PRE command. Since no interruption of bursts is allowed the minimum time between a RD command and a PRE is two clock cycles . All timing parameters are defined with controller terminations on. - 69 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.1.1 Read Command CLK# CLK CKE CS# RAS# CAS# WE# A2-A7,A9 A0,A1 A10-A11 A8 CA AP BA0-BA2 BA AP : AutoPrecharge CA : Row address BA : Bank Address Don‘t care - 70 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.1.2 Basic Read Burst Timing tCH tCL tCK tHP CLK# CLK RDQS Preamble tRPRE tDQSCK Postamble tRPST DQ (first data valid) DQ (last data valid) tAC D0 D0 D1 D1 D2 D2 D3 D3 All DQs collectively D0 tDQSQ tQH tQHS tLZ D1 Data Valid window D2 tDQSQ D3 Don‘t care Hi-Z : Not driven By DDRⅢ SGRAM tHZ Notes : 1. The GDDR3 GRAPHICS SDRAM switches off the DQ terminations one cycle before data appears on the bus and drives the data bus HIGH. 2. The GDDR3 GRAPHICS SDRAM drives the data bus HIGH one cycle after the last data driven on the bus before switching the termination on again. - 71 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.2 Read - Basic Sequence 6.16.2.1 Read Burst 0 CLK# CLK Com. RD N/D N/D N/D N/D N/D N/D N/D N/D N/D 1 2 3 6 7 8 9 10 11 Addr. B/C CAS latency = 5 RDQS DQ D0 D1 D2 D3 CAS latency = 6 RDQS DQ D0 D1 D2 D3 RD : READ N/D : NOP or Deselect Don‘t care DQs : Terminations off RDQS : Not driven B / C: Bank / Column address Dx : Data from B / C Com. : Command Addr. : Address B / C Notes : 1. Shown with nominal tAC and tDQSQ. 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data. - 72 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.3 Consecutive Read Bursts 6.16.3.1 Gapless Bursts 6.16.3.1.1 Gapless Consecutive Read Bursts 0 CLK# CLK Com. Addr. RD N/D RD B/Cy CAS latency = 5 N/D N/D N/D N/D N/D N/D N/D N/D N/D 1 2 3 6 7 8 9 10 11 12 13 B/Cx RDQS DQ Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3 CAS latency = 6 RDQS DQ Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3 B / Cx: Bank / Column address B / Cy: Bank / Column address Dx# : Data from B / Cx Dy# : Data from B / Cy Com. : Command Addr. : Address B / C RD : READ N/D : NOP or Deselect Don‘t care DQs : Terminations off RDQS : Not driven Notes : 1. The second RD command may be either for the same bank or another bank. 2. Shown with nominal tAC and tDQSQ. 3. Example applies only when READ commands are issued to same device. 4. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 5. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data. - 73 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.4 Bursts with Gaps 6.16.4.1 Consecutive Read Bursts with Gaps 0 CLK# CLK Com. RD N/D N/D RD N/D N/D N/D N/D N/D N/D N/D 1 2 3 6 7 8 9 10 11 12 Addr. B/Cx CAS latency = 5 B/Cy RDQS DQ CAS latency = 6 Dx0 Dx1 Dx2 Dx3 Dy0 Dy1 Dy2 Dy3 RDQS DQ Dx0 Dx1 Dx2 Dx3 Dy0 Don‘t care Dy1 Dy2 B / Cx: Bank / Column address x B / Cy: Bank / Column address y RD : READ Dx# : Data from B / Cx Dy# : Data from B / Cy Com. : Command Addr. : Address B / C DQs : Terminations off RDQS : Not driven Notes : 1. The second RD command may be either for the same bank or another bank. 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data. - 74 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.5 Read followed by DTERDIS Notes : 1. At least BL/2+1 NOPs are required between a READ command and a DTERDIS command in order to avoid contention on the RDQS bus in a 2 memories system. 2. CAS Latency 7 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of BL/2+2 clocks. 4. The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command corresponds to a Read command applied to the second Graphics DRAM in a 2 memories system. In this case, RDQS would be driven by the second Graphics DRAM. - 75 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.6 Read with Autoprecharge Notes : 1. When issuing a RD/A command, the tRAS requirement must be met at the beginning of Autoprecharge. 2. Shown with nominal tAC and tDQSQ 3. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 4. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data. 5. tRAS Lockout support. - 76 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.7 Read followed by W rite Notes : 1. Shown with nominal tAC, tDQSQ and tDQSS. 2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. 3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data. 4. WDQS can only transition when data is applied at the chip input and during pre- and postambles. 5. The Write command may be either on the same bank or on another bank. - 77 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.16.8 Read followed by Precharge on the same Bank Notes : 1. tRAS requirement must also be met before issuing PRE command. 2. RD and PRE commands are applied to the same bank. 3. Shown with nominal tAC and tDQSQ. 4. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS. - 78 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.17 Data Termination Disable (DTERDIS) The Data Temination Disable command is detected by the device by snooping the bus for Read commands when CS is high. The terminators are disabled starting at CL - 1 clocks after the DTERDIS command is detected and the duration is 4 clocks. The command and address terminators are always enabled. DTERDIS may only be applied to the GDDR3 Graphics memory if it is not in the Power Down or in the Self Refresh state. The timing relationship between DTERDIS and other commands is defined by the constraint to avoid contention on the RDQS bus (i.e Read to DTERDIS transition) or the necessity to have a defined termination on the data bus during W rite (i.e. W rite to DTERDIS transition). ACT and PRE/PREALL may be applied at any time before or after a DTERDIS command. 6.17.1 Data Terminal Disable Command - 79 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 617.1.1 DTERDIS Timing - 80 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.17.2 DTERDIS followed by DTERDIS Notes : 1. At least 1NOP is required between 2 DTERDIS commands. This correspond to a Read to Read transition on the other memory in a 2 memories system. 2. CAS Latency 7 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4 clocks. 4.The dashed lines (RDQS bus) describe the RDQS behavior in the case where the DTERDIS command corresponds to a Read command applied to the second Graphics DRAM in a 2 memories system. In this case, RDQS would be driven by the second Graphics DRAM. - 81 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.17.3 DTERDIS followed by READ Notes : 1. At least BL/2+1 NOPs are required between a DTERDIS command and a READ command in order to avoid contention on the RDQS bus in a 2 memories system. 2. CAS Latency 7 is used as an example. 3. The DQ terminations are switched off (CL-1) clock periods after the DTERDIS command for a duration of 4 clocks. - 82 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.17.4 DTERDIS followed by W rite Notes : 1. Write shown with nominal value of tDQSS. 2. WDQS can only transition when data is applied at the chip input and during pre- and postambles. 3. The minimum distance between DTERDIS and Write is (CL - W L + BL/2 +2) clocks. - 83 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.18 Precharge (PRE/PREALL) The Precharge command is used to deactivate the open row in a particular bank (PRE) or the open rows in all banks (PREALL). The bank(s) will enter the idle state and be available again for a new row access after the time tRP. A8/AP sampled with the PRE command determines whether one or all banks are to be precharged. For PRE commands BA0, BA1 and BA2 select the bank. For PREALL inputs BA0, BA1 and BA2 are ―Don‘t Care‖. The PRE/PREALL command may not be given unless the tRAS requirement is met for the selected bank (PRE), or for all banks within one rank (PREALL). 6.18.1 Precharge Command - 84 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.18.2 BA2, BA1 and BA0 precharge bank selection within one rank A8 / AP 0 0 0 0 0 0 0 0 1 BA2 0 0 0 0 1 1 1 1 X BA1 0 0 1 1 0 0 1 1 X BA0 0 1 0 1 0 1 0 1 X Precharged bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only All banks within one rank 6.18.3 Precharge Timing - 85 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.19 Auto Refresh Command (AREF) AREF is used to do a refresh cycle on one row in each bank. The addresses are generated by an internal refresh controller; external address pins are ―DON‘T CARE‖. All banks within the ranks must be idle before the AREF command can be applied. The delay between the AREF command and the next ACT or subsequent AREF must be at least tRFC(min). The refresh period starts when the AREF command is entered and ends tRFC later at which time all banks will be in the idle state. Within a period of tREF the whole memory has to be refreshed. The average periodic interval time from AREF to AREF is then tREFI. To improve efficiency bursts of AREF commands can be used. Such bursts may consist of maximum 8 AREF commands. tRFC(min) is the minimum required time between two AREF commands inside of one AREF burst. According to the number of AREF commands in one burst the average required time from one AREF burst to the next can be increased. Example: If the AREF bursts consists of 8 AREF commands, the average time from one AREF burst to the next is 8 * tREFI. The AREF command generates an update of the OCD output impedance and of the addresses, commands and DQ terminations. The timing parameter tKO . AREF affects one rank, only. Therefore, accesses to the other rank in the 2-CS-mode are allowed after tKO has expired. 6.19.1 Auto Refresh Command - 86 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.19.2 Auto Refresh Cycle 6.20 Self-Refresh 6.20.1 Self-Refresh Entry (SREFEN) The Self-Refresh mode can be used to retain data in the GDDR3 Graphics RAM even if the rest of the system is powered down. When in the Self-Refresh mode, the GDDR3 Graphics RAM retains data without external clocking. The Self-Refresh command is initiated like an Auto-Refresh command except CKE is disabled (LOW ). Self Refresh Entry is only possible if all banks are precharged and tRP is met.The GDDR3 Graphics RAM has a build-in timer to accommodate Self-Refresh operation. The SelfRefresh command is defined by having CS#, RAS#, CAS# and CKE held low with W E# high at the rising edge of the clock. Once the command is registered, CKE must be held LOW to keep the device in Self- Refresh mode. W hen the GDDR3 Graphics RAM has entered the Self-Refresh mode, all external control signals, except CKE are disabled. For power saving, the DLL and the clock are internally disable; and the address and command terminators are turned off. But the Data terminators remain on. The user may halt the external clock while the device is in Self-Refresh mode the next clock after Self-Refresh entry, however the clock must be restarted before the device can exit Self-Refresh operation. In 2-CS-mode, SR may only be entered for both ranks in parallel. Therefore CS0# and CS1# will have to be set to Low Level. - 87 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.20.1.1 Self-Refresh Entry Command - 88 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.20.1.2 Self Refresh Entry 6.21 Self-Refresh Exit (SREFEX) To exit the Self Refresh Mode, a stable external clock is needed before setting CKE high asynchronously. Once the Self-Refresh Exit command is registered, a delay equal or longer than tXSRD must be satisfied before a read command can be applied. During this time, the DLL is automatically enabled, reset and calibrated. CKE must remain HIGH for the entire Self-Refresh exit period and commands must be gated off with CS# held HIGH. Alternately, NOP commands may be registered on each positive clock edge during the Self Refresh exit interval. - 89 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.21.1 Self Refresh Exit Command 6.21.2 Self Refresh Exit - 90 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.22 Power-Down The GDDR3 requires CKE to be active at all times an access is in progress: From the issuing of a READ or WRITE command until completion of the burst. For READs, a burst completion is defined after the rising edge of the Read Postamble. For Writes, a burst completion is defined one clock after the rising edge of the Write Postamble. For Read with Autoprecharge and W rite with Autoprecharge, the internal Autoprecharge must be completed before entering PowerDown. Power-Down is entered when CKE is registered LOW . (No access can be in progress. "Access" means as well READ or WRITE to a second memory sharing the data bus in a dual rank system.) If Power-Down occurs when all banks are idle, this mode is referred to as Precharge Power-Down; if Power- Down occurs when there is a row active in any bank, this mode is referred to as Active PowerDown. Entering power- down deactivates the input and output buffers, excluding CLK, CLK# and CKE. For maximum power saving, the user has the option of disabling the DLL prior to entering power- down. In that case the DLL must be enabled and reset after exiting power-down, and 1000 cycles must occur before a READ command can be issued. In Power-Down mode, CKE low and a stable clock signal must be maintained at the inputs of the GDDR3 Graphics RAM, all the other input signals are ―Don‘t Care‖. Power down duration is limited by the refresh requirements of the device. The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESEL command). A valid executable command may be applied tXPN later. 6.22.1 Power Down Command - 91 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 6.22.2 Power-Down Mode - 92 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings and Operation Conditions 7.1.1 Absolute Maxim um Rating Rating Parameter Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Storage Temperature Junction Temperature Case Temperature Short Circuit Output Current Symbol Min. Max. 2.5 2.5 2.5 2.5 +150 +1 2 5 +105 50 V V V V °C °C °C mA Unit -0.5 -0.5 -0.5 -0.5 -55 — 0 — VDD VDDQ VIN VOUT TSTG TJ Tcase IOUT Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 7.2 DC Operation Conditions 7.2.1 Recommended Power & DC Operation Conditions 7.2.1.1 Power & DC Operation Conditions (0 °C ≤ Tc ≤ 105 °C) Limit Values Parameter Power Supply Voltage Reference Voltage Output Low Voltage Input leakage current CLK Input leakage current Output leakage current Notes : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. for 1.8 V VDD/VDDQ power supply. 4. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ± 2% VREF (DC). Thus, from 70% of VDDQ, VREF is allowed ± 19mV for DC error and an additional ± 27mV for AC noise. 5. IIL and IOL are measured with ODT disabled. Symbol Min. Typ. 1.8 — — — — — Max. 1 .9 0.71*VDDQ 0 .8 +5.0 +5.0 +5.0 Unit 1.7 0.69*VDDQ — –5.0 –5.0 –5.0 V V V μΑ μΑ μΑ Note 1,2,3 4 3 5 VDD / VDDQ VREF VOL(DC) IIL I IL C IOL 5 - 93 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.3 DC & AC Logic Input Levels 7.3.1 DC & AC Logic Input Levels (0 °C ≤ Tc ≤ 105 °C) Limit Values Parameter Input logic high voltage, DC Input logic low voltage, DC Input logic high voltage, AC Input logic low voltage, AC Input logic high, DC, RESET pin Input logic low, DC, RESET pin Input Logic High, DC, MF pin Input Logic Low,DC, MF pin Notes : 1. for 1.8 V VDD/VDDQ power supply. 2. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. 3. Input slew rate = 3 V/ns. If the input slew rate is less than 3 V/ns, input timing may be compromised. All slew rates are measured between and VIH(AC). Symbol Min. Max. — Unit Note 1 ,2 1 ,2 1 ,3 ,4 1 ,3 ,4 VIH(DC) VIL(DC) VIH(AC) VREF + 0.15 — V V V V V V V V VREF -0.15 — VREF + 0.25 — 0.65 × VDDQ -0.3 VIL(AC) VIHR(DC) VILR(DC) VIHMF(DC) VILMF(DC) VDD –0.3 VREF - 0.25 VDDQ + 0.3 0.35 × VDDQ VDD + 0.3 0 5 VIL(AC) 4. VIH overshoot: VIH(max) = VDDQ+0.5V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. VIL undershoot: VIL(min) = 0 V for a pulse width ≤ 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. 5. The MF pin must be hard-wired on board to either VDD or VSS. - 94 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.4 Differential Clock DC and AC Levels 7.4.1 Differential Clock DC and AC Input conditions (0 °C ≤ Tc ≤ 105°C) Limit Values Parameter Clock Input Mid-Point Voltage, CLK and CLK# Clock Input Voltage Level, CLK and CLK# Clock DC Input Differential Voltage, CLK and CLK# Clock AC Input Differential Voltage, CLK and CLK# AC Differential Crossing Point Input Voltage Notes : 1. All voltages referenced to VSS. 2. for 1.8 V VDD/VDDQ power supply. 3. VID is the magnitude of the difference between the input level on CLK and the input level on CLK#. 4. The value of VIX is expected to equal 0.7 × VDDQ of the transmitting device and must track variations in the DC level of the same. Symbol Min. Max. 0.7 × VDDQ + 0.10 Unit 0.7 × VDDQ – 0.10 0.42 0.3 0.5 0.7 × VDDQ – 0.15 V V V V V Note 1 1 ,2 1 1,2,3 1,2,4 VMP(DC) VIN(DC) VID(DC) VID(AC) VIX(AC) VDDQ + 0.3 VDDQ VDDQ + 0.5 0.7 × VDDQ + 0.15 7.5 Output Test Conditions VDDQ 60 ohm DQ DQS Test point - 95 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.6 Pin Capacitances 7.6.1 Pin Capacitances (VDDQ = 1.8 V, TA = 25°C, f = 1 MHz) Parameter Input capacitance: A0-A11,A12, , BA0-2, CKE, CS#, CAS#, RAS#, W E#, CKE, RES,CLK,CLK# Input capacitance: DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0-DM3 Symbol CI,CCK Min. 1.0 Max. 2.5 Unit pF Note CIO 2.0 3.0 pF 7.7 Driver current characteristics 7.7.1 Driver IV characteristics at 40 Ohms Figure represents the driver Pull-Down and Pull-Up IV characteristics under process, voltage and temperature best and worst case conditions. The actual Driver Pull-Down and Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 Ω, setting the nominal driver output impedance to 40 Ω. 7.7.1.1 40 Ohm Driver Pull-Down and Pull-up Characteristics Pull-Down Characterstics 50 45 40 35 30 25 20 15 10 5 0 0.0 0.5 1 .0 1 .5 2.0 0.0 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0.5 Pull-Up Characterstics 1.0 1.5 2.0 IOUT (mA) IOUT (mA) VOUT (V) VDDQ - VOUT (V) - 96 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Table lists the numerical values of the minimum and maximum allowed values of the output driver Pull-Down and Pull-Up IV characteristics. 7.7.1.2 Programmed Driver IV Characteristics at 40 Ohm Pull-Down Current (mA) Voltage (V) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.32 4.56 6.69 8.74 1 0 .7 0 1 2 .5 6 1 4 .3 4 1 6 .0 1 1 7 .6 1 1 9 .1 1 2 0 .5 3 2 1 .9 2 2 3 .2 9 2 4 .6 5 2 6 .0 0 2 7 .3 5 2 8 .7 0 3 0 .0 8 — — Maximum 3.04 5.98 8.82 11.56 14.19 16.72 19.14 21.44 23.61 26.10 28.45 30.45 32.73 34.95 37.10 39.15 41.01 42.53 43.71 44.89 Minimum -2.44 -4.79 -7.03 -9.18 -11.23 -13.17 -15.01 -16.74 -18.37 -19.90 .21.34 -22.72 -24.07 -25.40 -26.73 -28.06 -29.37 -30.66 — — Maximum -3 . 2 7 -6 . 4 2 -9 . 4 5 -12.37 -15.17 -17.83 -20.37 -22.78 -25.04 -27.17 -29.17 -31.25 -33.00 -35.00 -37.00 -39.14 -41.25 -43.29 -45.23 -47.07 Pull-Up Current (mA) 7.8 Termination current characteristics 7.8.1 Termination IV Characteristic at 60 Ohms Figure represents the DQ termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual DQ termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 Ω, setting the nominal DQ termination impedance to 60 Ω. (Extended Mode Register programmed to ZQ/4). - 97 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.8.1.1 60 Ohm Active Termination Characteristic 60 Ohm Termination Characteristic 0.0 0 -5 -10 0.5 1.0 1.5 2.0 IOUT (mA) -15 -20 -25 -30 -35 VDDQ - VOUT (V) Table lists the numerical values of the minimum and maximum allowed values of the output driver termination IV characteristic. 7.8.1.2 Programmed Terminator Characteristics at 60 Ohm Terminator Pull-Up Current (mA) Voltage (V) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -1.63 -3.19 -4.69 -6.12 -7.49 -8.78 -1 0 . 0 1 -1 1 . 1 6 -1 2 . 2 5 -1 3 . 2 7 Maximum -2.18 -4.28 -6.30 -8.25 -10.11 -11.89 -13.58 -15.19 -16.69 -18.11 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Minimum -14.23 -15.14 -16.04 -16.94 -17.82 -18.70 -19.58 -20.44 — — Maximum -1 9 . 4 5 -2 0 . 8 3 -2 2 . 0 0 -2 3 . 3 3 -2 4 . 6 7 -2 6 . 0 9 -2 7 . 5 0 -2 8 . 8 6 -3 0 . 1 5 -3 1 . 3 8 Terminator Pull-Up Current (mA) - 98 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.8.2 Termination IV Characteristic at 120 Ohms Figure represents the DQ or ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 Ω, setting the nominal termination impedance to 120 Ω. (Extended Mode Register programmed to ZQ/2 for DQ terminations or CKE = 0 at the RES transition during Power-Up for ADD/CMD terminations). 7.8.2.1 120 Ohm Active Termination Characteristic 120 Ohm Termination Characteristic 0.0 0 -2 -4 -6 IOUT (mA) 0.5 1.0 1. 5 2.0 -8 -10 -12 -14 -16 VDDQ - VOUT (V) - 99 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Table lists the numerical values of the minimum and maximum allowed values of the termination IV characteristic. 7.8.2.2 Programmed Terminator Characteristics of 120 Ohm Terminator Pull-Up Current (mA) Voltage (V) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -0.81 -1.60 -2.34 -3.06 -3.74 -4.39 -5.00 -5.58 -6.12 -6.63 Maximum -1.09 -2.14 -3.15 -4.12 -5.06 -5.94 -6.79 -7.59 -8.35 -9.06 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Minimum -7 . 1 1 -7 . 5 7 -8 . 0 2 -8 . 4 7 -8 . 9 1 -9 . 3 5 -9 . 7 9 -10.22 — — Maximum -9.72 -1 0 . 4 2 -1 1 . 0 0 -1 1 . 6 7 -1 2 . 3 3 -1 3 . 0 5 -1 3 . 7 5 -1 4 . 4 3 -1 5 . 0 8 -1 5 . 6 9 Terminator Pull-Up Current (mA) 7.8.3 Termination IV Characteristic at 240 Ohms Figure represents the ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and worst case conditions. The actual ADD/CMD termination Pull-Up current must lie between these two bounding curves. The value of the external ZQ resistor is 240 Ω, setting the nominal termination impedance to 240 Ω. (CKE = 1at the RES transition during Power-Up for ADD/CMD terminations). 7.8.3.1 240 Ohm Active Termination Characteristic 240 Ohm Termination Characteristic 0.0 0 -1.0 -2.0 -3.0 IOUT (mA) 0.5 1.0 1. 5 2.0 -4.0 -5.0 -6.0 -7.0 -8.0 VDDQ - VOUT (V) - 100 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Table lists the numerical values of the minimum and maximum allowed values of the ADD/CMD termination IV characteristic. 7.8.3.2 Programmed Terminator Characteristics at 240 Ohm Terminator Pull-Up Current (mA) Voltage (V) Minimum 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -0.41 -0.80 -1.17 -1.53 -1.87 -2.20 -2.50 -2.79 -3.06 -3.32 Maximum -0.55 -1.07 -1.58 -2.06 -2.53 -2.97 -3.40 -3.80 -4.17 -4.53 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 Voltage (V) Minimum -3.56 -3.79 -4.01 -4.23 -4.46 -4.68 -4.90 -5.11 — — Maximum -4.86 -5.21 -5.50 -5.83 -6.17 -6.52 -6.88 -7.21 -7.54 -7.85 Terminator Pull-Up Current (mA) - 101 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.9 Operating Current Ratings TYP. SYM. PARAMETER/CONDITION 650 One Bank Activate Precharge Current: tCK = tCK(min); tRC = tRC(min); CKE = HIGH; data bus inputs are SWITCHING; address and command inputs are SWITCHING; /CS is HIGH between valid commands One Bank Activate Read Precharge Current: tCK= tCK(min); tRC = tRC(min); CKE = HIGH; 1 bank activated; single read burst with data bus SWITCHING, address and command inputs are SWITCHING; /CS is High between valid commands; Iout = 0mA Precharge Power-Down Current: tCK = tCK(min); all banks idle; CKE = LOW; all other inputs are HIGH Precharge Standby Current in Non Power-down mode. Active Standby Current: tCK = tCK(min); 1 bank active; CKE = HIGH; all other inputs are HIGH Burst Read Current: tCK = tCK(min); CKE = HIGH; continuous read burst across banks with data bus SWITCHING; address and command inputs are SWITCHING; Iout = 0 mA Write Burst Current: tCK = tCK(min); CKE = HIGH; continuous write burst across banks with data bus SWITCHING; address and command inputs are SWITCHING Auto Refresh current at tREFI. Self Refresh Current: CKE = LOW; all other inputs are HIGH UNIT 700 800 NOTES IDD0 320 335 360 mA IDD1 IDD2P IDD2N IDD3N IDD4R IDD4W IDD5D IDD6 330 345 380 mA 2 140 190 285 495 150 200 300 520 160 220 330 550 mA mA mA mA 2 495 380 40 520 400 40 550 435 40 mA mA mA Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Measured with open outputs and ODT off. 3. LOW is defined as inputs stable at VIL(max). HIGH is defined as inputs stable at VIH(min). SWITCHING is defined as inputs changing between HIGH and LOW every clock cycle for address and command inputs, and inputs changing with 50% of each data transfer for DQ. - 102 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 7.10 AC Timings Limit Values Parameter CAS latency Symbol min CL =11 System frequency Clock cycle to cycle period jitter Clock high level width Clock low level width Minimum clock half period Address/Command input setup time Address/Command input hold time Address/Command input pulse width Mode Register Set cycle time Mode Register Set to READ timing Row Cycle Time Row Active Time ACT(a) to ACT(b) Command period ACT(a) to ACT(b) Command period (different rank) Row Precharge Time Row to Column Delay Time for Reads Row to Column Delay Time for Writes Four Active Windows within Rank CAS(a) to CAS(b) Command period Internal write to Read Command Delay Write to Read Command Delay (different rank) Write to Write Command Delay (different rank) Read to Write command delay Read to Read Command Delay (different rank) Write command to first W DQS latching transition CL =10 CL = 9 650 max — — 650 0.06 0.45 0.45 0.45 0.35 0.35 0.7 6 12 Row Timing 37 27 7 1 12 11 9 35 BL/2 6 1 2 2 WL–0.25 Unit 800 MHz max — 800 — 0.06 — — — — — — — — — — — — — — — — — — — — — WL+0.25 700 min 450 450 — 0.06 — — — — — — — — — — — — — — — — — — — — — 0.45 0.45 0.45 0.35 0.35 0.7 6 12 37 27 7 1 12 11 9 35 BL/2 6 1 2 2 — — — — — — — — — — — — — — — — — — — — — 0.45 0.45 0.45 0.35 0.35 0.7 6 12 max 700 700 — min — 450 — Note Clock and Clock Enable fCK11 fCK10 fCK9 tJIT(cc) tCH tCL tHP tIS tIH tIPW tMRD tMRDR tRC tRAS tRRD tRRD_RR tRP tRCDRD — — 450 MHz MHz MHz 1 1 1 2 ,3 2,3,4 2,3,4 3 tCK tCK tCK tCK ns ns Command and Address Setup and Hold Timing 5 ,6 5 ,6 4 tCK tCK tCK tCK tCK tCK tCK tCK tCK Mode Register Set Timing 7 ,8 7 37 27 8 1 14 13 9 12 tRCDWR tFAW tCCD tWTR tWTR_RR tWTW_RR tRTW tRTR_RR tDQSS 9 35 BL/2 6 1 2 2 tCK tCK tCK tCK tCK tCK tCK tCK tCK 10 11 10 10 14 10 Column Timing tRTW(min) = CL + BL/2+ 2 - WL Write Cycle Timing Parameters for Data and Data Strobe WL+0.25 WL–0.25 WL+0.25 WL–0.25 - 103 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Limit Values Parameter CAS latency Symbol min Data-in and Data Mask to W DQS Setup Time Data-in and Data Mask to W DQS Hold Time Data-in and DM input pulse width (each input) DQS input low pulse width DQS input high pulse width DQS Write Preamble Time DQS Write Postamble Time Write Recovery Time Data Access Time from Clock Read Preamble Read Postamble Data-out high impedance time from CLK Data-out low impedance time from CLK DQS edge to Clock edge skew DQS edge to output data edge skew Data hold skew factor Data output hold time from DQS Refresh Period (8192 cycles) Average periodic Auto Refresh interval Delay from AREF to next ACT/ AREF Self Refresh Exit time Power Down Exit time RES to CKE setup timing RES to CKE hold timing Termination update Keep Out timing Rev. ID EMRS to DQ on timing REV. ID EMRS to DQ off timing 650 max — — — — — 1.25 1.25 — 0.25 1.25 1.25 min 0.18 0.18 0.40 0.40 0.40 0.75 0.75 10 – 0 .2 5 0.75 0.75 700 max — — — — — 1.25 1.25 — 0.25 1.25 1.25 min 0.18 0.18 0.40 0.40 0.40 0.75 0.75 800 max — — — — — 1.25 1.25 — 0.25 1.25 1.25 ns ns 5,13 5,13 Unit MHz Note tDS tDH tDIPW tDQSL tDQSH tWPRE tWPST tWR tAC tRPRE tRPST tHZ tLZ tDQSCK tDQSQ tQHS tQH 0.18 0.18 0.40 0.40 0.40 0.75 0.75 10 –0.25 0.75 0.75 tCK tCK tCK tCK tCK tCK ns 11 10 – 0 .2 5 0.75 0.75 Read Cycle Timing Parameters for Data and Data Strobe tCK tCK ns ns ns ns ns ns 4 tACmin tACmin –0.25 — — tACmax tACmax 0.25 0.16 0.16 tACmin tACmin – 0 .2 5 — — tACmax tACmax 0.25 0.16 0.16 tACmin tACmin – 0 .2 5 — — tACmax tACmax 0.25 0.16 0.16 15 tHP–tQHS — 3.9 59 1000 6 10 10 10 — — — — — — — — 20 20 59 1000 6 10 10 10 — — 32 — 3.9 — — — — — — 20 20 59 1000 6 10 10 10 — — 32 — 3.9 — — — — — — 20 20 32 Refresh/Power Down Timing tREF tREFI tRFC tXSC tXPN tATS ms µs ns tCK tCK ns ns ns ns ns Other Timing Parameters tATH tKO tRIDon tRIDoff - 104 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 1. fCK(min), fCK(max) for DLL on mode. 2. CLK and CLK# input slew rate must be greater than 3 V/ns. 3. tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK,CLK# inputs. 4. Timing is calculated for a clock frequecy of 700 MHz. 5. The input reference level for signals other than CLK and CLK# is VREF. 6. Command/Address input slew rate = 3 V/ns. If the slew rate is less than 3 V/ns, timing is no longer referenced to the midpoint but to the maximum and ViH(AC) minimum points . 7. This value of tMRD applies only to the case where the "DLL reset"‘ bit is not activated. 8. tMRD is defined from MRS to any other command then READ. 9. tRAS,max is 8*tREFi. 10. tCCD is either for gapless consecutive reads or gapless consecutive writes. 11. WTR and tWR start at the first rising edge of CLK after the last valid (falling) W DQS edge of the slowest WDQS signal. 12. This parameter is defined for commands issued to rank m following rank n where m ≠ n. For all other type of access, standard timing parameters do apply. 13. DQ and DM input slew rates must not deviate from W DQS by more than 10 percent. If the DQ/DM/WDQS slew rate is less than 3 V/ns, timing is no longer referenced to the midpoint but to the Vil(AC) maximum and ViH(AC) minimum points. 14. Please round up tRTW to the next integer of tCK. 15. This parameter is defined per byte. 16. tAC +/-290ps when VDDmax. 17. Input slew rate = 2.2V/ns. If tIS/tIH higher than 550ps. Vil(AC) - 105 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 8. PACKAGE SPECIFICATION Package Outline TFBGA 136 (10x14 mm , ball pitch:0.8mm, Ø =0.45mm) 14 16 x 0.8 = 12.8 0.8 0.2 0.12 MAX. 0.18 MAX. 2 0.8 11 x 0.8 = 8.8 2.2 MAX 2) B 5) 1) 4) 2) 3) A 0.1 C 0.1 C 1.2 MAX. 0.31 MIN. O 0.45± 0.05 6) O 0.15 M O 0.08 M C C C A B SEATING PLANE Lead free solder balls (green solder balls) 1) Bad unit marking (BUM) (light = good) 2) Middle of packages edges 3) Package orientation mark A1 4) SBA- fiducial (solder ball attach) 5) Bare core area 6) Solder ball diameter refers to post reflow conduction - 106 - Publication Release Date: Apr, 22, 2011 Revision A01-002 9.2 10 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 9. ORDERING INFORMATION PART NUMBER W 641GG2JB-14 1Gb GDDR3 SDRAM DESCRIPTION Note: For pad information of KGD, please contact sales representative. - 107 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM 10. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01-001 03/28/2011 All 32 93 102 103,104 Product datasheet for customer. Add tSAC value. Add Tcase . Add 800 Mhz in DC table. Add 800 Mhz in AC table. A01-002 04/22/2011 - 108 - Publication Release Date: Apr, 22, 2011 Revision A01-002 W641GG2JB 1-Gbit GDDR3 Graphics SDRAM Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation whe rein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. ----------------------------------------------------------------------------------------------------------------------------- -------------------Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in the datasheet belong to their respective owners. - 109 - Publication Release Date: Apr, 22, 2011 Revision A01-002