W6811IRG

W6811 SINGLE-CHANNEL VOICEBAND CODEC (5V Analog, 3V Digital) Data Sheet -1- Publication Release Date: September, 2005 Revision A12 W6811 1. GENERAL DESCRIPTION The W6811 is a general-purpose single channel PCM CODEC with pin-selectable 　-Law or A-Law companding. The device is compliant with the ITU G.712 specification. It operates off of separated analog (5V) and digital (3V) power supplies and is available in 24-pin PDIP, SOG, SSOP, and TSSOP package options. Functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are compliant with ITU G.712 specification. W6811 performance is specified over the industrial temperature range of –40°C to +85°C. The W6811 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving 300Ω loads differentially up to a level of 6.3V peak-to-peak. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The data transfer protocol supports both long-frame and short-frame synchronous communications for PCM applications, and IDL and GCI communications for ISDN applications. W6811 accepts seven master clock rates between 256 kHz and 4.096 MHz, and an on-chip pre-scaler automatically determines the division ratio for the required internal clock. 2. FEATURES • • • • • • • • • • • Power supply: Analog 4.5 – 5.5V Digital 2.7 – 3.3V Typical power dissipation of 25 mW, power-down mode of 0.5 　W Fully-differential analog circuit design On-chip precision reference of 1.575 V for a 0 dBm TLP at 600 Ω Push-pull power amplifiers with external gain adjustment with 300 Ω load capability Seven master clock rates of 256 kHz to 4.096 MHz Pin-selectable 　-Law and A-Law companding (compliant with ITU G.711) CODEC A/D and D/A filtering compliant with ITU G.712 Industrial temperature range (–40°C to +85°C) Four packages: 24-pin PDIP, SOG, SSOP, and TSSOP Pb-Free / RoHS package options available APPLICATIONS • • • • • • • • • • • Digital Telephone Systems Central Office Equipment (Gateways, Switches, Routers) PBX Systems (Gateways, Switches) PABX/SOHO Systems Local Loop card SOHO Routers VoIP Terminals Enterprise Phones ISDN Terminals Analog line cards Digital Voice Recorders -2- Publication Release Date: September, 2005 Revision A12 W6811 3. BLOCK DIAGRAM Receive PCM Interface BCLKR FSR PCMR BCLKT FST PCMT Re Int PC cei erf M ve ace Transmit PCM Interface Tra Int ns PC erf mitM ace G.712 G.712 CODEC G.711 μ/A -Law PAO+ PAOPAI RO RO AO AI+ AI- μ/A-Law V REF 512 kHz 256 kHz MCLK 256 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz Pre -scaler Saler 8 kHz Voltage reference V AG Power Conditioning VDDA VDDD VSSA VSSD PUI -3- Publication Release Date: September, 2005 Revision A12 W6811 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION ................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM............................................................................................................................... 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION............................................................................................................ 9 7.1. Transmit Path............................................................................................................................. 9 7.2. Receive Path............................................................................................................................ 10 7.3. Power Management................................................................................................................. 11 7.3.1. Analog Supply ................................................................................................................ 11 7.3.2. Digital Supply ................................................................................................................. 11 7.3.3. Analog Ground Reference Bypass................................................................................. 11 7.3.4. Analog Ground Reference Voltage Output .................................................................... 11 7.4. PCM Interface .......................................................................................................................... 11 7.4.1. Long Frame Sync ........................................................................................................... 12 7.4.2. Short Frame Sync .......................................................................................................... 12 7.4.3. GCI Interface .................................................................................................................. 12 7.4.4. IDL Interface ................................................................................................................... 13 7.4.5. System Timing................................................................................................................ 13 8. TIMING DIAGRAMS.......................................................................................................................... 14 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 21 9.1. Absolute Maximum Ratings .................................................................................................... 21 9.2. Operating Conditions .............................................................................................................. 21 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22 10.1. General Parameters............................................................................................................... 22 10.2. Analog Signal Level and Gain Parameters............................................................................ 23 10.3. Analog Distortion and Noise Parameters............................................................................... 24 10.4. Analog Input and Output Amplifier Parameters ..................................................................... 25 10.5. Digital I/O ............................................................................................................................... 27 10.5.1. µ-Law Encode Decode Characteristics ........................................................................ 27 10.5.2. A-Law Encode Decode Characteristics........................................................................ 28 10.5.3. PCM Codes for Zero and Full Scale ............................................................................ 29 10.5.4. PCM Codes for 0dBm0 Output .................................................................................... 29 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 30 12. PACKAGE SPECIFICATION .......................................................................................................... 32 12.1. 24L TSSOP – 4.4X7.8mm ..................................................................................................... 32 12.2. 24L SOP – 300mil.................................................................................................................. 33 12.3. 24L SSOP – 209mil ............................................................................................................... 34 12.4. 24L PDIP – 300 mil ................................................................................................................ 35 13. ORDERING INFORMATION........................................................................................................... 36 14. VERSION HISTORY ....................................................................................................................... 37 -4- Publication Release Date: September, 2005 Revision A12 W6811 5. PIN CONFIGURATION VREF RO PAI PAO PAO+ VDDA NC VDDD FSR PCMI CMR BCLKR PUI 1 VREF 2 RO3 PAI 4 PAO 5 PAO+ 6 VDDA 7 NC 8 VDDD 9 FSR 10 PCMI 11 BCLKR 12 PUI 24 V AG AI+ 23 23 AI 22 AO 21 /A 20 μ V 19 SSA NC 18 18 17 V SSD FSX 16 16 PCMO 15 BCLKT 14 MCLK 13 VAG AI+ AIAO μ/A-Law VSSA NC VSSD FST PCMT BCLKT MCLK PDIP/SOP/SSOP/TSSOP -5- Publication Release Date: September, 2005 Revision A12 W6811 6. PIN DESCRIPTION Pin Name VREF Pin No. 1 VDD* A Functionality This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be decoupled to VSSA through a 0.1 μF ceramic decoupling capacitor. No external loads should be tied to this pin. Inverting output of the receive smoothing filter. This pin can typically drive a 2 kΩ load to 1.575 volt peak referenced to the analog ground level. This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage. Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt peak referenced to the VAG voltage level. Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 Volt peak referenced to the VAG voltage level. Analog power supply. This pin should be decoupled to VSSA with a 0.1μF ceramic capacitor. Not Connected Digital power supply. This pin should be decoupled to VSSD with a 0.1μF ceramic capacitor. For correct operation, VDDD value should always be lower than VDDA. 8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit and receive are synchronous operations. PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins. PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is selected when this pin is tied to VSSD. The IDL mode is selected when this pin is tied to VDDD. This pin can also be tied to the BCLKT when transmit and receive are synchronous operations. Power up input signal. When this pin is tied to VDDD, the part is powered up. When tied to VSSD, the part is powered down. System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have the MCLK signal synchronous and aligned to the FST signal. This is a requirement in the case of 256 and 512 kHz frequencies. PCM transmit bit clock input pin. PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins. 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. ROPAI PAOPAO+ VDDA NC VDDD 2 3 4 5 6 7 8 A A A A A D FSR 9 D PCMR BCLKR 10 11 D D PUI MCLK 12 13 D D BCLKT PCMT FST 14 15 16 D D D -6- Publication Release Date: September, 2005 Revision A12 W6811 Pin Name VSSD NC VSSA μ/A-Law This is the digital supply ground. This pin should be connected to 0V. Not Connected A This is the analog supply ground. This pin should be connected to 0V. D Compander mode select pin. μ-Law companding is selected when this pin is tied to VDDD. A-Law companding is selected when this pin is tied to VSSD. AO 21 A Analog output of the first gain stage in the transmit path. AI22 A Inverting input of the first gain stage in the transmit path. AI+ 23 A Non-inverting input of the first gain stage in the transmit path. VAG 24 A Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal processing. This pin should be decoupled to VSSA with a 0.01μF capacitor. This pin becomes high impedance when the chip is powered down. * These columns represent whether the pin Is driven by Analog (‘A’) or Digital (‘D’) power supply. Pin No. 17 18 19 20 VDD* D Functionality -7- Publication Release Date: September, 2005 Revision A12 W6811 7. FUNCTIONAL DESCRIPTION W6811 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC also includes a complete μLaw and A-Law compander. The μ-Law and A-Law companders are designed to comply with the specifications of the ITU-T G.711 recommendation. The block diagram in section 3 shows the main components of the W6811. The chip consists of a PCM interface, which can process long and short frame sync formats, as well as GCI and IDL formats. The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. The main CODEC block diagram is shown in section 3. VA VAG G +-+ PAO+ PAO PAI Receive Path 8 /Aμ/A Cont Control o D/A Converter w + Smooth Smoothing Filter F ng ilter 2 fC= 3400Hz Smooth SHz moothing Filter ng 1 RO - Transmit Path AO 8 μ - /Aμ/A Control Cont A/D Converter ++ AI+ AI - fC = 200Hz fC= 3400Hz = 3400 fC = 200 Figure 7.1 The W6811 Signal Path Hz Hz High Pass Ant-Aliasing Ant-Aliasi High Ant-Aliasi Ant-Aliasing Filt Filter Filter Pas i Filter ng 7.1. TRANSMIT PATH The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). The device has an input operational amplifier whose output is the input to the encoder section. If the input amplifier is not required for operation it can be powered down and bypassed. In that case a single ended input signal can be applied to the AO pin or the AI- pin. The AO pin becomes high input impedance when the input amplifier is powered down. The input amplifier can be powered down by connecting the AI+ pin to VDDA or VSSA. The AO pin is selected as an input when AI+ is tied to VDDA and the AI- pin is selected as an input when AI+ is tied to VSSA (see Table 7.1). -8- Publication Release Date: September, 2005 Revision A12 W6811 AI+ Input Amplifier Input VDDA Powered Down AO 1.2 to VDDA-1.2 Powered Up AI+, AIVSSA Powered Down AITable 7.1 Input Amplifier Modes of operation When the input amplifier is powered down, the input signal at AO or AI- needs to be referenced to the analog ground voltage VAG. The output of the input amplifier is fed through a 3.4 kHz switched capacitor low pass filter to prevent aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or A-Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression format can be selected according to Table 7.2. μ/A-Law Pin VSSA VDDA Format A-Law μ-Law Table 7.2. Pin-selectable Compression Format The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial transmission at the data rate supplied by the external bit clock BCLKT. 7.2. RECEIVE PATH The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO-. The RO- output can be externally connected to the PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external resistors (see section 11 for examples), various gain settings of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDDA. -9- Publication Release Date: September, 2005 Revision A12 W6811 7.3. POWER MANAGEMENT 7.3.1. Analog Supply The power supply for the analog part of the W6811 needs to be 5V +/- 10%. This supply voltage is connected to the VDDA pin. The VDDA pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. 7.3.2. Digital Supply The power supply for the digital part of the W6811 needs to be 3V +/- 10%. This supply voltage is connected to the VDDD pin. The VDDD pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. 7.3.3. Analog Ground Reference Bypass The system has an internal precision voltage reference which generates the 2.5V mid-supply analog ground voltage. This voltage needs to be decoupled to VSSA at the VREF pin through a 0.1 μF ceramic capacitor. 7.3.4. Analog Ground Reference Voltage Output The analog ground reference voltage is available for external reference at the VAG pin. This voltage needs to be decoupled to VSSA through a 0.01 μF ceramic capacitor. The analog ground reference voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing. 7.4. PCM INTERFACE The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of operation of the interface are shown in Table 7.3. BCLKR 64 kHz to 4.096 MHz VSSD VSSD VDDD VDDD Table 7.3 PCM Interface mode selections FSR 8 kHz VSSD VDDD VSSD VDDD Interface Mode Long or Short Frame Sync ISDN GCI with active channel B1 ISDN GCI with active channel B2 ISDN IDL with active channel B1 ISDN IDL with active channel B2 7.4.1. Long Frame Sync The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 64 kHz to 4.096 MHz clock and connecting the FSR or FST pin to the 8 kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal. It recognizes a Long Frame Sync when the FST pin is Publication Release Date: September, 2005 Revision A12 - 10 - W6811 held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 8 bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be HIGH impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section. 7.4.2. Short Frame Sync The W6811 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the bit-clock, the W6811 starts clocking out the data on the PCMT pin, which will also change from high to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway through the LSB. The Short Frame Sync operation of the W6811 is based on an 8-bit data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. More detailed timing information can be found in the interface timing section. 7.4.3. General Circuit Interface (GCI) The GCI interface mode is selected when the BCLKR pin is connected to VSSD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The GCI interface consists of 4 pins : FSC (FST), DCL (BCLKT), Dout (PCMT) & Din (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. Data transitions occur on the positive edges of the data clock DCL. The Frame Sync positive edge is aligned with the positive edge of the data clock DCLK. The data rate is running half the speed of the bit-clock. The channels B1 and B2 are transmitted consecutively. Therefore, channel B1 is transmitted on the first 16 clock cycles of DCL and B2 is transmitted on the second 16 clock cycles of DCL. For more timing information, see the timing section. - 11 - Publication Release Date: September, 2005 Revision A12 W6811 7.4.4. Interchip Digital Link (IDL) The IDL interface mode is selected when the BCLKR pin is connected to VDDD for two or more frame sync cycles. It can be used as a 2B+D timing interface in an ISDN application. The IDL interface consists of 4 pins : IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (PCMT) & IDL RX (PCMR). The FSR pin selects channel B1 or B2 for transmit and receive. The data for channel B1 is transmitted on the first positive edge of the IDL CLK after the IDL SYNC pulse. The IDL SYNC pulse is one IDL CLK cycle long. The data for channel B2 is transmitted on the eleventh positive edge of the IDL CLK after the IDL SYNC pulse. The data for channel B1 is received on the first negative edge of the IDL CLK after the IDL SYNC pulse. The data for channel B2 is received on the eleventh negative edge of the IDL CLK after the IDL SYNC pulse. The transmit signal pin IDL TX becomes high impedance when not used for data transmission and also in the time slot of the unused channels. For more timing information, see the timing section. 7.4.5. System Timing The system can work at 256 kHz, 512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz master clock rates. The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256 kHz and an 8 kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the division ratio accordingly. If the Frame Sync is LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W6811 will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the Frame Sync pulse needs to be present. It will take two Frame Sync cycles before the pin PCMT will become low impedance. - 12 - Publication Release Date: September, 2005 Revision A12 W6811 8. TIMING DIAGRAMS TFTRHM TFTRSM TMCKH TMCKL TRISE TFALL MCLK TMCK TFS TFSL TFTRH TFTRS TFTFH TBCKH TBCKL FST BCLKT 0 TFDTD 1 2 3 TBDTD 4 5 6 7 8 THID THID 0 TBCK 1 PCMT D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB TFS TFSL TFRRH TFRRS TFRFH FSR TBCKH TBCKL BCLKR 0 1 2 3 4 5 6 7 8 0 TBCK 1 PCMR D7 MSB TDRS D6 D5 TDRH D4 D3 D2 D1 D0 LSB Figure 8.1 Long Frame Sync PCM Timing - 13 - Publication Release Date: September, 2005 Revision A12 W6811 SYMBOL 1/TFS TFSL 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFDTD TBDTD THID TFRRH TFRRS TFRFH TDRS TDRH DESCRIPTION MIN TYP FST, FSR Frequency --8 FST / FSR Minimum LOW Width 1 TBCK BCLKT, BCLKR Frequency 64 --BCLKT, BCLKR HIGH Pulse Width 50 --BCLKT, BCLKR LOW Pulse Width 50 --BCLKT 0 Falling Edge to FST Rising 20 --Edge Hold Time FST Rising Edge to BCLKT 1 Falling 80 --edge Setup Time BCLKT 2 Falling Edge to FST Falling 50 --Edge Hold Time FST Rising Edge to Valid PCMT Delay ----Time BCLKT Rising Edge to Valid PCMT ----Delay Time Delay Time from the Later of FST 10 --Falling Edge, or BCLKT 8 Falling Edge to PCMT Output High Impedance BCLKR 0 Falling Edge to FSR Rising 20 --Edge Hold Time FSR Rising Edge to BCLKR 1 Falling 80 --edge Setup Time BCLKR 2 Falling Edge to FSR Falling 50 --Edge Hold Time Valid PCMR to BCLKR Falling Edge 0 --Setup Time PCMR Hold Time from BCLKR Falling 50 --Edge Table 8.1 Long Frame Sync PCM Timing Parameters MAX --4096 ----------60 60 60 UNIT kHz sec kHz ns ns ns ns ns ns ns ns ----------- ns ns ns ns ns 1 TFSL must be at least ≥ TBCK Publication Release Date: September, 2005 Revision A12 - 14 - W6811 TFTRHM TFTRSM TMCKH TMCKL TRISE TFALL MCLK TMCK TFTFH TFTFS TFS FST TFTRH TFTRS TBCKH TBCKL BCLKT -1 0 1 TBDTD 2 3 TBDTD 4 5 6 7 8 THID 0 TBCK 1 PCMT D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB TFS TFRFH TFRFS FSR TFRRH TFRRS TBCKH TBCKL BCLKR -1 0 1 2 3 4 5 6 7 8 0 TBCK 1 PCMR D7 MSB TDRS D6 D5 TDRH D4 D3 D2 D1 D0 LSB Figure 8.2 Short Frame Sync PCM Timing - 15 - Publication Release Date: September, 2005 Revision A12 W6811 SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFTFS TBDTD THID TFRRH TFRRS TFRFH TFRFS TDRS TDRH DESCRIPTION FST, FSR Frequency BCLKT, BCLKR Frequency BCLKT, BCLKR HIGH Pulse Width BCLKT, BCLKR LOW Pulse Width BCLKT –1 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 0 Falling edge Setup Time BCLKT 0 Falling Edge to FST Falling Edge Hold Time FST Falling Edge to BCLKT 1 Falling Edge Setup Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from BCLKT 8 Falling Edge to PCMT Output High Impedance BCLKR –1 Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR 0 Falling edge Setup Time BCLKR 0 Falling Edge to FSR Falling Edge Hold Time FSR Falling Edge to BCLKR 1 Falling Edge Setup Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge MIN --64 50 50 20 80 50 50 10 10 20 80 50 50 0 50 TYP 8 ------------------------------- MAX --4096 ------------60 60 ------------- UNIT kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Table 8.2 Short Frame Sync PCM Timing Parameters - 16 - Publication Release Date: September, 2005 Revision A12 W6811 TFS FST TFSRH TFSFH TFSRS 0 1 2 TBDTD 3 4 5 6 TBDTD 7 8 9 THID 10 11 12 13 14 TBCKH 15 16 TBCKL 17 18 THID D1 D0 LSB BCLKT -1 TBDTD TBDTD TBCK PCMT D7 D6 D5 D4 D3 D2 D1 D0 MSB TDRS TDRH LSB D7 D6 D5 D4 D3 D2 MSB TDRS TDRH PCMR D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB D7 D6 D5 D4 D3 D2 MSB D1 D0 LSB BCH = 0 B1 Channel BCH = 1 B2 Channel Figure 8.3 IDL PCM Timing SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFSRH TFSRS TFSFH TBDTD THID TDRS TDRH DESCRIPTION FST Frequency BCLKT Frequency BCLKT HIGH Pulse Width BCLKT LOW Pulse Width BCLKT –1 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 0 Falling edge Setup Time BCLKT 0 Falling Edge to FST Falling Edge Hold Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the BCLKT 8 Falling Edge (B1 channel) or BCLKT 18 Falling Edge (B2 Channel) to PCMT Output High Impedance Valid PCMR to BCLKT Falling Edge Setup Time PCMR Hold Time from BCLKT Falling Edge MIN --256 50 50 20 60 20 10 10 TYP 8 ----------------- MAX --4096 ----------60 50 UNIT kHz kHz ns ns ns ns ns ns ns 20 75 ----- ----- ns ns Table 8.3 IDL PCM Timing Parameters - 17 - Publication Release Date: September, 2005 Revision A12 W6811 TFS FST TFSRH TFSFH TFSRS TBCKH TBCKL BCLKT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 TFDTD TBDTD THID TBDTD TBDTD TBCK D1 D0 THID PCMT D7 D6 D5 D4 D3 D2 D1 D0 MSB TDRS TDRH D7 D6 D5 D4 D3 D2 LSB MSB TDRS TDRH LSB PCMR D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 MSB LSB MSB D1 D0 LSB BCH = 0 B1 Channel BCH = 1 B2 Channel Figure 8.4 GCI PCM Timing SYMBOL 1/TFST 1/TBCK TBCKH TBCKL TFSRH TFSRS TFSFH TFDTD TBDTD THID TDRS TDRH DESCRIPTION FST Frequency BCLKT Frequency BCLKT HIGH Pulse Width BCLKT LOW Pulse Width BCLKT 0 Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT 1 Falling edge Setup Time BCLKT 1 Falling Edge to FST Falling Edge Hold Time FST Rising Edge to Valid PCMT Delay Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the BCLKT 16 Falling Edge (B1 channel) or BCLKT 32 Falling Edge (B2 Channel) to PCMT Output High Impedance Valid PCMR to BCLKT Rising Edge Setup Time PCMR Hold Time from BCLKT Rising Edge Table 8.4 GCI PCM Timing Parameters MIN --512 50 50 20 60 20 ----10 TYP 8 ------------------- MAX --6176 ----------60 60 50 UNIT kHz kHz ns ns ns ns ns ns ns ns 20 --- ----- --60 ns ns - 18 - Publication Release Date: September, 2005 Revision A12 W6811 SYMBOL 1/TMCK DESCRIPTION Master Clock Frequency MIN --- TYP 256 512 1536 1544 2048 2560 4096 ------------- MAX --- UNIT kHz TMCKH / TMCK TMCKH TMCKL TFTRHM TFTRSM TRISE TFALL MCLK Duty Cycle for 256 kHz Operation Minimum Pulse Width HIGH for MCLK(512 kHz or Higher) Minimum Pulse Width LOW for MCLK (512 kHz or Higher) MCLK falling Edge to FST Rising Edge Hold Time FST Rising Edge to MCLK Falling edge Setup Time Rise Time for All Digital Signals Fall Time for All Digital Signals 45% 50 50 50 50 ----- 55% --------50 50 ns ns ns ns ns ns Table 8.5 General PCM Timing Parameters - 19 - Publication Release Date: September, 2005 Revision A12 W6811 9. ABSOLUTE MAXIMUM RATINGS 9.1. ABSOLUTE MAXIMUM RATINGS Condition Junction temperature Storage temperature range Voltage Applied to any pin Digital Voltage applied to any pin (Input current limited to +/-20 mA) VDDA - VSSA ; VDDD - VSSD VDDD – VDDA2 Analog Digital Analog 1500C -650C to +1500C (VSSA - 0.3V) to (VDDA + 0.3V) (VSSD - 0.3V) to (VDDD + 0.3V) (VSSA – 1.0V) to (VDDA + 1.0V) (VSSD – 1.0V) to (VDDD + 1.0V) -0.5V to +6V < 0.3V Value 1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. 2. At any time, the digital power supply should not be higher the 0.3V from the analog power supply. 9.2. OPERATING CONDITIONS Condition Industrial operating temperature Analog supply voltage (VDDA) Digital supply voltage (VDDD) Ground voltage (VSSA, VSSD) 0 0 Value -40 C to +85 C +4.5V to +5.5V +2.7V to +3.3V 0V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. - 20 - Publication Release Date: September, 2005 Revision A12 W6811 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS Symbo l VIL VIH VOL VOH IDDA IDDD ISBA ISBD IPDA IPDD IIL IOL CIN COUT Parameters Input LOW Voltage Input HIGH Voltage PCMT Output LOW Voltage PCMT Output HIGH Voltage VDDA Current (Operating) -ADC+DAC IOL = 1.6 mA IOL = -1.6 mA PUI = 1 FSX running MCLK running PUI = 1 FSX = 0 MCLK running PUI = 0 PUI = 0 VSSD