W681307

W681307 Product Datasheet USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM. -1- Publication Release Date: May, 2007 Revision 1.3 W681307 AMENDMENT HISTORY Ver Date 1.0 2006/11/22 1.1 2006/12/02 1.2 2006/12/28 1.3 2007/07/23 Filename W681307_Data Sheet_V1.0 W681307_Data Sheet_V1.1 W681307_Data Sheet_V1.2 W681307_Data Sheet_V1.3 Author MCSu MCSu MCSu Changes (•: modified, √: added, ×: removed) • Modify register 0x14C4. • Modify Figure 14-2. • Modify register 0x14E5. Reference W681307_Data Sheet_V1.0 W681307_Data Sheet_V1.1 W681307_Data Sheet_V1.2 TYChiu • Modify endpoint table 18.2.1. -2- Publication Release Date: May, 2007 Revision 1.3 W681307 CONTENTS 1. GENERAL DESCRIPTION ..................................................................................................... - 9 2. FEATURES ........................................................................................................................... - 10 3. PIN CONFIGURATION ....................................................................................................... - 11 4. PINS DESCRIPTION ............................................................................................................ - 12 5. SYSTEM DIAGRAM ............................................................................................................. - 17 5.1 Function Block Diagram ................................................................................................... - 17 5.2 I/O Cells in Winbond MCU Chip .................................................................................... - 18 6. ELECTRICAL CHARACTERISTICS ..................................................................................... - 20 6.1 Absolute Maximum Ratings ............................................................................................. - 20 6.2 DC Characteristics............................................................................................................ - 20 6.3 Analog Transmission Characteristics ............................................................................... - 21 6.3.1 Amplitude Response for Analog Transmission Performance ....................................... - 21 6.3.2 Distortion Characteristics for Analog Transmission Performance ................................ - 21 6.4 Analog Electrical Characteristics ...................................................................................... - 22 6.5 Power Drivers – PO1, 2 .................................................................................................... - 22 6.6 Programmable Output Linear Regulator .......................................................................... - 23 6.7 USB PHY Electronic Characteristics ( 25°C, VDD_USB = 3.3V, DVDD1, 3 =1.9V) ............. - 23 6.8 USB PLL Electronic Characteristics ( 25°C, AVDD = 3.3V, DVDD1, 3 =1.9V) .................... - 24 6.9 The Crystal Specification Requirement ............................................................................. - 24 6.10 Recommended Crystal Specification ................................................................................ - 25 7. MEMORY AND REGISTER MAP ......................................................................................... - 26 7.1 Program Memory Map..................................................................................................... - 26 7.2 Data Memory Map ........................................................................................................... - 26 7.3 Register Map .................................................................................................................... - 27 7.3.1 Mixer and Speech Logic Registers Overview ............................................................... - 27 7.3.2 Support Logic Registers Overview............................................................................... - 27 7.3.3 Interface Logic Registers Overview.............................................................................. - 28 7.3.4 Speech Interface Registers Overview ........................................................................... - 28 7.3.5 Processor Interface Registers Overview ....................................................................... - 29 7.3.6 Transcoder DSP Registers Overview............................................................................ - 29 7.3.7 Echo Canceller Registers Overview ............................................................................. - 30 7.3.8 Soft Clip Registers Overview ....................................................................................... - 31 7.3.9 CODEC Digital Part ..................................................................................................... - 31 7.3.10 Sounder Path Select ..................................................................................................... - 31 7.3.11 Frequency Adjustment of Crystal Oscillator ................................................................ - 31 7.3.12 Specific Register........................................................................................................... - 31 7.3.13 VAG Selection ............................................................................................................. - 32 7.3.14 CODEC Control Register Overview ............................................................................. - 32 7.3.15 Specific Registers ......................................................................................................... - 32 7.3.16 Test Cases and Debugging Registers Overview ........................................................... - 32 7.3.17 Charge Park Detection ................................................................................................. - 32 7.3.18 DA High Pass Filter Selection ...................................................................................... - 33 7.3.19 TI PATH Selection ....................................................................................................... - 34 7.3.20 Network side / Acoustic side Power Measurement ..................................................... - 34 7.3.21 PCM Highway Channel Registers Overview ............................................................... - 35 7.3.22 SPI Interface Registers Overview ................................................................................. - 35 7.3.23 Data Flash SPI Interface Registers Overview................................................................ - 36 -3Publication Release Date: May, 2007 Revision 1.3 W681307 7.3.24 W2S Interface Registers Overview ............................................................................... - 36 7.3.25 USB Control Registers Overview ................................................................................. - 37 7.3.26 ISP Mode ..................................................................................................................... - 38 8. SUPPORT LOGIC ................................................................................................................. - 39 8.1 Clock Control & Reset 32K ............................................................................................... - 40 8.1.1 Overview ..................................................................................................................... - 40 8.1.2 Functionality ............................................................................................................... - 40 8.1.3 Clock Enable Register .................................................................................................. - 40 8.2 Interrupt Control.............................................................................................................. - 41 8.2.1 Overview ..................................................................................................................... - 41 8.2.2 Functionality ............................................................................................................... - 41 8.2.3 Interrupt Registers ....................................................................................................... - 43 8.2.4 Extends of interrupt ..................................................................................................... - 44 8.3 Ringer Tone Generator ..................................................................................................... - 45 8.3.1 Overview ..................................................................................................................... - 45 8.3.2 Functionality ............................................................................................................... - 45 8.3.3 Sounder Tone Register Definition ................................................................................ - 46 8.3.4 Sounder Volume Register Definition ........................................................................... - 46 8.3.5 Example of use ............................................................................................................ - 46 8.3.6 Sounder Registers ........................................................................................................ - 47 8.4 PIEZO Tone Generator ..................................................................................................... - 48 8.4.1 Overview ..................................................................................................................... - 48 8.4.2 Functionality ............................................................................................................... - 48 9. INTERFACE LOGIC ............................................................................................................. - 49 9.1 Keypad Scanner ............................................................................................................... - 49 9.1.1 Overview ..................................................................................................................... - 49 9.1.2 Use of the Keypad Scanner .......................................................................................... - 50 9.1.3 Use of a Software Keypad Scanner............................................................................... - 50 9.2 I/O Ports.......................................................................................................................... - 50 9.3 Keypad Control Registers ................................................................................................ - 51 9.3.1 Key Location and Size Programming ........................................................................... - 53 9.4 Timers .............................................................................................................................. - 53 9.4.1 Watch Dog Control ...................................................................................................... - 54 9.4.2 Timer 1ms Control1 ..................................................................................................... - 54 9.4.3 Timer Control .............................................................................................................. - 54 9.4.4 1S Counter ................................................................................................................... - 55 9.4.5 Watch Dog Kick ........................................................................................................... - 55 9.4.6 1ms Counter ................................................................................................................ - 55 10. SPEECH INTERFACE........................................................................................................... - 56 10.1 Overview ......................................................................................................................... - 56 10.2 Functionality .................................................................................................................... - 56 10.3 PCM Serial Interface......................................................................................................... - 57 10.3.1 Use with Additional External Lines ............................................................................. - 57 10.3.2 I/O Ports ..................................................................................................................... - 57 10.3.3 Status of Speech Interface When Reset ......................................................................... - 58 10.4 Internal CODEC Control .................................................................................................. - 58 10.5 PCM Interface Registers ................................................................................................... - 58 10.5.1 Speech Control 0 .......................................................................................................... - 58 -4Publication Release Date: May, 2007 Revision 1.3 W681307 10.5.2 Specific Register........................................................................................................... - 58 10.5.3 Speech IO Direction ..................................................................................................... - 59 10.5.4 Speech IO Input Data................................................................................................... - 59 10.5.5 Speech IO Output Data ................................................................................................ - 59 10.5.6 Speech IO Mask ........................................................................................................... - 60 10.5.7 Fsync Counter ............................................................................................................. - 60 10.6 The multiplexer to connect 5 PCM channels to 4 processor channels ................................ - 60 10.6.1 Multiplexer control register ......................................................................................... - 60 10.7 PCM Highway Interface ................................................................................................... - 61 10.7.1 The Introduction of PCM Modes ................................................................................. - 61 10.7.2 The Description of PCM Highway Interface Registers ................................................. - 63 10.8 Digital Gain Multiplexer .................................................................................................. - 66 10.8.1 Fine-Tuning Gain Stage Registers ................................................................................ - 66 11. PROCESSOR INTERFACE.................................................................................................... - 70 11.1 Overview ......................................................................................................................... - 70 11.2 Functionality .................................................................................................................... - 70 11.3 Processor Access Sequencer ............................................................................................. - 70 11.4 Read Multiplexer ............................................................................................................. - 73 11.5 Processor Interface Control Registers ............................................................................... - 73 11.5.1 AuxOpPort .................................................................................................................. - 73 11.5.2 DiagSel ........................................................................................................................ - 74 11.5.3 Diag_CS....................................................................................................................... - 75 11.5.4 Diag_CS3 ..................................................................................................................... - 76 11.5.5 Multiplier_Enable ........................................................................................................ - 77 11.6 In System Programming Mode ......................................................................................... - 77 11.6.1 Hardware Setting Usage .............................................................................................. - 77 11.6.2 Software Command Usage .......................................................................................... - 77 11.6.3 ISP_CTRL (Hardware & Watchdog Reset Control Register)......................................... - 78 11.6.4 Specific Register........................................................................................................... - 78 11.7 MASK ROM Mode ........................................................................................................... - 79 11.7.1 Usage........................................................................................................................... - 79 12. SPEECH PROCESSOR .......................................................................................................... - 80 12.1 Transcoder DSP................................................................................................................ - 80 12.2 The Description of the Activation Registers...................................................................... - 81 12.2.1 MIXER_EN .................................................................................................................. - 81 12.2.2 SPEECH LOGIC_EN ................................................................................................... - 81 12.3 The Description of Transcoder DSP Registers................................................................... - 81 12.3.1 Connect0...................................................................................................................... - 82 12.3.2 Specified Register ........................................................................................................ - 82 12.3.3 Specified Register ........................................................................................................ - 82 12.3.4 Specified Register ........................................................................................................ - 82 12.3.5 PCMmode0.................................................................................................................. - 83 12.3.6 InputGain0 .................................................................................................................. - 83 12.3.7 OutputGain0 ............................................................................................................... - 83 12.3.8 ToneFreqA0 ................................................................................................................. - 83 12.3.9 ToneFreqB0 ................................................................................................................. - 84 12.3.10 ToneVolA0 .................................................................................................................. - 84 12.3.11 ToneVolB0 ................................................................................................................... - 84 -5Publication Release Date: May, 2007 Revision 1.3 W681307 12.3.12 ToneEna0..................................................................................................................... - 84 12.3.13 SideTone ...................................................................................................................... - 85 12.3.14 Loopback_EN .............................................................................................................. - 85 12.3.15 Specified Register ........................................................................................................ - 85 12.3.16 Connect1 ~ ToneEna1 .................................................................................................. - 85 12.3.17 Connect2 ~ ToneEna2 .................................................................................................. - 85 12.3.18 SideToneChannel_Ena ................................................................................................. - 86 12.3.19 Connect3 ~ ToneEna3 .................................................................................................. - 86 12.4 PCM Mixer Matrix ........................................................................................................... - 86 12.5 Gain Tables ...................................................................................................................... - 86 13. ECHO CANCELLER ............................................................................................................ - 89 13.1 Half AEC Block Diagram ................................................................................................. - 89 13.1.1 Acoustics Suppression ................................................................................................. - 89 13.1.2 Network Power Estimation.......................................................................................... - 90 13.1.3 Acoustic Power Estimation .......................................................................................... - 90 13.1.4 Auto Gain Control ....................................................................................................... - 91 13.2 The Software Interface of Speech Processor ...................................................................... - 91 13.3 Activation Registers ......................................................................................................... - 91 13.3.1 UP_CONFIG................................................................................................................ - 91 13.3.2 UP_RESET ................................................................................................................... - 92 13.3.3 EC_BELTA .................................................................................................................. - 92 13.3.4 Specific Register........................................................................................................... - 92 13.4 Performance Adjustment Registers .................................................................................. - 92 13.4.1 Acoustic Suppressor Register ...................................................................................... - 92 13.4.2 Acoustic Side Control Registers ................................................................................... - 93 13.4.3 Network Side Control Registers................................................................................... - 95 13.4.4 ACOUSTIC / NETWORK Active Status ...................................................................... - 98 13.4.5 AGC Control Registers ................................................................................................ - 98 13.4.6 Noise Suppressor Registers........................................................................................ - 100 13.4.7 AEC Soft Clip ............................................................................................................ - 101 13.5 Acoustic Side / Network Side Power Measurement ....................................................... - 106 13.5.1 ACOUSTIC_SHORT_TERM_POWER ....................................................................... - 106 13.5.2 ACOUSTIC_LONG_TERM_POWER ......................................................................... - 106 13.5.3 ACOUSTIC_POWER_DEVIATION ........................................................................... - 107 13.5.4 ACOUSTIC / NETWORK Active Status .................................................................... - 107 13.5.5 NETWORK_SHORT_TERM_POWER ....................................................................... - 107 13.5.6 NETWORK_LONG_TERM_POWER ......................................................................... - 108 13.5.7 NETWORK_POWER_DEVIATION ........................................................................... - 108 13.5.8 ACOUSTIC / NETWORK Active Status .................................................................... - 108 14. SYSTEM FUNCTION.......................................................................................................... - 109 14.1 Power On Reset .............................................................................................................. - 109 14.1.1 CODEC On/Off Scheme ............................................................................................ - 109 14.1.2 CODEC Digital Part ................................................................................................... - 110 - -6- Publication Release Date: May, 2007 Revision 1.3 W681307 14.2 ADC Adaptive Bit Flip Probability ................................................................................. - 110 14.3 Sounder Signal Selection ................................................................................................ - 111 14.4 Frequency Adjustment of Crystal Oscillator ................................................................... - 112 14.5 Specific Register ............................................................................................................. - 113 14.6 VAG Selection ................................................................................................................ - 113 14.7 TG Gain Register ............................................................................................................ - 114 14.8 PO Gain Register ............................................................................................................ - 115 14.9 The PCM CODEC .......................................................................................................... - 117 14.9.1 Block Diagram ........................................................................................................... - 117 14.9.2 Analog Interface and Signal Path ............................................................................... - 117 14.9.3 Control Register: CODEC_CTRL ............................................................................... - 118 14.9.4 Specific Register......................................................................................................... - 119 14.9.5 Specific Register......................................................................................................... - 119 14.10 RECEIVE_DIAG............................................................................................................. - 119 14.11 Specific Register ............................................................................................................. - 121 14.12 EnAllClock ..................................................................................................................... - 121 14.13 CODEC_Test_Sel ........................................................................................................... - 121 14.14 Test_SYSCLKOUT.......................................................................................................... - 122 14.15 BGP_LPF_EN ................................................................................................................. - 122 14.16 CODEC Status Indicator................................................................................................. - 122 14.17 BandGap Voltage Adjustment ........................................................................................ - 123 14.18 Specific Register ............................................................................................................. - 123 14.19 Linear Regulator Voltage Controller Register ................................................................. - 123 14.20 Core PWR_Det ............................................................................................................... - 124 14.21 DA High Pass Filter Selection......................................................................................... - 124 14.22 TI Path Selection............................................................................................................. - 125 15. SERIAL PERIPHERAL INTERFACE ................................................................................... - 127 15.1 Serial Peripheral Interface – SPI signals .......................................................................... - 127 15.1.1 SPI_Control 0 ............................................................................................................. - 128 15.1.2 SPI_Control 1 ............................................................................................................. - 128 15.1.3 SPI Status................................................................................................................... - 129 15.1.4 SPI Interrupt Enable .................................................................................................. - 129 15.1.5 DumpByte ................................................................................................................. - 129 15.1.6 Write TX FIFO ........................................................................................................... - 129 15.1.7 Read RX FIFO ............................................................................................................ - 130 15.1.8 SPI_Transfer_Size ...................................................................................................... - 130 15.1.9 SPI_Start_rtx .............................................................................................................. - 130 16. SPI FOR SERIAL DATA FLASH ......................................................................................... - 131 16.1 Introduction to SPI of Serial Data Flash .......................................................................... - 131 16.2 Block Diagram ............................................................................................................... - 131 16.3 Data Format ................................................................................................................... - 132 16.4 FSM................................................................................................................................ - 134 16.5 FIFO/RAM .................................................................................................................... - 134 16.6 Interrupt ........................................................................................................................ - 134 16.7 DF_SPI Register Group .................................................................................................. - 134 16.7.1 DF_CLK..................................................................................................................... - 134 16.7.2 DF_CMD_LEN .......................................................................................................... - 135 16.7.3 DF_DATA_LEN ........................................................................................................ - 135 -7Publication Release Date: May, 2007 Revision 1.3 W681307 16.7.4 DF_INTR_REG .......................................................................................................... - 135 16.7.5 DF_CMD_B1 ~ DF_CMD B5 ...................................................................................... - 136 16.7.6 DF_CLK_FORMAT ................................................................................................... - 137 16.7.7 DF_FIFO_DATA ........................................................................................................ - 138 16.7.8 DF_CNT .................................................................................................................... - 138 16.7.9 DF_WR_CNT............................................................................................................. - 139 16.7.10 DF_RD_CNT ............................................................................................................. - 139 16.8 Example of W25X20/40/80 Serial Flash ......................................................................... - 139 17. WINBOND 2-WIRE SERIAL BUS ....................................................................................... - 141 17.1 Introduction to Winbond 2-Wire Serial bus .................................................................... - 141 17.2 The Description of W2S Register .................................................................................... - 141 17.2.1 W2S_Enable ............................................................................................................... - 141 17.2.2 EEPROM_Config ....................................................................................................... - 142 17.2.3 Prescale_Lo................................................................................................................ - 142 17.2.4 Prescale_Hi ................................................................................................................ - 142 17.2.5 RdWrFIFO ................................................................................................................. - 143 17.2.6 Force_Activity ........................................................................................................... - 143 17.2.7 W2S_Status ................................................................................................................ - 143 17.2.8 FIFORdPtr ................................................................................................................. - 144 17.2.9 FIFOWrPtr ................................................................................................................. - 144 17.2.10 ForceAckFail.............................................................................................................. - 144 17.2.11 W2S_Misc .................................................................................................................. - 144 18. USB DEVICE CONTROLLER AND TRANSCEIVER .......................................................... - 145 18.1 Overview ....................................................................................................................... - 145 18.2 Functionality .................................................................................................................. - 145 18.2.1 Endpoints .................................................................................................................. - 146 18.2.2 Descriptor Rom ......................................................................................................... - 146 18.2.3 Configurations and Interfaces .................................................................................... - 147 18.2.4 Audio Class ............................................................................................................... - 148 18.2.5 HID Class .................................................................................................................. - 149 18.2.6 USB ISP mode............................................................................................................ - 150 18.2.7 Vendor Command ..................................................................................................... - 150 18.3 USB Registers ................................................................................................................. - 150 18.3.1 USB Enable Register .................................................................................................. - 150 18.3.2 USB Interrupt Register A ........................................................................................... - 150 18.3.3 USB Interrupt Register B ............................................................................................ - 151 18.3.4 EndPoint 0 – Control In/Out Registers ...................................................................... - 152 18.3.5 EndPoint 1 and 2 – ISO In/Out Registers................................................................... - 153 18.3.6 EndPoint 3 – Bulk In Registers ................................................................................... - 155 18.3.7 EndPoint 4 – Bulk Out Registers ................................................................................ - 156 18.3.8 EndPoint 5 – Interrupt In Registers ............................................................................ - 157 18.3.9 Specific Register......................................................................................................... - 158 18.3.10 Specific Register......................................................................................................... - 158 18.3.11 Specific Register......................................................................................................... - 158 19. PACKAGE DIMENSIONS .................................................................................................. - 159 - -8- Publication Release Date: May, 2007 Revision 1.3 W681307 1. GENERAL DESCRIPTION The main product targets for the USB CODEC MCU chip are • • • • • • 27.648MHz four cycle 8032 MCU Support external Flash and easy transfer to low cost Mask ROM production Universal Serial Bus (USB) v1.1 compliant device controller and PHY, capable of full speed communication (12MHz) with up to 5 configuration end –points 8KHz voice sampling rate and 16bits of ADC/DAC Support AEC/AGC for on-chip speaker phone support Support Keypad function Winbond MCU chip will be available in the following package Device W681307D xxxx Package 100 pin LQFP Description Normal mode, Mask ROM 32K, x2 CLK ： -9- Publication Release Date: May, 2007 Revision 1.3 W681307 2. FEATURES Micro controller • Embedded 27.648MHz WINBOND® Turbo 8032 Micro-Controller with 4 Clocks per Machine Cycle • 4K system RAM, 32K MASK ROM • Core 1.9V, I/O 3.3V • Power on Reset circuit • Software Power Down mode • In system Programming (ISP) for 29/39/49 series flash ROM • Built-in Keypad Scan, Watchdog, Wait State Speech Processor/Interface • 4 Processor Channels • Programmable input/output gain stage • Programmable Auto Gain Control (AGC) stage • Programmable Soft Clip gain stage • Acoustic Echo Cancellation (AEC) with half duplex, absolute/relative mode • PCM interface for External CODEC or PCM interface • SNDR output • Built in DTMF tone generator PCM CODEC • One Built-in PCM CODEC • Analogue input amplifier with Internal programmable gain stage • Analog output amplifier: Push pull drive, Internal programmable gain stage USB 1.1 • Universal Serial Bus USB v1.1 compliant device controller and PHY, capable of full speed communication (12MHz) with up to 5 configuration end –points. UART • T8032 UART for data transmit application. PCM Highway • The 1st PCM Highway has four channels.. • All channels support 8/16 bits pcm format, and IOM2 mode. • Works in master or slave modes with external CODEC. W2S • Support three EEPROM format page modes. • Support six kinds of W2S bus clocks. SPI interface • Works in master or slave modes. SPI Flash interface • Works in master with the Winbond SPI interface of series flash. ISP • In-system-Programming capability with software command via UART or USB interface. Package • 100 pin LQFP package - 10 - Publication Release Date: May, 2007 Revision 1.3 W681307 3. PIN CONFIGURATION SNDR_REF_CLK VDD_REG REG_CTRL VDD_USB VSS_REG VSS_USB USB_DN USB_DP PLL_LPF RESETC DGND1 DVDD1 AGND1 AVDD1 AVDD2 VGAP PO2N PO2 P 77 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 VAG 82 81 80 79 78 76 75 74 73 72 71 70 69 68 67 KR0 KR1 KR2 KR3 KR4 KC0 KC1 KC2 KC3 PCM_IN PCM_ OUT PCM_ CLK PCM_FSC ISP_WR PSEN ALE DVDD4 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PO1N TI2 T I2 T I1 TI 1 NC PO1P AGND 2 NC NC NC NC NC NC NC NC NC NC NC SYSCLKOUT NC DGND5 DVDD5 RESET OUT _ GND OSC _ XTAL2 XTAL1 VDD_ OSC DVDD3 DGND3 EXT_ROM W681307 D 100 PIN LQFP MASK ROM 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A8 A9 A10 A11 A12 A13 A14 DVDD2 DGND2 P3.4 /A0 P1.1 P1.2/SDA P3.5 /A1 P1.4/SCK P1.0 P1.3/SCL NC - 11 - P3.1(TXD0) CS2 / SPI_CS (ISP_EN) P1.6/MISO/SDO P1.5/MOSI/SD I / CS3 WR P3.0(RXD0) RD CS1/ DF_CS Publication Release Date: May, 2007 Revision 1.3 W681307 4. Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PINS DESCRIPTION State during Reset Input H Input H Input H Input H Input H Input L Input L Input L Input L Input H Input H Input L Input L Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H State after Reset Input H Input H Input H Input H Input H Input L Input L Input L Input L Input H Input H Input L Input L Input H Output H Output H Input H Input H Input H Input H Input H Input H Input H Input H Pin type section PC3B01U PC3B01U PC3B01U PC3B01U PC3B01U PC3B01D PC3B01D PC3B01D PC3B01D Pin name KR0 KR1 KR2 KR3 KR4 KC0 KC1 KC2 KC3 PCM_IN PCM_OUT PCM_CLK PCM_FSC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O PWR I/O I/O I/O I/O I/O I/O I/O I/O PWR PWR Function Description Keypad Scan row output Keypad Scan row output Keypad Scan row output Keypad Scan row output Keypad Scan row output Keypad Scan column input Keypad Scan column input Keypad Scan column input Keypad Scan column input Alternative Function GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO PC3B02U PCM high way, Data input PC3B02U PCM high way, Data output PC3B02D ISP_ WR PCM high way, Clock GPIO In/Output PCM high way, Frame pluse GPIO PC3B02D In/Output In the normal mode operation, this pin is high. In the inPC3B02U system-programming (PROG) state, this pin is used for WR function for writing flash memory program. PC3B02U PC3B02U PVDDC PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PVDDR PVSSR 8032T for Program Memory Strobe Enable Output address latch enable (ALE) function Digital supply voltage 4 (for digital I/O pads power) 8032T Multiplexed Address/Data pin 7 8032T Multiplexed Address/Data pin 6 8032T Multiplexed Address/Data pin 5 8032T Multiplexed Address/Data pin 4 8032T Multiplexed Address/Data pin 3 8032T Multiplexed Address/Data pin 2 8032T Multiplexed Address/Data pin 1 8032T Multiplexed Address/Data pin 0 Digital supply voltage 2 (for digital I/O pads power) Digital ground 2 (I/O ground) PSEN ALE DVDD4 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 DVDD2 DGND2 - 12 - Publication Release Date: May, 2007 Revision 1.3 W681307 29 30 31 32 33 34 35 36 37 38 39 40 A9 A10 A11 A12 A13 A14 NC P3.5 /A1 P3.4 /A0 P3.1 /TXD0 P3.0 /RXD0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input H Active Active - Output H Output H Output H Output H Output H Output H Output H Input H Input H Input H Input H Output H Output H Input H Input H Input H Input H Input H Input H Input H Input H Input H Input Active Active - PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3T02 8032T Address Line 9 8032T Address Line 10 8032T Address Line 11 8032T Address Line 12 8032T Address Line 13 8032T Address Line 14 No connection Port3 Bit 5 of 8032T Port3 Bit 4 of 8032T Port 3 Bit 1 or TXD serial transmit data port of internal 8032 Turbo Port 3 Bit 0 or RXD serial receive data port of internal 8032 Turbo External Chip Select General Purpose Output CS2 / SPI _ CS 41 42 43 44 CS1 / DF _ CS RD /P3.7 I/O I/O I/O I/O PC3T02 PC3B02U PC3B02U PC3B02U External Chip Select 8032T Read Strobe 8032T Write Strobe Port 1 Bit 6 General Purpose Output P3.7 is 8032 I/O P3.6 is 8032 I/O SPI function SPI function or External Chip Select WR / P3.6 P1.6 /MISO/SDI P1.5 /MOSI/SDO / 45 I/O PC3B02U Port 1 Bit 5 CS3 P1.4 /SCK P1.3 /SCL P1.2 /SDA P1.1 P1.0 I/O I/O I/O I/O I/O I PWR PWR PWR I O PWR 46 47 48 49 50 51 52 53 54 55 56 57 PC3B02U PC3B02U PC3B02U PC3B02U PC3B02U PC3D01U PVSSC PVDDC PVDDC PAnalog PAnalog PVSSC Port 1 Bit 4 or SPI interface This pin also supports wait clock output state function. Port 1 Bit 3 or W2S interface clock output of programming EEPROM. Port 1 Bit 2 or W2S interface serial data of programming EEPROM. Port 1 Bit 1 Port 1 Bit 0 When set this pin to high then the chip goes into external ROM mode. Digital ground 3 (core power ground) Digital supply voltage 3 for core power, which should connect to DVDD1. Oscillation circuits supply voltage. 13.824Mhz Crystal oscillator output 13.824Mhz Crystal oscillator input Oscillation circuits ground EXT_ROM DGND3 DVDD3 VDD_OSC XTAL1 XTAL2 GND_OSC - 13 - Publication Release Date: May, 2007 Revision 1.3 W681307 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 RESETOUT DVDD5 DGND5 NC SYSCLKOUT NC NC NC NC NC NC NC NC NC NC NC AGND2 O PWR PWR O O O O O O O O O O O O I PWR L Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Hi-Z - H Tristate L Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Tristate Hi-Z - PC3o01 PVDDC PVSSC PC3T02 PC3T02 PC3T02 PC3T01 PC3B01 PC3T01 PC3T01 PC3T02 PC3T02 PC3T02 PC3T01 Analog Analog PVSSC 75 PO1P O Tristate Tristate PAnalog 76 PO1N O Tristate Tristate PAnalog 77 PO2P O Tristate Tristate PAnalog 78 PO2N O Tristate Tristate PAnalog 79 80 81 82 83 84 85 86 87 88 89 AVDD2 AVDD1 RESETC REG_CTRL VAG VBGP AGND1 TI1+ TI1TI2+ TI2- PWR PWR O O O O PWR I I I I Tristate Active Tristate 1. 0V Hi-Z Hi-Z Hi-Z Hi-Z Tristate Active 1.5V 1.0V Hi-Z Hi-Z Hi-Z Hi-Z PVDDC PVDDC PAnalog PAnalog PAnalog Panalog PVSSC PAnalog PAnalog PAnalog PAnalog Chip reset indication output. Active high after the reset state. Digital supply voltage 5 (for digital I/O pads power) Digital ground 5 (I/O ground) No connection 13.824 MHz system clock output No connection No connection No connection No connection No connection No connection No connection No connection No connection No connection No connection Analog ground for OP2 output amplifier Power amplifier output (non-inverting) - This pin is the noninverting power amplifier output, which is an inverted version of the signal at PO1N. This pin is capable of driving a 120 Ω load to PO1N at 3V supply power. This pin is D.C. referred to the VAG pin. This pin is tri-state when the chip is in analog CODEC power down mode. Power amplifier output (inverting) - This pin is the inverting power amplifier output. This pin is capable of driving a 120 Ω load to PO1P at 3V supply voltage. This pin is D.C. referenced to the VAG pin. The PO1P and PO1N outputs are differential. This pin is tri-state when the chip is in analog CODEC power down mode. Power amplifier output (non-inverting) - This pin is the noninverting power amplifier output, which is an inverted version of the signal at PO2N. This pin is capable of driving a 16 Ω load to PO2N at 3V supply power. This pin is D.C. referred to the VAG pin. This pin is tri-state when the chip is in analog CODEC power down mode. Power amplifier output (inverting) - This pin is the inverting power amplifier output. This pin is capable of driving a 16 Ω load to PO2P at 3V supply voltage. This pin is D.C. referenced to the VAG pin. The PO2P and PO2N outputs are differential. This pin is tri-state when the chip is in analog CODEC power down mode. Analog supply voltage for OP2 amplifier Analog supply voltage It should connect a capacitor for internal power on reset circuit. Output signal of 3V linear regulator to drive the PNP transistor. Analog reference voltage. This pin possesses the analog virtual ground of internal CODEC circuits. The Band gap output voltage. It is 1.0V volt typically. Analog ground This is the non-inverting input of the transmission operational amplifier TG1. This is the inverting input of the transmission operational amplifier TG1. This is the non-inverting input of the transmission operational amplifier TG2. This is the non-inverting input of the transmission operational amplifier TG2. Publication Release Date: May, 2007 Revision 1.3 - 14 - W681307 90 91 92 93 94 95 VSS_REG VDD_REG DVDD1 DGND1 PLL_LPF VSS_USB PWR PWR PWR PWR O PWR Analog I/O Tristate - Tristate - PVSSC PVDDC PVDDC PVSSC Panalog PVSSC Ground of 3.0V linear regulator. 3.3V input of 3.0V linear regulator. 1.9V linear regulator output for internal digital core power supply. Connect a large capacitor (>10uF) for output regulation. Digital ground 1 (core power ground) Internal 48MHz PLL charge pump output. Put a passive LPF filter in the pin to ground. USB analog front end ground. USB D+ connection. Series termination resistors (22 ±1%) are required for impedance of USB bus. The USB Spec1.1 states that the impedance of each driver is required to be between 28 and 44 . This chip drive output resistance is 8 to 10 . Therefore, the 22 ±1% series resistors are used. USB D- connection. Series termination resistors (22 ±1%) are required for impedance of USB bus. The USB Spec1.1 states that the impedance of each driver is required to be between 28 and 44 . This chip drive output resistance is 8 to 10 . Therefore, the 22 ±1% series resistors are used. USB analog front end supply power. Full speed devices are identified by pulling D+ to 3.3V±0.3 Volts via a 1.5k ±5 % resistor. The baseband chip inside has been built in the 1.5k ±20% resistor and the default is disconnected to VDD_USB. The No connection Sounder output - This is a control pin to turn on/off the external transistor, which is used to supply the high peak currents that magnetic sounders typically require. 96 USB_DP Hi-Z Hi-Z PAnalog 97 USB_DN Analog I/O Hi-Z Hi-Z PAnalog 98 VDD_USB PWR - - PVDDC 99 100 NC SNDR I O Input Output L Input Output L PC3D21 PC3B02U * When /CS2 is pull low in the initial power on state. Then the chip will enter into the hardware ISP mode to download the system program code via UART or USB ports. * P1.2; P1.3 and P1.4 multiple functions W2 S_ENA 0x1740[7] & ~(W2S_Prot_Sel 0x1740 [6]) P1. 2 0 P1.2 SDA 1 SCL Piezo_ENB 0x144 B[ 0] P1. 4 1 SDA Piezo_CLK ： W2S_ENA 0x1740[7 ]& (W2 S_ Prot_Sel 0x1740[6 ]) W2S_ENA 0x1740[7 ]& ~(W2S_Prot_Sel 0x1740 [6]) P1.3 0 0 P1.3 1 SPI_ENB 0x1720 [7] 0 0 1 SPI_SCK 1 DF_SCK 1 SCL 1 0 0 P1.4 DF _ENB 0x1730[7] W2 S_ENA 0x1740[7] & (W2S_ Prot_Sel 0x1740[6 ]) 、 - 15 - Publication Release Date: May, 2007 Revision 1.3 W681307 * P1.5 and P1.6 multiple functions CS3_Enable [B4] ( 0x150C [B4] ) /CS3 1 P1.5 P1.6_ Sel [1:0] ( 0x150C [1:0] ) P1.6 X X P1.6 * P3.4 and P3.5 multiple functions P3.4 A0 P3.5 A1 ： P1.5_ Sel [B2] ( 0x150C [B2] ) SPI_ ENB X 1 0 0 MOSI ( SPI Master Output ; Slave Input) SDI (DF_SPI) P1.5/ MOSI / SDI / /CS3 1 0 3 2 1 0 MISO ( SPI Master Input ; Slave Output ) SPI_ ENB DF_ ENB 0 0 1 SDO (DF_SPI) 1 P1.6/MISO / SDO ： P3.4_A0_Sel 150C[5] 0 1 UART_EN & SIM_EN 1554[7-6] 00 01 10 11 X UART_RXD1 SIM_CLK P3.4/ A0/ RXD1/SIM_CLK P3.5_A1_Sel 150C[6] 0 UART_EN 1554[7] 0 1 P3.5/ A1/ TXD1 UART_TXD1 1 - 16 - Publication Release Date: May, 2007 Revision 1.3 W681307 5. 5.1 SYSTEM DIAGRAM Function Block Diagram The function block diagrams of the MCU chip and speech interface are shown below 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 KeyPad USB CODEC PCM & MIXER Winbond Turbo 8032 32K MASK ROM UART SPI - 17 - ： AEC 4K RAM W2S Publication Release Date: May, 2007 Revision 1.3 W681307 5.2 I/O Cells in Winbond MCU Chip Chartered Semiconductor (Artisan) 0.25um Integral I/O cell library PC3B02U 3V CMOS 3-State I/O Pad with Pull-up Resistor, 2mA VDD OEN I PAD CIN Figure 5-1: PC3B02U pad PC3B02D 3V CMOS 3-State I/O Pad with Pull-down Resistor, 2mA OEN I PAD CIN VSS Figure 5-2: PC3B02D pad PC3o02 3V CMOS Output Pad, 2mA I PAD Figure 5-3: PC3o02 pad PC3D01D 3V CMOS Input only Pad with Pull-down Resistor PAD CIN VSS Figure 5-4: PC3D01D pad - 18 - Publication Release Date: May, 2007 Revision 1.3 W681307 PC3D01U 3V CMOS Input only Pad with Pull-up Resistor VDD PAD CIN Figure 5-5: PC3D01U pad PC3D21U 3V CMOS Schmitt non inverting Input only Pad with Pull-up Resistor VDD PAD CIN Figure 5-6: PC3D01D pad PC3T01/02 3V CMOS 3-State Output Pad, 1mA/2mA OEN I PAD Figure 5-7: PC3T01 pad - 19 - Publication Release Date: May, 2007 Revision 1.3 W681307 6. 6.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltage Referenced to AGND pin) PARAMETER Core Power Supply Voltage, pin 53, 92 I/O Power Supply Voltage, pin 17, 26, 59 Power Supply Voltage , pin 80 DC Supply Voltage for USB Ouput Stage Operating Temperature Storage Temperature SYMBOL DVDD IOVDD AVDD VDD_USB TOP TSTG RATING 1.9 2.7 ~ 3.6 3.0 ~ 3.6 3.0 ~ 3.6 -10 to +55 -85 to +85 UNIT V V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 6.2 DC Characteristics (AGND = 0 volt TOP = -10 to +55 ) PARAMETER Core Operating Current I/O Operating Current Analog Operating Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Input Capacitance SYM. Icore II/O IANA VIH VIL VOH VOL IIL IIH CIN CONDITION MIN. VDD ×0.7 0 VDD× 0.75 0 -10 -10 - TYP. 6 6 5 MAX . - UNIT mA mA mA All digital input pins All digital input pins DT, SSP Tx DT, SSP Tx AGND ≤ Vin ≤ AVDD AGND ≤ Vin ≤ AVDD All digital input pins to AGND - VDD ×0.3 VDD× 0.25 +10 +10 10 - 20 - Publication Release Date: May, 2007 Revision 1.3 ℃ ℃ ℃ V V V V µA µA pF W681307 6.3 Analog Transmission Characteristics (AVDD =+3.0V ±5%, AGND = 0 volt , Top = -10 to +55° C ; all analog signal referenced to VAG; 64 Kbps PCM; FST = FSR = 8 KHz; BCLKT = BCLKR = 1.536 MHz; MCLK = 13.824 MHz ; Unless otherwise noted) 6.3.1 Amplitude Response for Analog Transmission Performance PARAMETER Absolute Level * Max. Transmit Level SYM. LABS TXMAX CONDITION 0 dBm0 = -3.0 dBm @ 600 TYP. MIN. A/D MAX. D/A MIN. MAX. UNIT -----0.5 -0.5 -0.5 -0.5 -0.20 -0.35 0.549 VAG 1dB ------------------------- -----------------------0.3 -1.0 -1.6 -----------3 -0.20 -0.35 -0.5 ----+0.3 +1.0 +1.6 -----60 -40 -20 -5 +0.15 +0.15 Vrms Vpk --- 15 Hz 50 Hz 100 Hz Frequency Response, Relative to 0 dbm0 @ 1020Hz 200 Hz GRTV 300 to 3000 Hz 3300 Hz 3400 Hz 4000 Hz 4600 to 7000 Hz Gain Variation vs Level Tone (1020 Hz relative to -10 dBm0) +3 to -40 dBm0 GLT -40 to -50 dBm0 -50 to -55 dBm0 6.3.2 Distortion Characteristics for Analog Transmission Performance TYP . --------------------- PARAMETER Absolute Group Delay SYM. DABS CONDITION 1600 Hz 500 to 600 Hz 600 to 1000 Hz 1000 to 2600 Hz 2600 to 2800 Hz 2800 to 3000 Hz +3 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0 Group Delay Referenced to 1600 Hz DRTV Total Distortion vs. Level Tone (1020 Hz, Mu-Law, CMessage) DLT  dB 0 -12 -40 -0.2 -0.4 -0.8 -0.5 ----+0.2 +0.4 +0.8 dB TRANSMIT MIN. ------------36 36 29 25 RECEIVE MI N. ------------34 36 30 25 MA X. 250 250 200 70 100 145 --------- MA X. 200 30 20 70 120 200 --------- UNIT µS µS dBC - 21 - Publication Release Date: May, 2007 Revision 1.3 W681307 6.4 Analog Electrical Characteristics (OP Amplifer TG and VAG; AVDD = +3.0V ±5%, AGND = 0V; Top = -10 to +55° C) PARAMETER Input Current of TG AC Input Impedance to VAG for TG (1 kHz) Input Capacitance of TG Input Offset voltage of TG Input Common Mode Voltage of TG Input Common Mode Rejection Ratio of TG Gain Bandwidth Product of TG (10kHz) DC Open Loop Gain of TG Rload ≥ 10 K Bandgap voltage VAG Output Voltage VAG Output Current with less than 50 mV change in output voltage Power Supply Rejection Ratio SYM. CONDITIONS TI1+, TI1TI2+, TI2- MIN. --------0.5 TYP. ±0.01 1.0 ------60 MAX. ±1.0 UNIT µA M pF mV V dB KHz RTIIN CTIIN VOFIN VCMV TI1+, TI1TI2+, TI2TI1+, TI1TI2+, TI2TI1+, TI1TI2+, TI2TI1+, TI1TI2+, TI2TI1+, TI1TI2+, TI2TI1+, TI1TI2+, TI2- AVDD– 0.8 100 975 dB V V mA IVAG VVAG PSRR TG --- 6.5 Power Drivers – PO1, 2 ( AVDD = +3.0V ±5%, AGND = 0V; Top = -10 to +55° C) PARAMETER Output Offset Voltage of PO1+ (PO2+) relative to PO1-(PO2-) PO1+(PO2+), PO1-(PO2-) Output Current @ VAG=1.5V, RL=120, THD0x1700 [1] =1’b1). Reset the bit for one bit per 1 Bitclk. =1: disabling the B1 channel of the PCM Highway. =0: enabling the B1 channel of the PCM Highway. PCMB2_dis Half rate PCMB1_dis 10.7.2.2 Address 0x1701h Bit 7 TX delay1 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX delay1 Set the values for delaying the transmitted bits of PCM B1 channel after the rising edge of the frame pulse. The resolution is one bitclk in full date rate and two Bitclk in half data rate. 10.7.2.3 Address 0x1702h Bit 7 TX delay2 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX delay2 Set the values for delaying the transmitted bits of PCM B2 channel after the tail bit of PCM B1 channel. The resolution is one PCM Bitclk in full date rate and two Bitclk in half data rate. Publication Release Date: May, 2007 Revision 1.3 - 63 - W681307 10.7.2.4 Address 0x1703h Bit 7 RX delay1 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX delay1 Set the values for delaying the received bits of PCM B1 channel after the rising edge of the Fsync. The resolution is one Bitclk in full date rate and two Bitclk in half data rate. 10.7.2.5 Address 0x1704h Bit 7 RX delay2 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX delay2 Set the values for delaying the received bits of PCM B2 channel after the tail bit of Rx PCM Highway B1 channel. The resolution is one Bitclk in full date rate and two Bitclk in half data rate. 10.7.2.6 Address 0x1708h Bit 7 PCM channel format and delay control of 2nd group (PCM B3, PCM B4) Access Mode R/W Bit 6 Bit 5 Value At Reset 0x02 Bit 4 RESERVED Bit 3 Bit 2 RESERVED Bit 1 Bit 0 RESERVED PCMB3_dis Data 16/8bits Hizen Half/Full Half rate PCMB4_dis Hizen Half/Full Data 16/8bits Set the bit to receive/transmit 16 bits; Reset the bit to receive/transmit 8 bits. Set the bit to tristate in the end of the bit. Reset the bit to tristate in the falling edge of the end of the bit. =1: disabling the B4 channel of the PCM Highway. =0: enabling the B4 channel of the PCM Highway. Set the bit for one bit per 2 Bitclk (during data length being 16 bits=>0x1708 [1] =1’b1). Reset the bit for one bit per 1 Bitclk. =1: disabling the B3 channel of the PCM Highway. =0: enabling the B3 channel of the PCM Highway. PCMB4_dis Half rate PCMB3_dis - 64 - Publication Release Date: May, 2007 Revision 1.3 W681307 10.7.2.7 Address 0x1709h Bit 7 TX delay3 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX delay3 Set the values for delaying the transmitted bits of PCM Highway B3 channel after the tail bit of TX PCM Highway B2 channel. The resolution is one Bitclk in full date rate and two Bitclk in half data rate. 10.7.2.8 Address 0x170Ah Bit 7 TX delay4 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX delay4 Set the values for delaying the transmitted bits of PCM Highway B4 channel after the tail bit of TX PCM Highway B3 channel. The resolution is one Bitclk in full date rate and two Bitclk in half data rate. 10.7.2.9 Address 0x170Bh Bit 7 RX delay3 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX delay3 Set the values for delaying the received bits of PCM Highway B3 channel after the tail bit of RX PCM Highway B2 channel. The resolution is one Bitclk in full date rate and two Bitclk in half data rate. 10.7.2.10 Address 0x170Ch Bit 7 Rx delay4 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX delay4 Set the values for delaying the received bits of PCM Highway B4 channel after the tail bit of RX PCM Highway B3 channel. The resolution is one Bitclk in full date rate and two Bitclk in half data rate. - 65 - Publication Release Date: May, 2007 Revision 1.3 W681307 10.8 Digital Gain Multiplexer There are 4 fine-tune on-chip gain stage allocated between multiplexer interface and half acoustic canceller block or behind multiplexer interface. This gain stage is implemented by a digital multiplexer to provide a range of +12 dB to –12 dB with a resolution of 0.5 dB per step. Figure 10-3 is shown the location of this digital gain multiplexer. The 4 channels FT Gain Stage support gain adjustment for linear PCM signal for each PCM channel. Each channel has its independent gain registers for gain setting. Gain Stage #146Eh C0 CODEC #146Fh #146Ch Half AEC C1 Figure 10-3 The location of digital fine-tuning gain stage Multiplexer C2 #146Dh #146Ah #146Bh # 1468h C3 # 1469h 10.8.1 10.8.1.1 Address 0x1468 Fine-Tuning Gain Stage Registers FTInGain3 Access Mode R/W Value At Reset 0x00 Nominal Value - 66 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 RESERVED Bit 6 RESERVED Bit 5 FTInGain[5] Bit 4 FTInGain[4] Bit 3 FTInGain[3] Bit 2 FTInGain[2] Bit 1 FTInGain[1] Bit 0 FTInGain[0] Refer to Table 10-1 for fine tune input gain. This gain is applied to the input data of processor channel C3. 10.8.1.2 Address 0x1469 Bit 7 RESERVED FTOutGain3 Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 FTOutGain[5] FTOutGain[4] FTIOutGain[3] FTOutGain[2] FTOutGain[1] FTOutGain[0] Refer to Table 10-1 for fine tune output gain. This gain is applied to the output data of processor channel C3. 10.8.1.3 Address 0x146A Bit 7 RESERVED FTInGain2 Access Mode R/W Bit 6 RESERVED Bit 5 FTInGain[5] Value At Reset 0x00 Bit 4 FTInGain[4] Nominal Value Bit 3 FTInGain[3] Bit 2 FTInGain[2] Bit 1 FTInGain[1] Bit 0 FTInGain[0] Refer to Table 10-1 for fine tune input gain. This gain is applied to the input data of processor channel C2. 10.8.1.4 Address 0x146B Bit 7 RESERVED FTOutGain2 Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 FTOutGain[5] FTOutGain[4] FTIOutGain[3] FTOutGain[2] FTOutGain[1] FTOutGain[0] Refer to Table 10-1 for fine tune output gain. This gain is applied to the output data of processor channel C2. 10.8.1.5 Address 0x146C Bit 7 RESERVED FTInGain1 Access Mode R/W Bit 6 RESERVED Bit 5 FTInGain[5] Value At Reset 0x00 Bit 4 FTInGain[4] Nominal Value Bit 3 FTInGain[3] Bit 2 FTInGain[2] Bit 1 FTInGain[1] Bit 0 FTInGain[0] Refer to Table 10-1 for fine tune input gain. This gain is applied to the input data of processor channel C1. - 67 - Publication Release Date: May, 2007 Revision 1.3 W681307 10.8.1.6 Address 0x146D Bit 7 RESERVED FTOutGain1 Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 FTOutGain[5] FTOutGain[4] FTIOutGain[3] FTOutGain[2] FTOutGain[1] FTOutGain[0] Refer to Table 10-1 for fine tune output gain. This gain is applied to the output data of processor channel C1. 10.8.1.7 Address 0x146E Bit 7 RESERVED FTInGain0 Access Mode R/W Bit 6 RESERVED Bit 5 FTInGain[5] Value At Reset 0x00 Bit 4 FTInGain[4] Nominal Value Bit 3 FTInGain[3] Bit 2 FTInGain[2] Bit 1 FTInGain[1] Bit 0 FTInGain[0] Refer to Table 10-1 for fine tune input gain. This gain is applied to CODEC PCM output data. This gain can be also adjusted to consider the power requirement of the half acoustic echo canceller. 10.8.1.8 Address 0x146F Bit 7 RESERVED FTOutGain0 Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 FTOutGain[5] FTOutGain[4] FTIOutGain[3] FTOutGain[2] FTOutGain[1] FTOutGain[0] Refer to Table 10-1 for fine tune output gain. This gain is applied to CODEC PCM input data. This gain can be also adjusted to consider the power requirement of the half acoustic echo canceller. - 68 - Publication Release Date: May, 2007 Revision 1.3 W681307 Table 10-1 mute. ： Fine-tuning input, output gain (decimal index). The 5-bit numbers allow +/- 12 dB adjustment in 0.5 dB steps and hard FT In/out Gain [4:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 Gain Value 0 dB 0.5 dB 1.0 dB 1.5 dB 2.0 dB 2.5 dB 3.0 dB 3.5 dB 4.0 dB 4.5 dB 5.0 dB 5.5 dB 6.0 dB 6.5 dB 7.0 dB 7.5 dB 8.0 dB 8.5 dB 9.0 dB 9.5 dB 10.0 dB 10.5 dB 11.0 dB 11.5 dB 12.0 dB FT In/out Gain [4:0] 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x3F Gain Value -0.5 dB -1.0 dB -1.5 dB -2.0 dB -2.5 dB -3.0 dB -3.5 dB -4.0 dB -4.5 dB -5.0 dB -5.5 dB -6.0 dB -6.5 dB -7.0 dB -7.5 dB -8.0 dB -8.5 dB -9.0 dB -9.5 dB -10.0 dB -10.5 dB -11.0 dB -11.5 dB -12.0 dB Mute - 69 - Publication Release Date: May, 2007 Revision 1.3 W681307 11. PROCESSOR INTERFACE 11.1 Overview The Processor Interface controls reads and writes made by the Processor to the on-chip RAM and on-chip registers. 11.2 Functionality Figure 11-1 shows the processor interface block diagram. Figure 11-1 Illustration of the Processor Interface 11.3 Processor Access Sequencer The Processor Access Sequencer has 2 functions • • Internal Register access sequencing On-Chip RAM access sequencing External RAM accesses, external ROM accesses and internal register reads are performed directly by the 8032Turbo, the Address Decoder and Read Multiplexer. No action is required by the Processor Access Sequencer. The operation of the Processor Access Sequencer for internal register writes is shown in Figure 11-2. Note that • • The sequence of a register write is not affected by the setting of STRECH. The Internal Register Clock Enable signal SysClock2En is active for 4 cycles to allow internal events to be scheduled after a ： - 70 Publication Release Date: May, 2007 Revision 1.3 ： W681307 • register writes. The Internal Address Bus IntAddress is a latched version of the Processor Address bus, updated when an internal accesses is required. This reduces internal transitions on the chip to save power. Figure 11-2 Timing of Internal Register Writes - 71 - Publication Release Date: May, 2007 Revision 1.3 W681307 The operation of the Processor Access Sequencer for access to the On-Chip RAM is shown in Figure 11-3. Note that • • ： The On-Chip RAM is a clocked-synchronous RAM. The data read out of the On-Chip RAM is latched in the Processor Interface. Figure 11-3 Timing of On-Chip RAM Access - 72 - Publication Release Date: May, 2007 Revision 1.3 W681307 11.4 • • • • Read Multiplexer The Read Multiplexer multiplexes the following data onto the internal 8032Turbo data bus: On-chip registers On-Chip RAM Speech Processor Registers Off-Chip Bus Interface Each function performs local address decoding for both Reads and Writes. For register reads, each block multiplexes the addressed register onto a single output bus and asserts a Data Valid signal. All internal modules present zero on the read data buses when not selected. In the case of support logic, processor interface, speech interface and interface logic these modules decode a lower part of the address bus, so may present data out at various points in the memory map. For other blocks all the decoding is done within the processor interface. A data inputs are qualified with appropriate Address Decoder outputs. This ensures that only the required sub-module data is presented to the 8032Turbo. 11.5 11.5.1 Processor Interface Control Registers AuxOpPort Access Mode R/W Bit 6 CS1R2 Bit 5 CS1R1 Address 0x1470 Bit 7 RESERVED Value At Reset 0x00 Bit 4 CS1R0 Nominal Value Bit 3 AuxOp Port1En Bit 2 AuxOpPort1 Bit 1 AuxOp Port0En Bit 0 AuxOpPort0 CS1 and CS2 can be set as general output port, 0x1470 bit1 and bit3 enable this function independently. AuxOpPort0 means CS1 and AuxOpPort1 means CS2. When you enable the general output function, the CS1/CS2 will be not in address decode mode. Figure 11-4 shows /CS1 & /CS2 output multiplexer. AuxOpPort0 AuxOpPort0En AuxOpPort1 The AuxOpPort data bits contain TRUE data. When set, enable the AuxOpPort 0. The AuxOpPort data bits contain TRUE data. AuxOpPort1En When set, enable the AuxOpPort 1. The AuxOpPort enables are active high. - 73 - Publication Release Date: May, 2007 Revision 1.3 ] 2: 3[ 2 7 4 1 x 0 0 ] 3[0741x 0 n E 1t r o P p O x u A n E 1t r o P p O x u A n E 1t r o P p O x u A n E 1t r o P p O x u A 1 2 0 1 3 3 3 3 2 S C/ e m a N ni P e m a N ni P e m a N ni P e m a N ni P ]2[ 0741x0 1t r o P p O x u A 1t r o P p O x u A 1t r o P p O x u A 1t r o P p O x u A ] 0: 1[ 2 7 4 1 x 0 ] 0: 1[ 2 7 4 1 x 0 ] 0: 1[ 2 7 4 1 x 0 ] 0: 1[ 2 7 4 1 x 0 0 0 0 0 ] 1[0741x 0 ] 1[0741x 0 ] 1[0741x 0 ] 1[0741x 0 n E 0t r o P p O x u A 1 2 0 0 0 0 1 3 1 S C/ 1 S C/ 1 S C/ 1 S C/ e m a N ni P ]0[ 0741x0 ]0[ 0741x0 ]0[ 0741x0 ]0[ 0741x0 0t r o P p O x u A 0t r o P p O x u A The CS1 range is defined as: 2 S C/ 2 S C/ 2 S C/ 2 S C/ D R/ R W/ R W/ R W/ 1 S C/ 1 S C/ 1 S C/ 1 S C/ D R/ D R/ D R/ D R/ R W/ R W/ R W/ R W/ 11.5.2 Address 0x1471 CS1R2 0 0 0 0 1 1 1 1 DiagSel CS1R1 0 0 1 1 0 0 1 1 Access Mode R/W CS1R0 0 1 0 1 0 1 0 1 Figure 11-4 Value At Reset 0x00 /CS1 & /CS2 output multiplexer Depth 4KB 8KB 12KB 16KB 20KB 24KB 28KB 32KB - 74 Nominal Value Address Range 0x8000 0x8FFF 0x8000 0x9FFF 0x8000 0xAFFF 0x8000 0xBFFF 0x8000 0xCFFF 0x8000 0xDFFF 0x8000 0xEFFF 0x8000 0xFFFF Publication Release Date: May, 2007 Revision 1.3 W681307 W681307 Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 RESERVED 11.5.3 Address 0x1472 Bit 7 RESERVED Diag_CS Access Mode R/W Bit 6 CS2R2 Bit 5 CS2R1 Value At Reset 0x00 Bit 4 CS2R0 Nominal Value Bit 3 CS2_Sel[1] Bit 2 CS2_Sel[0] Bit 1 CS1_Sel[1] Bit 0 CS1_Sel[0] CS1 & CS2 can be selected output for setting the bits CS1 & CS2 output multiplexer (See Figure 11-4) CS1[1:0] / CS2[3:2] 00 01 10 11 Output CS1 / CS2 CS1|RD / CS2|RD CS1|WD / CS2 |WD ~((CS 1 | RD) & (CS1 | WR)) / ~((CS 2 | RD) & (CS2 | WR)) The CS2 range is defined as: CS2R2 0 0 0 0 1 1 1 1 CS2R1 0 0 1 1 0 0 1 1 CS2R0 0 1 0 1 0 1 0 1 Depth 4KB 8KB 12KB 16KB 20KB 24KB 28KB 32KB Address Range 0xF000 0xFFFF 0xE000 0xFFFF 0xD000 0xFFFF 0xC000 0xFFFF 0xB000 0xFFFF 0xA000 0xFFFF 0x9000 0xFFFF 0x8000 0xFFFF CS1 and CS2 can address 32 K totally. So for example, you set CS2 for addressing 12 KB, then CS1 only address 20KB . CS1: 0x8000H~ 0xCFFFH ; CS2 : 0xD0000H~0xFFFFH. - 75 - Publication Release Date: May, 2007 Revision 1.3 W681307 11.5.4 Address 0x1473 Bit 7 RESERVED Diag_CS3 Access Mode R/W Bit 6 RESERVED Bit 5 RD_WR_BLK Value At Reset 0x00 Bit 4 CS2_WAIT _EN Nominal Value Bit 3 CS3_SEL[1] Bit 2 CS3_SEL[0] Bit 1 PWR_SAVE[1] Bit 0 PWR_SAVE[0] 3 / WR 2 /RD 1 / CS3 0 Pin Name /CS3 0x 1473[3:2] Figure 11-5 CS3 Output multiplexer CS3 output multiplexer is shown in Figure 11-5. Address mapping range of CS3 is 0x2000~0x5FFF CS3_sel[1:0] 00 01 10 11 Output CS3 CS3 | RD CS3 | WD ~((CS 3 | RD) & (CS3 | WR)) CS2_WAIT_EN This is a wait state enable bit for CS2 controlled device. When set this bit, the WR/RD duration to CS2 controlled device will last from 4 clock cycles to 8 clock cycles. When set this bit, the external RD/WR signal will not active (blocked) when access internal RAM/register (0x0000 to 0x1FFF and 0x6000 to 0x7FFF), the default is not blocked. You can set PWR_SAVE [1:0] to control AD/ADDR bus output state for I/O power save purpose. PWR_SAVE[1:0] 00 01 10 11 AD/ADDR bus No power save feature. AD/ADDR bus only active when T8032 RD/WR in the Mask ROM mode. AD/ADDR bus only active when T8032 RD/WR external device (0x8000~0xFFFF),in the Mask ROM mode. AD/ADDR bus always inactive. RD_WR_BLK PWR_SAVE [1:0] - 76 - Publication Release Date: May, 2007 Revision 1.3 W681307 11.5.5 Address 0x1474 Bit 7 RESERVED Multiplier_Enable Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 Mul8x8_en Mul8x8_en This is an enable bit of a fast 8x8 multiplier in T8032.When set this bit, a fast T8032 internal 8x8 multiplier will be active otherwise the original T8032 add-shift multiplier is the default choice. 11.6 In System Programming Mode In System Programming mode is designed for fast program on board flash. Flash type includes 29, 39 and 49 series. The chip is provided two ISP entry modes. One is hardware setting and the other is software command mode. This function comes with the PC software, which transfer the binary code to internal T8032 to program the external ROM flash. ISP function use internal T8032 UART or USB port to transfer data, the default baud rate of the UART port is 9600bps, which can be set by remote PC program. There are four baud-rates for selection, 9600bps, 19200bps, 28800bps and 57600bps. The double-speed MCU chip (2x), you can select optional 115200bps for flash program. 11.6.1 Hardware Setting Usage In the initial power-up state, the /CS2 pin will replaced as ISP function hardware setting pin. When /CS2 pin set to low and re-power up the system, the chip will execute the internal ISP code, and wait for PC command and binary data to update the external ROM flash. If the /CS2 is set to output purpose pin (the pin is default pull-up), this chip will in normal mode. The flash needed an external write signal. The ISP_WR pin of the chip needs to connect to the /WR pin of the external Flash and which pin only active in ISP operation. 11.6.2 Software Command Usage This ISP function can provide the system program update from the internal USB or UART ports with software command and don’t need any hardware modification. Therefore the baseband chip doesn’t need extra circuit to support this function. Figure 11-6 is shown the function description and specification. - 77 - Publication Release Date: May, 2007 Revision 1.3 W681307 Figure 11-6 The software ISP operation procedure 11.6.3 Address 0x1900 Bit 7 ISP_EN ISP_CTRL (Hardware & Watchdog Reset Control Register) Access Mode RW Bit 6 Reserved Bit 5 Reserved Value At Reset 0x00 Bit 4 Reserved Nominal Value Bit 3 Reserved Bit 2 Reserved Bit 1 USB_ISP Bit 0 UART_ISP This ISP control register is provided the In-system-programming function to update the system program code without modification hardware. This function can be enabled by the bit 7 of ISP_CTRL control register. And the enable command which is come from the internal UART port or USB interface. UART_ISP This bit is reserved for ISP mask rom program recognition which type ISP mode is enabled. When ISP enabled command is come from internal UART port. Then the normal program will set this bit for recognition in ISP mode period before enabled ISP_EN bit. And download program data will come from UART port in the ISP programming period. The bit function is the same as UART_ISP. When set this bit will enable ISP mode to program the external flash ROM via the internal USB interface or UART port. USB_ISP ISP_EN 11.6.4 Address 0x1901 Bit 7 Blocked (for test modes) Specific Register Access Mode RW Bit 6 Reserved Bit 5 Reserved Value At Reset 0x00 Bit 4 Reserved Nominal Value Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved - 78 - Publication Release Date: May, 2007 Revision 1.3 edoc MOR noitarepo edom eldi ro BSU morf hsalf lanretxe ot edoc margorp daolnwod RST RST hsalF lanretxe dnabesaB UCM otni lanretxe eht nur ot noitarepo lamron ot hctiws erawdraH .edoc MOR hsalf ot noitarepo edoc PSI MOR ksam lanretni dnabesaB ecruos dnammoc PSI eht no tnedneped trop TRAU fo edoc MOR PSI ksam lanretni .7.1P ot hctiws-dnab lliw pihc dnabesab fo sretsiger lanretni eht nur ot hctiws erawdraH eht lla eht dnA .dnabesab edom UCM otni eldi hsalF lanretxe dnabesaB noitarepo edoc MOR NE_PSI_WH TSR_PSI NE_PSI ISP hardware module generates ISP hardware module generates ISP Program completes the ISP mode Program set ISP_EN W681307 11.7 MASK ROM Mode Mask ROM Mode is designed to use the internal mask ROM, besides this MCU chip also can disable the internal mask ROM to use external flash ROM. Although MCU chip provide ISP mode and MASK ROM mode but you cannot use it simultaneously. Each function is independent function. 11.7.1 Usage When set EXT_ROM pin to low, the chip will execute the internal mask ROM code. When set EXT_ROM pin to high, the chip will execute the external flash ROM code. - 79 - Publication Release Date: May, 2007 Revision 1.3 W681307 12. SPEECH PROCESSOR The Speech Processor provides a complete implementation, including • • • • 4 duplex channels 1 channel Echo Canceller A Mixer Block Programmable Tone Generators The Speech Processor supports A-law, µ-law and 16-bits linear PCM formats. Echo canceller channels support 16 bits linear PCM only. The Speech Processor is implemented by an optimized micro-coded DSP, an external FIR Filter Engine and one digital gain multiplexer. The architecture of the Speech Processor can be shown in Figure 12-1. The Microcode DSP Core: • • Performs Tone Generation Performs PCM Mixing The FIR Engine: • • • • Performs real-time Echo Estimation Implements Network Echo Suppression Calculates the Echo Cancellation filter coefficients Performs intermediate calculations on the Echo Estimation error 12.1 • • • • • Transcoder DSP The Transcoder DSP is a low power implementation and has the following features: Low power consumption and low gate count Group delay under 14 µs / channel DTMF and call progress tones Sidetone generation and Volume control Requires only 4.1 MIPS per channel The Transcoder DSP supports A-law, µ-law and 16-bits linear PCM formats. Format selection is programmable on a by-channel basis. The signal flow (per channel) is shown in Figure 12-1 below INPUT GAIN PCM_IN PCM FORMAT TONE GEN PCM_OUT OUTPUT GAIN Figure 12-1 Transcoder signal flow There are dual-tone generators for each PCM channel. These can generate DTMF and common signaling tones, as well as user notification tones. The tones may be added in either direction. A mixer function is enabled by setting 1401[0]. Four full-duplex PCM - 80 - ： + MIXER MATRIX SIDE TONE ： + MIXER MATRIX + Publication Release Date: May, 2007 Revision 1.3 W681307 channels can be connected / mixed together in any combination. This function is controlled by programmable registers. Moreover, the speech logic interface (which is not needed by the CODEC) of four channels must be enabled. 12.2 12.2.1 The Description of the Activation Registers MIXER_EN Access Mode R/W Bit 6 Bit 5 Address 0x1401 Bit 7 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 MIXER_EN Blocked Blocked Blocked Blocked Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) MIXER_EN Set to enable the mixer block. 12.2.2 Address 0x1420 Bit 7 SPEECH LOGIC_EN Access Mode R/W Bit 6 Bit 5 Value At Reset 0x04 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 SPEECH LOGIC_EN Blocked Blocked Blocked Blocked Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) SPEECH LOGIC_EN Set to enable speech logic interface (which is not needed by the CODEC) of four channels. 12.3 The Description of Transcoder DSP Registers The transcoder block is programmed via microprocessor accessible programming registers. All registers allow read/write access and reset to zero except as noted. All bits not specified below are reserved or blocked and should only be written with zeros. Unspecified bits read back zero. The transcoder registers are divided into `Global registers' and `Channel-specific registers'. Global registers • Consist of SideTone (0x148D) and Lookback_EN (0x148E) registers. Channel-specific registers Channel-specific registers appear in four groups at offsets of sixteen bytes. • • • • Channel 0 registers appear at addresses 0x1480 -> 0x148C Channel 1 registers appear at addresses 0x1490 -> 0x149C Channel 2 registers appear at addresses 0x14A0 -> 0x14AC Channel 3 registers appear at addresses 0x14B0 -> 0x14BC ： ： - 81 - Publication Release Date: May, 2007 Revision 1.3 W681307 12.3.1 Address 0x1480 Bit 7 Connect0 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x01 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 PCM channel 3 PCM channel 2 PCM channel 1 PCM channel 0 Blocked Blocked Blocked * Blocked (for test modes) (for test modes) (for test modes) (for test modes) Specify mixing among four PCM channels. This register enables the connections of each PCM channels. Bits [7:4] correspond to PCM channels 3:0. * Blocked (for test modes) must be set to 1. When the value of the bit is set to 1, it enables the addition of the corresponding channel in mixing. An additive connection is set up between the specified channels. 12.3.2 Address 0x1481 Bit 7 RESERVED Specified Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 Bit 0 Blocked Blocked (for test modes) (for test modes) 12.3.3 Address 0x1482 Bit 7 RESERVED Specified Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 Blocked (for test modes) 12.3.4 Address 0x1483 Bit 7 RESERVED Specified Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 Blocked (for test modes) - 82 - Publication Release Date: May, 2007 Revision 1.3 W681307 12.3.5 Address 0x1484 Bit 7 RESERVED PCMmode0 Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 COMP_FORMAT Bit 0 PCM_LINEAR PCM_LINEAR =1, PCM port 0 operates in 16-bit linear mode. =0, 8-bit compressed PCM. If PCM port 0 is in compressed mode, =1, A-law, =0, µ -law COMP_FORMAT 12.3.6 Address 0x1485 Bit 7 RESERVED InputGain0 Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 InputGain[3] Bit 2 InputGain[2] Bit 1 InputGain[1] Bit 0 InputGain[0] InputGain[3:0] PCM input gain table is listed as below Table 12-1. This gain is applied directly to the PCM input value. 12.3.7 Address 0x1486 Bit 7 RESERVED OutputGain0 Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 OutputGain[3] OutputGain[2] OutputGain[1] OutputGain[0] OutputGain[3:0] PCM output gain table is listed as below Table 12-2. This gain is applied after the Mixer Matrix and tone generation. 12.3.8 Address 0x1488 Bit 7 ToneFreqA0 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 ToneFreqA Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Frequency of tone A = ToneFreqA * 15.625 (Hz) - 83 - Publication Release Date: May, 2007 Revision 1.3 W681307 12.3.9 Address 0x1489 Bit 7 ToneFreqB0 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 ToneFreqB Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Frequency of tone B = ToneFreqB * 15.625 (Hz) 12.3.10 Address 0x148A Bit 7 RESERVED ToneVolA0 Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 ToneVolA[4] Nominal Value Bit 3 ToneVolA[3] Bit 2 ToneVolA[2] Bit 1 ToneVolA[1] Bit 0 ToneVolA[0] Tone level is listed as below Table 12-3 for tone generator A. 12.3.11 Address 0x148B Bit 7 RESERVED ToneVolB0 Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 ToneVolB[4] Nominal Value Bit 3 ToneVolB[3] Bit 2 ToneVolB[2] Bit 1 ToneVolB[1] Bit 0 ToneVolB[0] Tone level is listed as below Table 12-3 for tone generator B. 12.3.12 Address 0x148C Bit 7 RESERVED ToneEna0 Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 Tx_tone Bit 0 Rcv_tone Rcv_tone =1, add tone generators to the receiving (PCM_OUT) path. Receive tones are added just before the PCM output gain stage. Tx_tone =1, add tone generators to the transmitting (PCM_IN) path. Transmit tones are added just after the PCM input gain stage. WARNING: enabling tones in both directions at the same time causes the output frequencies to double. - 84 - Publication Release Date: May, 2007 Revision 1.3 W681307 12.3.13 Address 0x148D Bit 7 RESERVED SideTone Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 SideTone[4] Nominal Value Bit 3 SideTone[3] Bit 2 SideTone[2] Bit 1 SideTone[1] Bit 0 SideTone[0] SideTone[4:0] SideTone[4:0] Side tone gain is listed as below Table 12-4. This is applied to all active PCM channels between the Mixer Matrix and PCM formatting. Please refer to 0x14AF to enable the active sidetone channel. =0, to disable side tone. 12.3.14 Address 0x148E Bit 7 Loopback_EN Access Mode R/W Bit 6 Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 * Blocked RESERVED (for test modes) Blocked Blocked Blocked Loopback_EN (for test modes) (for test modes) (for test modes) Loopback_EN =1, loopback behind the side tone function in the transmitting (PCM_IN) path. * Blocked (for test modes) must be set to 1. 12.3.15 Address 0x148F Bit 7 Specified Register Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Blocked (for test modes) 12.3.16 Address Connect1 ~ ToneEna1 Access Mode R/W Value At Reset 0x00 Nominal Value 0x1490 ~ 0x149C The functions are the same as channel 0. 12.3.17 Address Connect2 ~ ToneEna2 Access Mode R/W Value At Reset 0x00 Nominal Value 0x14A0 ~ 0x14AC The functions are the same as channel 0. - 85 - Publication Release Date: May, 2007 Revision 1.3 W681307 12.3.18 Address 0x14AF Bit 7 RESERVED SideToneChannel_Ena Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x01 Bit 4 RESERVED Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 SideTone_ch3 SideTone_ch2 SideTone_ch1 SideTone_ch0 The register can enable side tone individually for the each active pcm channel. 12.3.19 Address Connect3 ~ ToneEna3 Access Mode R/W Value At Reset 0x00 Nominal Value 0x14B0 ~ 0x14BC The functions are the same as channel 0. 12.4 PCM Mixer Matrix The registers Connect0-3 specify channels which should be connected together and enable the corresponding PCM channels. The connection registers of each specified PCM channels can be set to the same value simultaneously. The result is the same that one of each registers be set. For example, The PCM0 and PCM1 channels need to be connected. So the 1480 and 1490 can be set to 31. The effect is the same that only 1480 or 1490 is set. 12.5 Gain Tables There are four gain functions in this block: PCM I/O gain, side tone gain and tone gain (level). Table 12-1 The PCM Input gain is provided to allow minor corrections for board-level analogue gain problems. The 4-bit numbers allow +/- 10 dB adjustments and hard mute. InputGain (3:0) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Nominal gain 0 dB +1 dB +2 dB +3 dB +4 dB +6 dB +8 dB +10 dB -∞ (Hard mute) -10 dB -8 dB -6 dB -4 dB -3 dB -2 dB -1 dB Actual gain 0 dB +1.0 +2.0 +2.8 +4.2 +6.0 +8.0 +9.5 -∞ -10.1 -8.5 -6.0 -4.1 -3.2 -1.8 -1.2 Publication Release Date: May, 2007 Revision 1.3 - 86 - W681307 Table 12-2 The PCM Output gain is provided to allow minor corrections for board-level analogue gain problems. The 4-bit numbers allow +/- 16 dB adjustments and hard mute. OutputGain(3:0) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Nominal gain 0 dB +1.5 dB +3 dB +5 dB +7 dB +10 dB +13 dB +16 dB -∞ (Hard mute) -16 dB -13 dB -10 dB -7 dB -5 dB -3 dB -1.5 dB Actual gain 0 dB +1.9 +3.5 +4.9 +7.0 +9.9 +13.5 +15.6 -∞ -18.1 -12.0 -8.5 -6.0 -4.1 -2.5 -1.2 Table 12-3 Tone levels are specified in linear values, referenced to ½ of the max PCM level (+3.17 dBm0). Tone level = -2.85 dBm0 + 20 log10 (TONEVOL / 32). Because there are 32 legal values, the following table contains only example values. Tone Generator Gain Value TONEVOLx(4:0) Actual level (dBm0) TONEVOLx(4:0) Actual level (dBm0) TONEVOLx(4:0) Actual level (dBm0) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A Disable -32.9530 -26.9324 -23.4106 -20.9118 -18.9736 -17.3900 -16.0510 -14.8912 -13.8681 -12.9530 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 -12.1251 -11.3694 -10.6741 -10.0304 -9.4312 -8.8706 -8.3440 -7.8475 -7.3779 -6.9324 -6.5086 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F -6.1045 -5.7184 -5.3488 -4.9942 -4.6535 -4.3257 -4.0098 -3.7050 -3.4106 -3.1258 - 87 - Publication Release Date: May, 2007 Revision 1.3 W681307 Table 12-4 The side tone gain is adjustable from -32 dB to 0 dB in 1 dB steps. Setting this register to 0 disables side tone. Side Tone Gain value Index 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Value Mute 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB -7 dB -8 dB -9 dB -10 dB -11 dB -12 dB -13 dB -14 dB Index 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Value -15 dB -16 dB -17 dB -18 dB -19 dB -20 dB -21 dB -22 dB -23 dB -24 dB -25 dB -26 dB -28 dB -30 dB -32 dB -36 dB - 88 - Publication Release Date: May, 2007 Revision 1.3 W681307 13. 13.1 ECHO CANCELLER Half AEC Block Diagram The acoustics echo cancellation unit removes the echo signal inserted by the speaker and space. Figure 13-1 illustrates the block diagram of the Half Acoustics Echo Canceller in the Speech Processor. Figure 13-1 The signal flow through the Acoustics Echo Canceller in the Speech Processor 13.1.1 Acoustics Suppression When enabled (and so, switched into the network output data path) the acoustic suppression unit will insert a configurable attenuation factor into the network output path. The attenuation will switch between a maximum and minimum value depending on the presence or absence of speech on the network output data path. When speech is present the attenuation will converge towards the minimum value. When speech is absent the attenuation will converge towards the maximum value. The attenuation factor will not switch abruptly between these two factors but will exponentially converge from one to the other. When enabled the network output data path will include the following arithmetic unit Nout ∝ Nout ∗ AS _ ATTENUATIO N - 89 - ： Publication Release Date: May, 2007 Revision 1.3 W681307 13.1.2 Network Power Estimation To detect the double talk condition an estimate of the long term network power is required. The long term network power is estimated with the following arithmetic unit  Nin n ∗ 2VD _ LONG _ NETWORK _ ATTACK _ TC −16  Pninn ∝ Pninn−1 +  − Pninn −1 ∗ 2VD _ LONG _ NETWORK _ ATTACK _ TC −16   + Vd _ Long _ Network _ Threshold ∗ 2VD _ LONG _ NETWORK _ ATTACK _ TC −17  ( ( ( The short term network power is estimated with the following arithmetic unit  Nin n ∗ 2VD _ SHORT _ NETWORK _ ATTACK _ TC −16 PninShort n ∝ PninShort n −1 +   − PninShort ∗ 2VD _ SHORT _ NETWORK _ ATTACK _ TC −16 n −1  ( ( The deviation term network power is estimated with the following arithmetic unit PninDevn ∝ Pninn − Cut _ Off _ Network _ Power − PninShortn 13.1.3 Acoustic Power Estimation This speech will have originated at the near end and does not correspond to a reflected echo signal. Speech is deemed to occur if the long term acoustic power exceeds a predetermined threshold or if the short term acoustic power exhibits sudden variations. If speech is being carried over both the network and acoustic interfaces then the double talk condition occurs. The long term acoustic power is estimated with the following arithmetic unit  Ain n ∗ 2 DT _ LONG _ ACOUSTIC _ ATTACK _ TC −16 Pain n ∝ Pain n −1 +   − Pain ∗ 2 DT _ LONG _ ACOUSTIC _ ATTACK _ TC −16 n −1  ( ( The short term acoustic power is estimated with the following arithmetic unit  Ain n ∗ 2 DT _ SHORT _ ACOUSTIC _ ATTACK _ TC −16 PainShort n ∝ PainShort n −1 +   − PainShort ∗ 2 DT _ SHORT _ ACOUSTIC _ ATTACK _ TC −16 n −1  ( ( - 90 - ： ： ： ： ： ) ) )       ) )     ) )     ) )     Publication Release Date: May, 2007 Revision 1.3 W681307 13.1.4 Auto Gain Control The short term cancelled power is estimated with the following arithmetic unit PgShort n ∝ PgShort n −1  ( Hsout ∗ 2 AGC _ ST _ ATTACK _ TC −16 )   +  − (PgShort ∗ 2 AGC _ ST _ ATTACK _ TC −16 ) n −1   The AGC module is operated with the following algorithm If ( Hsout > PgShort) then PgShort = Hsout If PgShort < AGC _ NOISE _ THRESHOLD then Sg = 1 Else Sg = AGC _ THRESHOLD PgShort If Sg > AGC _ MAX _ SG then Sg = AGC _ MAX _ SG The long term AGC module gain is estimated with the following arithmetic unit Sglong n ∝ Sglong n −1 If Sglong > Sg then Sglong = Sg  (Sg ∗ 2 AGC _ LG _ ATTACK _ TC −16 )   + AGC _ LG _ ATTACK _ TC −16   − (Sglong ∗ 2 ) n −1  13.2 The Software Interface of Speech Processor The following registers are used to configure the echo canceller. All registers may be both read and written by software. The width of each location will be a byte within the memory map. Some locations may have unused bits which will be returned undefined values on a read cycle. Information in these bit positions will be discarded on write cycles. The registers within the echo cancellation unit may be segmented into two classes Activation Registers and Performance Adjustment Registers. An overview of each register class and nominal values to program each register is presented. 13.3 13.3.1 Activation Registers UP_CONFIG Access Mode R/W Bit 6 RESERVED Bit 5 Address 0x14C0 Bit 7 AGC Value At Reset 0x00 Bit 4 Nominal Value 0x82 Bit 3 Bit 2 Bit 1 AS1_ENA Bit 0 Blocked (for test modes) Blocked Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) (for test modes) - 91 - ： ： ： ： Publication Release Date: May, 2007 Revision 1.3 W681307 AS1_ENA When set, the acoustic suppression (AS1) function will be enabled. AGC When set, enable AGC function. * The acoustic suppression (AS2) function is always enabled. 13.3.2 Address 0x14C1 Bit 7 Blocked (for test modes) UP_RESET Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x08 Bit 4 AEC_Reset Nominal Value 0x00 Bit 3 Power Down Bit 2 Bit 1 Bit 0 Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) Power Down AEC_Reset When set, When set, Power down the AEC unit to save power. Speech signal will bypass AEC module. Setting this bit will cause the AEC registers, including the activation registers and performance adjustment registers, to be reseted to their hardware reset values. 13.3.3 Address 0x14C2 Bit 7 NS_Enable EC_BELTA Access Mode R/W Bit 6 NetAcIdle Bit 5 * Blocked (for test modes) Value At Reset 0x03 Bit 4 Absolute Nominal Value 0xE0 Bit 3 Bit 2 Bit 1 Bit 0 Blocked (for test modes) Absolute When set, the double talk detection algorithm is based on absolute value of Acoustic power. NetAcIdle When set, the double sides don’t have any voice; it will mute in Network side. NS_Enable If this bit is set "0", noise suppressor is by-passed. If this bit is set "1", then noise suppressor is enabled. * Blocked (for test modes) must be set to 1. 13.3.4 Address 0x14C3 Bit 7 RESERVED Specific Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x03 Bit 4 RESERVED Nominal Value 0x03 Bit 3 Bit 2 Bit 1 Bit 0 Blocked (for test modes) 13.4 13.4.1 13.4.1.1 Performance Adjustment Registers Acoustic Suppressor Register AS_BUILD_UP_TIME Access Mode R/W Value At Reset 0x07 Nominal Value 0x55 Address 0x14C4 - 92 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AS2_BUILD_UP_TIME AS1_BUILD_UP_TIME Control register for acoustic suppression factor convergence towards target. Raising (lowering) the value of this field will lower (raise) the inertial delay present when the acoustic suppression unit responds to the presence or absence of speech. 13.4.1.2 Address 0x14C5 - 0x14C6 Bit 15 AS_MAX_ATTEN Access Mode R/W Bit 13 Value At Reset 0x1CA8 Bit 12 Nominal Value 0x0200 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 C5 AS1 & AS2_MAX_ATTEN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C6 AS1 & AS2_MAX_ATTEN Maximum attenuation value will be utilized by the acoustic suppression algorithm. The maximum value of this field provides an attenuation factor of 1. The minimum value provides an attenuation factor of 0. 13.4.1.3 Address 0x14C7 - 0x14C8 Bit 15 AS_MIN_ATTEN Access Mode R/W Bit 13 Value At Reset 0xFFFF Bit 12 Nominal Value 0xFFFF Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 C7 AS1 & AS2_MIN_ATTEN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C8 AS1 & AS2_MIN_ATTEN Minimum attenuation value will be utilized by the acoustic suppression algorithm. The maximum value of this field provides an attenuation factor of 1. The minimum value provides an attenuation factor of 0. 13.4.2 13.4.2.1 Address 0x14C9 Acoustic Side Control Registers DT_LONG_ACOUSTIC_ATTACK_TC Access Mode R/W Value At Reset 0x09 Nominal Value 0x09 - 93 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 Bit 2 Bit 1 Bit 0 DT_LONG_ACOUSTIC_ATTACK_TC Acoustic long term power estimation’s attacking time constant. This field defines the inertial delay utilized for the long term acoustic power estimation. Raising the value of this field reduces the inertia and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the acoustic. 13.4.2.2 Address 0x14CA Bit 7 RESERVED DT_SHORT_ACOUSTIC_ATTACK_TC Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x0B Bit 4 RESERVED Nominal Value 0x0B Bit 3 Bit 2 Bit 1 Bit 0 DT_SHORT_ACOUSTIC_ATTACK_TC Acoustic short term power estimation’s attacking time constant This field defines the inertial delay utilized for the short term acoustic power estimation. Raising the value of this field reduces the inertia and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the acoustic side. 13.4.2.3 Address 0x14CB - 0x14CC Bit 15 DT_ACOUSTIC_HANGOVER_TIME Access Mode R/W Bit 13 Value At Reset 0x0020 Bit 12 Nominal Value 0x0340 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 CB DT_ACOUSTIC_HANGOVER_TIME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CC DT_ACOUSTIC_HANGOVER_TIME This field defines the inertial delay of the double talk detection algorithm for acoustic side. Following the detection of the double talk condition there is a programmable inertial delay (in PCM sample periods 125us) following the disappearance of the double talk condition. For the duration of this delay period the double talk condition is assumed to remain. If double talk does not reappear during this window then the echo cancellation unit will revert back to acoustic training mode. 13.4.2.4 Address 0x14CD - 0x14CE Bit 15 DT_ ACOUSTIC _DEV_THRESHOLD Access Mode R/W Bit 13 Value At Reset 0x0666 Bit 12 Nominal Value 0x0040 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 CD DT_ ACOUSTIC_DEV_THRESHOLD - 94 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CE DT_ ACOUSTIC_DEV_THRESHOLD This field defines the instantaneous acoustic power change that is deemed to correspond to speech and is used to detect short term changes in voice level on the acoustic interface.Raising (lowering) this field will raise (lower) the change in acoustic power required for the detection of speech (and hence the double talk condition). 13.4.2.5 Address 0x14CF - 0x14D0 Bit 15 DT_SHORT_ACOUSTIC_THRESHOLD Access Mode R/W Bit 13 Value At Reset 0x0404 Bit 12 Nominal Value 0x0040 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 CF DT_SHORT_ ACOUSTIC_THRESHOLD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D0 DT_SHORT_ ACOUSTIC_THRESHOLD This field defines the power threshold that is deemed to correspond to speech. Raising(lowering) this field will raise (lower) the acoustic power required for the detection of speech (and hence the double talk condition). 13.4.3 13.4.3.1 Address 0x14D1 Bit 7 RESERVED Network Side Control Registers VD_LONG_NETWORK_ATTACK_TC Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x09 Bit 4 RESERVED Nominal Value 0x09 Bit 3 Bit 2 Bit 1 Bit 0 VD_LONG_NETWORK_ATTACK_TC Network long term power estimation’s attacking time constant This field defines the inertial delay utilized for the long term network power estimation. Raising the value of this field reduces the inertia and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the network side. 13.4.3.2 Address 0x14D2 Bit 7 RESERVED VD_SHORT_NETWORK_ATTACK_TC Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x0B Bit 4 RESERVED Nominal Value 0x0B Bit 3 Bit 2 Bit 1 Bit 0 VD_SHORT_NETWORK_ATTACK_TC - 95 - Publication Release Date: May, 2007 Revision 1.3 W681307 Network short term power estimation’s attacking time constant This field defines the inertial delay utilized for the short term network power estimation. Raising the value of this field reduces the inertia and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the network side. 13.4.3.3 Address 0x14D3 - 0x14D4 Bit 15 VD_NETWORK_HANGOVER_TIME Access Mode R/W Bit 13 Value At Reset 0x0009 Bit 12 Nominal Value 0x0340 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 D3 VD_NETWORK_HANGOVER_TIME Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D4 VD_NETWORK_HANGOVER_TIME This field defines the inertial delay of the voice detection algorithm for the network side. Following the detection of the speech on the network interface there is a programmable inertial delay (in PCM sample periods) following the disappearance of the speech signal. For the duration of this delay period the speech is assumed to remain. If speech does not reappear during this window then the echo cancellation unit will revert back to channel training mode. 13.4.3.4 Address 0x14D5 - 0x14D6 Bit 15 VD_NETWORK_DEV_THRESHOLD Access Mode R/W Bit 13 Value At Reset 0x0666 Bit 12 Nominal Value 0x01B0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 D5 VD_NETWORK_DEV_THRESHOLD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D6 VD_NETWORK_DEV_THRESHOLD This field defines the instantaneous network power change that is deemed to correspond to speech and is used to detect short term changes in voice level on the network interface. Raising (lowering) this field will raise (lower) the change in network power required for the detection of speech. - 96 - Publication Release Date: May, 2007 Revision 1.3 W681307 13.4.3.5 Address 0x14D7 - 0x14D8 Bit 15 VD_LONG_NETWROK_THRESHOLD Access Mode R/W Bit 13 Value At Reset 0x0666 Bit 12 Nominal Value 0x1050 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 D7 VD_LONG_NETWORK_THRESHOLD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D8 VD_LONG_NETWORK_THRESHOLD Minimum power level constitutes speech over the network interface, as measured by the long term power estimation algorithm. 13.4.3.6 Address 0x14D9 - 0x14DA Bit 15 VD_SHORT_NETWROK_THRESHOLD Access Mode R/W Bit 13 Value At Reset 0x040E Bit 12 Nominal Value 0x03C0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 D9 VD_SHORT_NETWORK_THRESHOLD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DA VD_SHORT_NETWORK_THRESHOLD Minimum power level constitutes speech over the network interface, as measured by the short term power estimation algorithm. 13.4.3.7 Address 0x14DB - 0x14DC Bit 15 VD_CUT_OFF_NETWORK_POWER Access Mode R/W Bit 13 Value At Reset 0x0666 Bit 12 Nominal Value 0x08A0 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 DB VD_CUT_OFF_NETWORK_POWER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DC VD_CUT_OFF_NETWORK_POWER Configurable bias for network power estimation. This field defines the zero reference for the network power estimation algorithm. 13.4.3.8 Address 0x14DD Specific Register Access Mode R/W Value At Reset 0x00 Nominal Value - 97 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Blocked (for test modes) 13.4.4 Address 0x14DE Bit 7 RESERVED AcousticActive NetworkActive ACOUSTIC / NETWORK Active Status Access Mode R Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Blocked Blocked Blocked Blocked AcousticActive NetworkActive (for test modes) (for test modes) (for test modes) (for test modes) = 1, reflect the status of acoustic power = 1, reflect the status of network power. 13.4.5 13.4.5.1 Address AGC Control Registers AGC_THRESHOLD Access Mode R/W Bit 13 Value At Reset 0x0800 Bit 12 Nominal Value 0x1000 Bit 11 Bit 10 Bit 9 Bit 8 0x14DF - 0x14E0 Bit 15 Bit 14 DF AGC_THRESHOLD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E0 AGC_THRESHOLD The AGC threshold is set the maximum output power from AGC module. The purpose is set properly gain to prevent voice signal clipping. 13.4.5.2 Address 0x14E1 - 0x14E2 Bit 15 AGC_NOISE_THRESHOLD Access Mode R/W Bit 13 Value At Reset 0x00C8 Bit 12 Nominal Value 0x0100 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 E1 AGC_NOISE_THRESHOLD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 E2 AGC_NOISE_THRESHOLD The calculated input power with time constant AGC_ST_ATTACK_TC is less than the AGC_NOISE_THRESHOLD, then AGC gain is set to unit gain. It is assumed that the input power is background signal. - 98 - Publication Release Date: May, 2007 Revision 1.3 W681307 13.4.5.3 Address 0x14E3 Bit 7 Reserved AGC_MAX_SG Access Mode R/W Bit 6 Reserved Bit 5 Reserved Value At Reset 0x02 Bit 4 Reserved Nominal Value 0x0A Bit 3 Bit 2 Bit 1 Bit 0 AGC_MAX_SG The AGC module has maximum gain to amplifier the echo cancelled input signal. 13.4.5.4 Address 0x14E4 Bit 7 Reserved Specific Register Access Mode R/W Bit 6 Reserved Bit 5 Reserved Value At Reset 0x0F Bit 4 Reserved Nominal Value 0x00 Bit 3 Bit 2 Bit 1 Bit 0 *Blocked for test modes *Blocked for test modes. Set the 4 bits to 1. 13.4.5.5 Address 0x14E5 Bit 7 AGC_LG_ATTACK_TC Access Mode R/W Bit 6 Bit 5 Value At Reset 0x0B Bit 4 Nominal Value 0x33 Bit 3 Bit 2 Bit 1 Bit 0 AGC_LG_ATTACK_TC_POS AGC_LG_ATTACK_TC_NEG AGC_LG_ATTACK_TC_NEG AGC_LG_ATTACK_TC_POS The field defines the inertial delay utilized for the long term gain estimation when the AGC gain is increasing. Raising the value of this field reduces the inertial and will make the estimation more responsive while lowering the field will cause the gain estimation algorithm to be less responsive to bursts of gain on the AGC. The field defines the inertial delay utilized for the long term gain estimation when the AGC gain is decreasing. Raising the value of this field reduces the inertial and will make the estimation more responsive while lowering the field will cause the gain estimation algorithm to be less responsive to bursts of gain on the AGC. 13.4.5.6 Address 0x14E6 Bit 7 AGC_ST_ATTACK_TC Access Mode R/W Bit 6 Bit 5 Value At Reset 0x09 Bit 4 Nominal Value 0x09 Bit 3 Bit 2 Bit 1 Bit 0 RESERVED AGC_ST_ATTACK_TC Attack time for short term AGC power estimation. This field defines the inertial delay utilized for the short term AGC power estimation. Raising the value of this field reduces the inertial and will make the estimation more responsive while lowering the field will cause the power estimation algorithm to be less responsive to bursts of energy on the AGC. - 99 - Publication Release Date: May, 2007 Revision 1.3 W681307 13.4.6 13.4.6.1 Address 0x14E7 Bit 7 Noise Suppressor Registers NS_STTACK_Tcand_GAIN Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value 0xB5 Bit 3 Bit 2 Bit 1 Bit 0 ShortTermNSPowerATTACKTC[7:4] Noise_Suppressor_Index[3:0] Noise_Suppressor_Index This 4-bit field defines the gain of Noise suppressor Noise_Suppressor_Index[3:0] 0 1 2 3 4 5 6 7 8 Noise Suppressor Level (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 Noise_Suppressor_Index[3:0] 9 A B C D E F Noise Suppressor Level (dB) -10 -11 -12 -13 -14 -15 -16 ShortTermNSPowerATTACKTC The 4-bit field defines the "Time Constant" to calculate the power of voice that enters the noise suppressor module. So "Noise Suppressor" can determine if current power of voice is larger than "Noise threshold" or not. The operation is just like "Short term acoustic power time constant. 13.4.6.2 Address 0x14E8 Bit 7 NS_ATTEN_DW_UP_TC Access Mode R/W Bit 6 Bit 5 Noise_fall_TC[4:7] Noise_rise_TC This 4-bit field defines the time constant of Noise suppressor gain from the gain specified by "noise_suppressor_index" to "0dB". Larger value, faster speed. This 4-bit field defines the time constant of Noise suppressor gain from "0dB" to the gain specified by "noise_suppressor_index". Larger value, faster speed. Noise_fall_TC 13.4.6.3 Address 0x14E9 Bit 7 NS_Active_Power_MSB Access Mode R/W Bit 6 Bit 5 The most significant byte of noise threshold. ： ： Value At Reset 0x00 Bit 4 Nominal Value 0x55 Bit 3 Bit 2 Bit 1 Bit 0 Noise_rise_TC[0:3] Value At Reset 0x00 Bit 4 Nominal Value 0x00 Bit 3 Bit 2 Bit 1 Bit 0 NS_Active_Power_MSB - 100 - Publication Release Date: May, 2007 Revision 1.3 W681307 13.4.6.4 Address 0x14EA Bit 7 NS_Active_Power_LSB Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value 0x40 Bit 3 Bit 2 Bit 1 Bit 0 NS_Active_Power_LSB The most significant byte of noise threshold. So "noise_threshold" = {NS_Active_Power_MSB,NS_Active_Power_LSB} 13.4.7 AEC Soft Clip In order to reduce clipping distortion, a soft clipping function has been implemented in GTx1. A second gain (GTx1_SC) and an overload threshold point (TH_SC) is programmable. Gain GTx1 is changed to GTx1_SC if the input signal level of the GTx1 gain state is greater than TH_SC. Note that the input signal power level is estimated in the GTx1 gain stage using the following arithmetic unit PGTx1 = PGTx1 × 1 − 2 GTx1_ TC −16 + AGTx1 × 2 GTx1_ TC −16 If ( ( ) PGTx1 ≥ TH_SC) GTx1_ Factor ⇐ GTx1_ SC Else GTx1_ Factor ⇐ GTx1 GTx1avg ⇐ (1 − 2 ( GT _ TC −16) ) × GTx1avg + GTx1_ Factor × 2 ( GT _ TC −16) Arin ⇐ AGTx1 × GTx1avg PGTx1 GTx1 input power with time constant GTx1_TC GTx1avg GTx1 average gain with time constant GT_TC - 101 - Publication Release Date: May, 2007 Revision 1.3 ： ： ： W681307 Output_ Signal MAX_ LEVEL GTx1*TH_SC GTx1_SC GTx1 Input_ Signal TH_SC MAX_ LEVEL Figure 13-2 Block diagram of the soft clipping function of GTx1 13.4.7.1 Address 0x14EB Bit 7 RESERVED Soft Clip Control Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value 0x03 Bit 3 Reserved Bit 2 Reserved Bit 1 DTSC_Enable Bit 0 VDSC_Enable Soft_clip control register is used to enable the soft clipping function. There are two bits in this register to control two soft clip blocks independently. VDSC_Enable When set, enable soft clip function for network signal before network signal is sent to AEC module. When reset, disable soft clip function. So network signal is sent to AEC module directly. When set, enable soft clip function for acoustic signal after acoustic signal is sent out from AEC module. When reset, disable soft clip function. So acoustic signal is sent to next stage directly. DTSC_Enable - 102 - Publication Release Date: May, 2007 Revision 1.3 W681307 13.4.7.2 Address 0x14EC Bit 7 RESERVED VD Soft Clip Normal Index Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value 0x12 Bit 3 Bit 2 Bit 1 Bit 0 VDSC_Normal_Index[5:0] VDSC_Normal_Index[5:0] is used to control the gain of VD Soft_Clip module at normal mode. The gain selection range is the same as "Digital Gain Multiplexer" and is reproduced below VDSC_Normal_Index[5:0] HEX Value 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0 dB (default) 0.5 dB 1.0 dB 1.5 dB 2.0 dB 2.5 dB 3.0 dB 3.5 dB 4.0 dB 4.5 dB 5.0 dB 5.5 dB 6.0 dB 6.5 dB 7.0 dB 7.5 dB 8.0 dB 8.5 dB 9.0 dB 9.5 dB 10.0 dB 10.5 dB 11.0 dB 11.5 dB 12.0 dB ： Gain VDSC_Normal_Index[5:0] HEX Value 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x3F Gain - 0.5 dB - 1.0 dB - 1.5 dB - 2.0 dB - 2.5 dB - 3.0 dB - 3.5 dB - 4.0 dB - 4.5 dB - 5.0 dB - 5.5 dB - 6.0 dB - 6.5 dB - 7.0 dB - 7.5 dB - 8.0 dB - 8.5 dB - 9.0 dB - 9.5 dB - 10.0 dB - 10.5 dB - 11.0 dB - 11.5 dB - 12.0 dB Mute - 103 - Publication Release Date: May, 2007 Revision 1.3 W681307 13.4.7.3 Address 0x14ED Bit 7 RESERVED VD Soft Clip Low Index Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value 0x06 Bit 3 Bit 2 Bit 1 Bit 0 VDSC_Low_Index[5:0] VDSC_Low_Index[5:0] is used to control the gain of vd soft_clip module at low mode. The gain selection range is the same as "VD Soft Clip Normal Index". 13.4.7.4 Address 0x14EE - 0x14EF Bit 15 VD Soft Clip Threshold Access Mode R/W Bit 13 Value At Reset 0x0400 Bit 12 Nominal Value 0x4000 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 EE VDSC_Threshold Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EF VDSC_Threshold VDSC_Threshold is used to determine the selection of Soft Clip gain. When the input network power is larger then VDSC_Threshold, VDSC_Low_Index gain is used, otherwise VDSC_Normal_Index gain is used. 13.4.7.5 Address 0x14F0 Bit 7 RESERVED ShortTermPreNetworkPowerAttackTC Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x07 Bit 4 RESERVED Nominal Value 0x0B Bit 3 Bit 2 Bit 1 Bit 0 ShortTermPreNetworkPowerAttackTC[3:0] ShortTermPreNetworkPowerAttackTC[3:0] is the time constant which is used to calculate the short term network power for VD Soft Clip. 13.4.7.6 Address 0x14F1 Bit 7 RESERVED VDSC Attack TC Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x07 Bit 4 RESERVED Nominal Value 0x05 Bit 3 Bit 2 Bit 1 Bit 0 VDSC_AttackTC[3:0] When soft clip gain is switched between normal and low, an embedded smoothing function is used to smooth the gain change. VDSC_AttackTC[3:0] is a time constant to control the smoothing speed. - 104 - Publication Release Date: May, 2007 Revision 1.3 W681307 13.4.7.7 Address 0x14F2 Bit 7 RESERVED DT Soft Clip Normal Index Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value 0x18 Bit 3 Bit 2 Bit 1 Bit 0 DTSC_Normal_Index[5:0] DTSC_Normal_Index[5:0] is used to control the gain of DT Soft Clip module at normal mode. The gain selection range is the same as "VDSC_Normal_Index". 13.4.7.8 Address 0x14F3 Bit 7 RESERVED DT Soft Clip Low Index Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value 0x0C Bit 3 Bit 2 Bit 1 Bit 0 DTSC_Low_Index[5:0] DTSC_Low_Index[5:0] is used to control the gain of DT Soft_Clip module at low mode. The gain selection range is the same as "VDSC_ Normal_Index". 13.4.7.9 Address 0x14F4 - 0x14F5 Bit 15 DT Soft Clip Threshold Access Mode R/W Bit 13 Value At Reset 0x0400 Bit 12 Nominal Value 0x1140 Bit 11 Bit 10 Bit 9 Bit 8 Bit 14 F4 DTSC_Threshold Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F5 DT_SC_Threshold DTSC_Threshold is used to determine the selection of Soft Clip gain. When the output acoustic power is larger then DTSC_Threshold, DTSC_Low_Index gain is used, otherwise DTSC_Normal_Index gain is used. - 105 - Publication Release Date: May, 2007 Revision 1.3 W681307 13.4.7.10 Address 0x14F6 Bit 7 RESERVED ShortTermPostAcousticPowerAttackTC Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x07 Bit 4 RESERVED Nominal Value 0x0B Bit 3 Bit 2 Bit 1 Bit 0 ShortTermPostAcousticPowerAttackTC[3:0] ShortTermPostAcousticPowerAttackTC[3:0] is the time constant which is used to calculate the short term acoustic power for DT Soft Clip. 13.4.7.11 Address 0x14F7 Bit 7 RESERVED DTSC Attack TC Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x07 Bit 4 RESERVED Nominal Value 0x05 Bit 3 Bit 2 Bit 1 Bit 0 DTSC_AttackTC[3:0] When soft clip gain is switched between normal and low, an embedded smoothing function is used to smooth the gain change. DTSC_AttackTC[3:0] is a time constant to control the smoothing speed. 13.5 13.5.1 Acoustic Side / Network Side Power Measurement ACOUSTIC_SHORT_TERM_POWER Access Mode R Bit 13 Address 0x15C0- 0x15C1 Bit 15 Bit 14 Value At Reset 0x0000 Bit 12 Nominal Value Bit 11 Bit 10 Bit 9 Bit 8 C0 ACOUSTIC_SHORT_TERM_POWER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C1 ACOUSTIC__SHORT_TERM_POWER Short Term Acoustic Power calculated by the double talk detector (DT). 13.5.2 Address ACOUSTIC_LONG_TERM_POWER Access Mode R Bit 13 Value At Reset 0x0000 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Nominal Value 0x15C2- 0x15C3 Bit 15 Bit 14 - 106 - Publication Release Date: May, 2007 Revision 1.3 W681307 C2 ACOUSTIC_LONG_TERM_POWER Bit 7 C3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACOUSTIC_LONG_TERM_POWER Long Term Power on acoustic side estimated by the double talk detector (DT). 13.5.3 Address ACOUSTIC_POWER_DEVIATION Access Mode R Bit 13 Value At Reset 0x0000 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Nominal Value 0x15C4- 0x15C5 Bit 15 C4 Bit 14 ACOUSTIC_POWER_DEVIATION Bit 7 C5 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACOUSTIC_POWER_DEVIATION Acoustic Power Deviation estimated by the double talk detector (DT). 13.5.4 Address 0x15C6 Bit 7 RESERVED ACOUSTIC / NETWORK Active Status Access Mode R Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 Bit 0 AcousticActive NetworkActive Bit[1] Bit[0] = 1, reflect the status of acoustic power. = 1, reflect the status of network power. 13.5.5 Address NETWORK_SHORT_TERM_POWER Access Mode R Bit 13 Value At Reset 0x0000 Bit 12 Nominal Value 0x15C8 - 0x15C9 Bit 15 Bit 14 Bit 11 Bit 10 Bit 9 Bit 8 C8 NETWORK_SHORT_TERM_POWER - 107 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C9 NETWORK_SHORT_TERM_POWER Network Short Term Power calculated by VD modules. 13.5.6 Address NETWORK_LONG_TERM_POWER Access Mode R Bit 13 Value At Reset 0x0000 Bit 12 Nominal Value 0x15CA- 0x15CB Bit 15 Bit 14 Bit 11 Bit 10 Bit 9 Bit 8 CA NETWORK_LONG_TERM_POWER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CB NETWORK_LONG_TERM_POWER Network Long Term Power calculated by VD modules. 13.5.7 Address NETWORK_POWER_DEVIATION Access Mode R Bit 13 Value At Reset 0x0000 Bit 12 Nominal Value 0x15CC- 0x15CD Bit 15 Bit 14 Bit 11 Bit 10 Bit 9 Bit 8 CC NETWORK_POWER_DEVIATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CD NETWORK_POWER_DEVIATION Network Power Deviation estimated by the voice detector (VD). 13.5.8 Address 0x15CE Bit 7 RESERVED ACOUSTIC / NETWORK Active Status Access Mode R Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 Bit 0 AcousticActive NetworkActive Bit[1] Bit[0] = 1, reflect the status of acoustic power. = 1, reflect the status of network power. - 108 - Publication Release Date: May, 2007 Revision 1.3 W681307 14. SYSTEM FUNCTION 14.1 Power On Reset The power on reset (POR) block generates a internal reset signal to reset the whole chip after connecting the power supply voltage the chip. The power on reset circuit responds to the voltage difference applied between AVDD and AGND. Figure 14-1 shows the power reset circuit. When AVDD is rising slowly starting from zero to the signal PowerOnResetN will be low until AVDD passed the power-on voltage level Von. After a delay time (about 37ms for 13.824MHz clock) Reset_out goes high and the actual reset sequence starts. If AVDD does not pass Von voltage, then the PowerOnResetN stays low, causing the oscillator to run and having most of the digital logic circuits being in an active reset mode. If AVDD sinks below the power-off voltage level Voff, PowerOnRestN will become low again. The hysteresis voltage between Von and Voff is need to overcome a “reset oscillation” phenomenon that otherwise might occur if AVDD decrease due to the activity during the reset sequence. Figure 144-1 Analog part of the power on Reset function. 14.1.1 Address 0x1500 Bit 7 RESERVED CODEC On/Off Scheme Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Bit 3 Bit 2 Bit 1 Codec on/off Bit 0 CODECOnOff scheme Enable PeriodSelection CODECOnOff_scheme_Enable Set “1” to enable hardwired CODEC On/Off scheme. Set “0” to use independent On/Off control from 0x1509. Set“1” to turn on CODEC. Set “0” to turn off CODEC. Set to select the duration length between CODEC_digital_on/off and CODEC_analog_on/off. Bit[3:2] 2’b00 2’b01 2’b10 2’b11 Period 2 mS 4 mS 8 mS 16 mS CODEC On/Off PeriodSelection - 109 - Publication Release Date: May, 2007 Revision 1.3 W681307 14.1.2 Address 0x1501 Bit 7 ABF_MODE CODEC Digital Part Access Mode R/W Bit 6 Bit 5 Value At Reset 0x80 Bit 4 DAC_Dither _Enable Nominal Value 90 Bit 3 Bit 2 Bit 1 Bit 0 DAC_Dither_Level[1:0] ADC_ABF_Length[1:0] CODEC_FIFO_ CODEC_FIFO_ PTR_Reset Reset CODEC_FIFO_Reset CODEC_FIFO_PTR_Reset ADC_ABF_Length[1:0] When set, Clear CODEC FIFO content after each 8K operation. When set, Reset CODEC FIFO pointer after each 8K operation. Select the limit cycle length to do adaptive bit flipping (ABF) algorithm. ABF_L[1:0] Limit cycle Length 0 4 1 6 2 8 3 10 When set, enable the dither input in DAC path Select the dither level in the DAC path. DA_Dither_Level[1:0] Dither Level 0 17 bit 1 15 bit 2 16 bit 3 18 bit When set, select adaptive bit flipping algorithm (ABF) mode in the analog CODEC modulator. DAC_Dither_Enable DAC_Dither_Level[1:0] ABF_MODE 14.2 ADC Adaptive Bit Flip Probability Address 0x1502 Access Mode R/W Bit 6 Bit 5 Value At Reset 0xFF Bit 4 Nominal Value 80 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 ADC_ABF_PROB This byte set the adaptive bit flip probability of the ADC path in the CODEC modulator. When set ADC_ABF_PROB to 0xFF will disable the adaptive bit-flipping algorithm, and set to 0x00 means always enable the adaptive bit-flipping algorithm if the limit cycle length condition is detected. - 110 - Publication Release Date: May, 2007 Revision 1.3 W681307 14.3 Sounder Signal Selection Address 0x1503 Bit 7 Bit 6 RESERVED Access Mode R/W Bit 5 Value At Reset 0x00 Bit 4 RefClkSel Nominal Value Bit 3 Bit 2 RefClkOn Bit 1 PDMEN Bit 0 SNDRSigSel Blocked (for test modes) Rclk_SNDR_SE L There are two sounders signal to be selected to connect to SNDR pin. This subsection describes the sounder signal of PDM (Pulse Density Modulation) format. The selection of different sounder signal and the related control bits are shown in 0x1503[1:0]. PDMEN When set, the TX path of CODEC will be hardware muted, the over sampled DTMF signal is switched to sounder signal path. So except to generate sounder signal, this bit should be reset to 0 while CODEC is active. When set, the sounder signal comes from the DTMF generator in the speech processor. The DTMF signal will be over sampled to 1 bit signal, which is called Pulse Density Modulation (PDM) format. The PDM format signal then connects to pin SNDR while PDMRingEN=1. The control registers of DTMF generator are allocated from addresses 1488H~148CH =0, the sounder signal comes from the Ringer Tone Generator with Pulse Width Modulation (PWM) format. The control registers of Ringer Tone Generator are allocated from addresses 1447H~144AH When set, enable Reference Clock Generation circuit. Reference clock rate selection. RefClkSel[4:3] 0 1 2 3 SNDRSigSel RefClkOn RefClkSel Reference Clk Rate 13.824 MHz 6.912 MHz 3.456 MHz 1.728 MHz Rclk_SNDR_Sel Switch the function of pin SNDR. Set “1” to configure the SNDR pin as RefClock output. Set ”0” to configure the SNDR pin as SNDR output. - 111 - Publication Release Date: May, 2007 Revision 1.3 W681307 CODECAPd 0x1509[6] ADown CODEC Analog SWC_in CODEC Digital 0 1 DAout Half AEC 0x14C1 0x1485 PCM Format Tone Geneator 0x1488-0x148C Linear PCM 0x1486 PDMEN 0x1503[1] PDM 0x1484 PWM SNDRSigSel 0x 1503[0] 1 0 SNDR Ringer Tone Generation (dd209_rt) Figure 14-2 Sounder signal selection circuit SNDR_in negedge clk control logic control RefClkSel[1:0] RefClkOn On system clock Rclk_SNDR_Sel cnt 00 01 10 11 0 1 Muxed_SNDR 0 1 counter to 7 2 Figure 14-3 Reference clock frequency rate and function selection circuit. 14.4 Frequency Adjustment of Crystal Oscillator A 13.824 MHz crystal is connected to pin XTAL1 and XTAL2. But the accuracy of the system clock will affect the performance and power saving capability of a handset operating in suspend mode. The frequency deviation resulted from the variation of crystal device and external load capacitances can be adjusted by the on-chip capacitances. FACO (Frequency Adjustment of Crystal Oscillator) controls the connection of on-chip capacitance Cg and Cd to the crystal oscillator pins XTAL1 and XTAL2 respectively. The total maximum value is 11.9pF per pin. Therefore this register can control the frequency of the crystal oscillator at 13.824 MHz. accurately. FACO Address 0x1504 Access Mode R/W Value At Reset 0x00 Nominal Value - 112 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 Bit 6 Bit 5 Bit 4 FACO Bit 3 Bit 2 Bit 1 Bit 0 FACO[Bit 7] FACO[Bit 6] FACO[Bit 5] FACO[Bit 4] FACO[Bit 3] FACO[Bit 2] FACO[Bit 1] FACO[Bit 0] When set, add an 8 pF to Cg and Cd each. When set, add an 4 pF to Cg and Cd each. When set, add an 2 pF to Cg and Cd each. When set, add an 1 pF to Cg and Cd each. When set, add an 0.5 pF to Cg and Cd each. When set, add an 0.25 pF to Cg and Cd each. When set, add an 0.125 pF to Cg and Cd each. When set, add an 0.0625 pF to Cg and Cd each. 14.5 Specific Register Address 0x1505 Bit 7 Bit 6 RESERVED Access Mode R/W Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 RESERVED Blocked Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) (for test modes) 14.6 VAG Selection Address 0x1506 Bit 7 Bit 6 Vc_vag [2:0] Access Mode R/W Bit 5 Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 RESERVED VAG default voltage is 1.5V. And the VAG level can be programmed by software with following table. Vc_vag [2:0] VAG (V) 0 1 2 3 4 5 6 7 1.50 1.57 1.67 1.80 2.00 2.33 1.50 1.50 Bin Hex Default 000 001 010 011 100 101 110 111 - 113 - Publication Release Date: May, 2007 Revision 1.3 W681307 14.7 TG Gain Register Address 0x1507 Bit 7 Bit 6 TG_A Gain[2] Access Mode R/W Bit 5 TG_A Gain[1] Value At Reset 0x00 Bit 4 TG_A Gain[0] Nominal Value Bit 3 Reserved Bit 2 TG_B Gain[2] Bit 1 TG_B Gain[1] Bit 0 TG_B Gain[0] Reserved TG Op amp of the Codec is implemented as a two amplifiers cascade to provide the necessary gain for low signal microphone input. The first stage (TG_A) is designed as a full differential high impendence and low noise amplifier. This amplifier gain can be set as bypass or maximum gain 18dB for microphone input. The second stage (TG_B) is also full differential amplifier and provides maximum gain 24dB for the application requirement. It is according this register to set different gain in the Codec, equivalent architecture is shown in Figure 14-4. The TG amplifier gain table is listed as below TG_A Gain[2:0] Bin Hex 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 Gain [dB] 0 dB 6 dB 12 dB 18 dB Bypass Bypass Bypass Bypass 1st TG 2nd TG Figure 14-4 Equivalent schematics for TG Op amp. - 114 - Publication Release Date: May, 2007 Revision 1.3 +GT -GT K042 ,K021 ,K06 , K03, K51 K042 ,K021 ,K06 , K03, K51 ]6[7051x0 , ]0[1251x0 K51 K51 K51 K51 K51 K51 -2IT +1IT -1IT +2IT K021 ,K06 , K03, K51 K021 ,K06 , K03, K51 ： TG_B Gain[2:0] Bin Hex 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 Gain [dB] 0 dB 6 dB 12 dB 18 dB 24 dB 24 dB 24 dB 24 dB XUM ]0[1251x0 1 0 1 0 K51 K51 K51 K51 +1IT +2IT -1IT -2IT W681307 14.8 PO Gain Register Address 0x1508 Bit 7 Bit 6 PO2Gain [2] Access Mode R/W Bit 5 PO2Gain [1] Value At Reset 0x88 Bit 4 PO2Gain [0] Nominal Value Bit 3 PO1_PD Bit 2 PO1Gain [2] Bit 1 PO1Gain [1] Bit 0 PO1Gain [0] PO2_PD The gains of PO1 and PO2 op amp are set according to this register value. The maximum driving capability of PO1 is 120Ω and PO2 is 16Ω. The PO1 and PO2 can be power down by the corresponding control bits of PO Gain register. Note that the PO op amps can be also power down by the CODEC_CTRL register (0x1509). The PO amplifier gain table is listed as below. PO1 Gain [3:0] Bin Hex 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1xxx Gain [dB] 0 dB 2 dB 4 dB 6 dB 8 dB 10 dB -2 dB -4 dB Disable PO2 Gain [7:4] Bin Hex 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1xxx Gain [dB] 0 dB 2 dB 4 dB 6 dB 8 dB 10 dB -2 dB -4 dB Disable - 115 - Publication Release Date: May, 2007 Revision 1.3 W681307 The equivalent resistance is shown in Figure 14-5. PO1_PD 0x1508 B[3] 15K P O1+ PO 1 PO 1- Unit Gain RO 15K 15K 15K Figure 14-5 Equivalent schematics for PO op amp - 116 - r PO2_PD 0x1508 B[7] PO2+ PO 2 PO2- r Publication Release Date: May, 2007 Revision 1.3 W681307 14.9 14.9.1 The PCM CODEC Block Diagram Figure 14-6 shows the block diagram of the speech CODEC-filter. Figure 14-6 The block diagram of the PCM CODEC-Filter 14.9.2 Analog Interface and Signal Path The built in linear 14-bit PCM CODEC-filter uses Σ∆ technology. There are two paths in the block, a transmit path and a receive path. 14.9.2.1 Transmit Path in Σ∆ CODEC-Filter An analog signal input, from a microphone interface, is passed to three terminal operational amplifiers (TI+, TI-, TG) driving a typical 2 KΩ load externally to amplify the input analog signal. The modulator block over samples the analog signal at 1.536 MHz with one bit resolution. The next anti-aliasing decimation filter reduces the sampling frequency from 1.536 MHz (1 bit) to 32 KHz (15 bit). Digital biquad filters perform the decimation from 32K to 8 KHz and CCITT low-pass filtering at 3400 Hz. The digital HPF block performs the high-pass filtering at 300 Hz. In the final step, the 14 bit A/D conversed data is sent by the transmit path to the DSP engine for further signal processing. 14.9.2.2 Receive Path in Σ∆ CODEC-Filter A 14-bit linear digital signal from the DSP engine is first passed to the digital anti-aliasing interpolation filter block. The interpolation block performs the reverse operation of the decimation filter (described above in the transmit path) and the sampling rate will be increased from 8 KHz (14 bits) to 1.536 MHz (14 bits). The digital demodulator will then reduce the 14-bit samples (1.024 MHz) to 1 bit (1.536 MHz). The digital output signal will be passed to a 3400 Hz switched capacitor low-pass filter with sin(x)/x correction and an analog smoothing filter to reduce the spectral components of the switched capacitor filter. Finally, the analog output signal is sent to the unit gain power amplifier RO, which is capable of driving a 2 KΩ load connected to the VAG pin. The last stage of the received path is a pair of power driver PO1- (PO2-) and PO1+ (PO2+) which is connected in a push-pull (differential) configuration. The PO driver can accommodate large gain ranges by adjusting two external resistors for applications such as driving a handset receiver (or a speaker). This differential circuit is capable of driving a 120 Ω (16Ω) load. Publication Release Date: May, 2007 Revision 1.3 - 117 - W681307 14.9.3 Control Register: CODEC_CTRL The functional description and read/write status of each bit are illustrated in this section. The read or write status of each bit is indicated by the symbol R or W described in Table 14-1. SYMBOL R/W TYPE Read/Write MEANING Data may be read or written by micro-processor. Table 14-1: Read/Write status description in control register Address 0x1509 Bit 7 CODEC DigDis Bit 6 Access Mode R/W Bit 5 Reserved =1, =0, Value At Reset 0xC0 Bit 4 Reserved Nominal Value Bit 3 Analog Loopback Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved CODECAPd CODECDigDis [Bit7]: Disable the CODEC digital part, Enable the CODEC digital part. To disabled the CODEC analog part to save power. Especially when using the PDM mode sounder signal, only the CODEC digital filter is necessary. CODEC analog part enabled. Setting this bit causes an analog loopback from the receive path to the transmit path. Internally the RO output in the receive path is routed to the transmit gain control in the transmit path; the op-amp TG is bypassed. This feature is useful for self-testing to neglect the external connecting circuit, shown in Figure 14-7. . CODECAPd [Bit6]: =1, =0, Analog Loopback [Bit 3]: =1, Figure 14-7 The signal flow of Analog Lookback - 118 - Publication Release Date: May, 2007 Revision 1.3 W681307 14.9.4 Address 0x150A Bit 7 Specific Register Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Blocked (for test modes) 14.9.5 Address 0x150B Bit 7 Blocked (for test modes) Specific Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Blocked Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) (for test modes) 14.10 RECEIVE_DIAG Address 0x150C Access Mode R/W Bit 6 P3.5_A1 _Sel Bit 5 P3.4_A0 _Sel Value At Reset 0x00 Bit 4 CS3_Enable Nominal Value Bit 7 Bit 3 P1.4_WaitState_Sel Bit 2 P1.5_Sel Bit 1 P1.6_Sel[1] Bit 0 P1.6_Sel[0] Reserved B[1:0] P1.6_Sel[1:0]= 0, 1, 2, 3, Pin 44= P1.6 Pin 44= X Pin 44= X Pin 44= P1.6 Pin 45= P1.5 or /CS3 Pin 45= X Pin 46= P1.4 Pin 46= wait state input Pin 45= P1.5 Pin 45= /CS3 Pin37= P3.4 Pin37= A0 Pin36= P3.5 Port 1 Bit 6 of embedded T8032. Undefined. signal. Undefined. signal. Port 1 Bit 6 of embedded T8032. Port 1 Bit 5 of embedded T8032 or External chip select. Undefined. signal Port 1 Bit 4 of embedded T8032. The input pin with pull-high can receive wait signal from external device. Port 1 Bit 5 of embedded T8032. External chip select. Port 3 Bit 4 of embedded T8032. A0 address of embedded T8032. Port 3 Bit 5 of embedded T8032. B[2] P1.5_Sel= 0 1 B[3] P1.4_waitstate_sel= 0, 1, B[4] CS3_Enable= 0 1 B[5] P3.4_A0_Sel= 0, 1, B[6] P3.5_A1_Sel= 0, 1, Pin36= A1 A1 address of embedded T8032. If KR is used as GPIO function besides setting SPI_Enable 0x1720 [7] = 0 (disable SPI), 0x150C [7] must be set “0”. ※ - 119 - Publication Release Date: May, 2007 Revision 1.3 W681307 The usages of pin44 and pin45 are illustrated in Figure 14-8. CS3_Enable [B4] ( 0x150C [B4] ) /CS3 1 P1.5_ Sel [B2] ( 0x150C [B2] ) SPI_ ENB X 1 0 0 MOSI ( SPI Master Output ; Slave Input) SDI (DF_SPI) P1.5/ MOSI / SDI / /CS3 1 P1.5 0 P1.6_ Sel [1:0] ( 0x150C [1:0] ) P1.6 3 2 1 0 MISO ( SPI Master Input ; Slave Output ) SPI_ ENB DF_ ENB 0 0 1 SDO (DF_SPI) 1 P1.6/MISO / SDO X X P1.6 Figure 14-8 The Multiplexers of pin44 and pin45 The usages of pin36 and pin37 are illustrated in Figure 14-9. P3.4_A0_Sel 150C[5] P3.4 A0 0 1 UART_EN & SIM_EN 1554[7-6] 00 01 10 11 X UART_RXD1 SIM_CLK P3.4/ A0/ RXD1/SIM_CLK P3.5_A1_Sel 150C[6] P3.5 A1 0 UART_EN 1554[7] 0 1 P3.5/ A1/ TXD1 UART_TXD1 1 Figure 14-9 The Multiplexers of pin36 and pin37 - 120 - Publication Release Date: May, 2007 Revision 1.3 W681307 14.11 Specific Register Address 0x150D Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x19 Bit 4 Nominal Value Bit 7 RESERVED Bit 3 Bit 2 Bit 1 Bit 0 Blocked Blocked Blocked Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) 14.12 EnAllClock Address 0x150E Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 7 SpeedUp32K Bit 3 Dump mask Rom Bit 2 8032 clk output selection Bit 1 Read MASK ROM Enable Bit 0 EnAllClock EnAllClock Read Mask ROM Enable 8032 clk output selection Dump mask Rom SpeedUp32K when set, most of the clocks will be enabled. when set, enable read_access for MASK ROM when set, P1.4 will output system clock used by on chip TB8032. If chip is configured as double system clock speed, it output the x2 system clock. when set, enable MASK ROM test mode. when set, 32k clock will replace with 13.824 system clock for speed up testing. 14.13 CODEC_Test_Sel Address 0x150F Access Mode R/W Bit 6 codec_test _sel[6] Bit 5 codec_test _sel[5] Value At Reset 0x00 Bit 4 codec_test _sel[4] Nominal Value Bit 7 codec_test _sel[7] Bit 3 codec_test _sel[3] Bit 2 codec_test _sel[2] Bit 1 codec_test _sel[1] Bit 0 codec_test _sel[0] Codec_test-sel[3:0] =0001, loopback DA output. =0010, loopback AD output. =0011, assign DA output to “0”. =0100, loopback DA input. =0101, test ALU function. =0110, set value to internal register D2. =0111, calculate checksum of code ROM. =1000, calculate checksum of coefficient ROM. =1001, route external input (pDR) to AD input. =1010, output code ROM content. =1011, output coefficient ROM content. =0001, 1-bit AD input. =0010, ADC FIFO pointer. =0011, ADC 1st -stage SINC filter output. =0100, ADC 2nd –stage SINC filter output. =0101, ADC LPF output. =0110, ADC HPF output. =0111, ADC output. =1000, DAC input. =1001, DAC 1st –stage SINC filter output. =1010, DAC LPF output Codec_test-sel[7:4] - 121 - Publication Release Date: May, 2007 Revision 1.3 W681307 =1011, DAC 2nd –stage SINC filter output. =1100, 1-bit DA output. =1101, DAC FIFO pointer. 14.14 Test_SYSCLKOUT Address 0x1510 Access Mode R/W Bit 6 Reserved Bit 5 Reserved Value At Reset 0x00 Bit 4 Reserved Nominal Value Bit 7 Reserved Test_SYSCLKOUT Bit 3 Reserved Bit 2 Reserved Bit 1 Bit 0 Test_SYSCLKO Blocked UT (for test modes) When set, the SYSCLKOUT signal switches to pin RESET_OUT. 14.15 BGP_LPF_EN Address 0x1511 Access Mode R/W Bit 6 Bit 5 Blocked (for test modes) Value At Reset 0x00 Bit 4 Nominal Value Bit 7 BGP_LPF_EN Bit 3 Bit 2 Bit 1 Bit 0 Blocked Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) (for test modes) BGP_LPF_EN When set, the switch is open and bandgap low pass filter is enabled. When reset, the switch is close and bandgap low pass filter is disabled. BGAP 14.16 CODEC Status Indicator Address 0x1512 Access Mode R Bit 6 RESERVED Bit 5 ADC_FIFO _Overflow Value At Reset 0x00 Bit 4 ADC_FIFO _Underflow Bit 7 RESERVED TABV ::rewoP yllppuS TABV rewoP y ppuS TABV ::rewoP yllppuS TABV rewoP y ppuS nepO WS ::tteS nep O WS eS nepO WS ::tteS nep O WS eS esollC WS ::tteseR eso C W S ese R esollC WS ::tteseR eso C W S ese R BGP_LPF_EN Bandgap Bandgap Generator 500K ohm Nominal Value Bit 3 DAC_FIFO _Overflow Bit 2 DAC_FIFO _Underflow Bit 1 ADC_SINC _Overflow Bit 0 ADC_SINC _Underflow - 122 - Publication Release Date: May, 2007 Revision 1.3 W681307 ADC_FIFO_OverflowFIFO pointer overflow in the ADC path. ADC_FIFO_underflowFIFO pointer underflow in the ADC path. DAC_FIFO_OverflowFIFO pointer overflow in the DAC path. DAC_FIFO_underflowFIFO pointer underflow in the DAC path. ADC_SINC_OverflowOverflow indication for ADC SINC filter. ADC_SINC_UnderflowUnderflow indication for ADC SINC filter. 14.17 BandGap Voltage Adjustment Address 0x1513 Access Mode R/W Bit 6 Reserved Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 7 Reserved Bit 3 Bit 2 Bit 1 Bit 0 Vbgp_trimming[5:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80mV 40mV 20mV 10mV 5mV ± Bandgap voltage is default 1V. You can fine tune bandgap voltage follow below formula. When set Vbgp_trimming[5] = 1, BandGap Voltage = 1V 5mV * Vbgp_trimming[4:0] When set Vbgp_trimming[5] = 0, BandGap Voltage = 1V 5mV * Vbgp_trimming[4:0] Where Vbgp_trimming [4:0] is a decimal value and ranges from 0 to 31 14.18 Specific Register Address 0x1514 Access Mode R/W Bit 6 Bit 5 Blocked (for test modes) Value At Reset 0x00 Bit 4 Bit 7 Blocked (for test modes) Blocked (for test modes) 14.19 Linear Regulator Voltage Controller Register Address 0x1515 Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Bit 7 RESERVED RESERVED RESERVED RESERVED REG_LV[1] The output voltage of the embedded linear regulator (REG) is correlated to the internal bandgap voltage. Any tolerance and deviation of the bandgap voltage will cause a deviation of the output voltage of the embedded linear regulator. In order to ease the usage, the adjustment possibilities of output voltage of the linear regulator have been built in to compensate the bandgap variation in process. REG_LV[1:0] REG_LV [1:0] 00 01 10 11 REG Output Voltage 3.0V 3.1V 3.2V 3.3V ＋ － Nominal Value Bit 3 Bit 2 Bit 1 Blocked (for test modes) Bit 0 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 REG_LV[0] RESERVED RESERVED - 123 - Publication Release Date: May, 2007 Revision 1.3 W681307 14.20 Core PWR_Det Address 0x1518 Access Mode R Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 CPWR_Det Nominal Value Bit 7 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 Bit 0 Blocked Blocked (for test modes) (for test modes) CPWR_Det This bit is for core power voltage monitor purpose and read only. When the core power voltage is below 1.7V, this bit will set to low. If the core power voltage is above 1.8V, this bit will set to high. Normally, the core power voltage is 1.9V. This core power voltage monitor function can generate the interrupt and locate at 0x144D[5] register. 14.21 DA High Pass Filter Selection Address 0x151A Access Mode R/W Bit 6 Bit 5 Reserved Value At Reset 0x00 Bit 4 Reserved Nominal Value Bit 7 Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Reserved Disable HPF DA_dither_select Disable HPF DA_ditehr_select when set, disable the High Pass filter D to A directory when set, change D to A dither function is add level (no sign) - 124 - Publication Release Date: May, 2007 Revision 1.3 W681307 14.22 TI Path Selection There is a multiplexer at the input stage to choose which the receiving signal comes from Address 0x1521 Bit 7 RESERVED Bit 6 Access Mode R/W Bit 5 TI2NtoPO2 Value At Reset 0x00 Bit 4 TI2NtoPO1 Nominal Value Bit 3 RESERVED Bit 2 TI2_Buffer_SEL Bit 1 Blocked (for test modes) Bit 0 Path_SEL RESERVED Path_SEL TI2_Buffer_SEL TI2NtoPO1 TI2NtoPO2 When set, the signal is come from TI1- and TI1+ terminal to internal TG OP Amp When reset, the signal is come from TI2- and TI2+ terminal to internal TG OP Amp When set this bit, the TI2 input will provide high input impedance to meet application requirement. When set, the signal TI2N will be connected to internal PO1 Amp. When reset, the signal TI2N will be disconnected to internal PO1 Amp. When set, the signal TI2N will be connected to internal PO2 Amp. When reset, the signal TI2N will be disconnected to internal PO2 Amp. The multiplexers of the TI Path Selection are shown in Figure 14-10. - 125 - Publication Release Date: May, 2007 Revision 1.3 W681307 Figure 14-10 The multiplexers of the TI Path Selection - 126 - Publication Release Date: May, 2007 Revision 1.3 W681307 15. SERIAL PERIPHERAL INTERFACE 15.1 Serial Peripheral Interface – SPI signals • • • • SCK: Input pin in slave mode; output pin in master mode. Serial Clock from Master. Max clock rate is TBD MHz (depends on how fast the CPU to read a word of received data). /SPI_CS: Input pin in slave mode; output pin in master mode. Low active Chip Select signal from Master. MISO: Output pin in slave mode; input pin in master mode. Slave data out to the input of Master. MOSI: Input pin in slave mode; output pin in master mode. Master data out to the input of Slave. If the phase of the clock is zero, i.e. CPHA = 0, data is latched at the rising edge of the clock with CPOL = 0, and at the falling edge of the clock with CPOL = 1. If CPHA = 1, the polarities are reversed. CPOL = 0 means falling edge, CPOL = 1 rising edge. The transmission clock edges are the reversed of sampling edges, shown in Figure 15-1. Timing diagram of CPHA = 0 and CPHA = 1 is shown in Figure 15-2 and Figure 15-3. Figure 15-1 Sampling edges of different modes Figure 15-2 Timing diagram of CPHA = 0 ( SS is the pin /SPI_CS) - 127 - Publication Release Date: May, 2007 Revision 1.3 W681307 Figure 15-3 Timing Diagram of CPHA = 1 ( SS is the pin /SPI_CS) 15.1.1 Address 0x1720 Bit 7 SPI_Enable SPI_Control 0 Access Mode R/W Bit 6 SPI_Master_Mo de Bit 5 Reserved Value At Reset 00 Bit 4 Reserved Nominal Value Bit 3 DumpComp Bit 2 Reserved Bit 1 CPHA Bit 0 CPOL SPI_Enable Spi_master_mode CPOL CPHA DumBcomp SPI interface enable. If SPI_ENB=0, the SPI is disabled and pins defined as original functions. Default to 0. set to 1 in master mode. Default to slave mode Clock polarity, if CPOL=0, clock is active high; if CPOL=1, clock is active low. Default to 0. Clock Phase, determined the sampling clock edge of SCLK. Default to 0. When this bit is on and the received byte is the same as Dumpbyte (0x1724), then no write to RX fifo. SPI mode 0 = 0x80; SPI mode 1 = 0x82; SPI mode 2 = 0x81; SPI mode 3 = 0x83; Note: 0x1720[1:0] = ‘10’ is mode 1 in figure 1; 0x1720[1:0] = ‘01’ is mode 2 in figure 1. 15.1.2 Address 0x1721 Bit 7 SPI_Control 1 Access Mode R/W Bit 6 SPI_Clock Bit 5 Reserved Value At Reset 00 Bit 4 Reserved Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 RxDepth_intr[3:0] Set master spi clock speed. (Master mode only) 00 1.152MHz 01 576KHz 10 256KHz 11 64KHz The SPI in slave mode support maximum clock speed is 576K. SPI_Clock Rxdepth_intr An RxINT interrupt event 1723[bit 4] is generated when received byte count reaches Rxdepth_intr[bit 3:0] +1 bytes. - 128 - Publication Release Date: May, 2007 Revision 1.3 W681307 15.1.3 Address 0x1722 Bit 7 Reserved SPI Status Access Mode R Bit 6 Reserved Bit 5 Reserved Value At Reset 00 Bit 4 RxFIFOgeThres hold Nominal Value Bit 3 TxEmpty Bit 2 RxEmpty Bit 1 TxOverflow Bit 0 RxOverflow RxOverflow TxOverflow RxEmpty TxEmpty RxFIFOgeThreshold When SPI keeps on receiving data and Rx-FIFO is full, the RxOverflow will be set to 1. When 8032 writing data is fast than SPI transmitting rate, the Tx-FIFO will overflow indicated by TxOverflow bit. Indicate the Tx-FIFO is currently empty. Indicate the Tx-FIFO is currently empty. When RX-FIFO reach to RxDepth_intr (0x1721[3:0]), the RxFIFOgeThreshold will set to 1. 15.1.4 Address 0x1723 Bit 7 Reserved SPI Interrupt Enable Access Mode R/W Bit 6 Reserved Bit 5 Reserved Value At Reset 00 Bit 4 RxInt Nominal Value Bit 3 TxEmpty Bit 2 Reserved Bit 1 TxOverflow Bit 0 RxOverflow According to 0x1722, these interrupts will occur if the corresponding interrupts enable. RxOverflow TxOverflow TxEmpty RxInt Rx overflow interrupt enable. Tx overflow interrupt enable. Tx empty interrupt enable. (Recommended this bit served in low data rate interface application.) Rx interrupt enable. RX interrupt occurs upon the number of rx data reaches Rxdepth_intr[3:0]. 15.1.5 Address 0x1724 Bit 7 DumpByte Access Mode R Bit 6 Bit 5 Value At Reset 00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 DumpByte[7:0] If 1720[3] DumpCmp is set to "1", the received byte will be filtered out (No Write to RX-FIFO) when DumpByte is equal to Received Byte. 15.1.6 Address 0x1725 Write TX FIFO Access Mode W Value At Reset 00 Nominal Value - 129 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TxFIFO[7:0] Store data in SPI TX-FIFO when micro controller writes data to this register. 15.1.7 Address 0x1726 Bit 7 Read RX FIFO Access Mode R Bit 6 Bit 5 Value At Reset 00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 RxFIFO[7:0] Read data from SPI RX-FIFO when micro controller read data from this register. 15.1.8 Address 0x1727 Bit 7 Reserved SPI_Transfer_Size Access Mode R/W Bit 6 Reserved Bit 5 Reserved Value At Reset 00 Bit 4 Reserved Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Transfer Size [3:0] SPI_Transfer_Size perform (transfer size+1) bytes of Tx/Rx when start_rtx is set. (master mode only) 15.1.9 Address 0x1728 Bit 7 Reserved SPI_Start_rtx Access Mode R/W Bit 6 Reserved Bit 5 Reserved Value At Reset 00 Bit 4 Reserved Nominal Value Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 Start_rtx Start_rtx Set to 1 to start Tx/Rx for (transfer size+1) bytes; cleared by hardware automatically when it is done. (master mode only) - 130 - Publication Release Date: May, 2007 Revision 1.3 W681307 16. 16.1 SPI FOR SERIAL DATA FLASH Introduction to SPI of Serial Data Flash Winbond W681307 chip embed a SPI of serial data flash (DF_SPI) port which is a 4-pin (SCK, /DF_CS, SDI, SDO) SPI Interface. This SPI interface makes W681307 chip easy to control 4-pin Serial Peripheral Interface (SPI) Data Flash memories. It has various clock speed and data format configurations by setting control register. The SPI interface can be operated at clock rates of up to CPU CLK frequency / 2. 16.2 Block Diagram Figure 16-1 The SPI of the Serial Data Flash block diagram - 131 - Publication Release Date: May, 2007 Revision 1.3 W681307 16.3 Data Format The packet/page data format is separated to 2 fields. First one is the Command field, and the second one is Data field. Command field (1 ~ 5 bytes) is used to send the control instruction/code and access address. The Data field (0 ~ 256 bytes) is used to send/store the write/read data of serial data flash. All of Command and Data bytes are sand MSB first. ◆ ◆ ◆ ◆ Example 1: Single Byte Command Only Example 2: Multiple Bytes Command only Example 3: Single Byte Command with Single Byte Write Data Example 4: Single Byte Command with Single Byte Read Data - 132 - Publication Release Date: May, 2007 Revision 1.3 W681307 ◆ ◆ ◆ ◆ Example 5: Single Byte Command with Multiple Bytes Write Data Example 6: Single Byte Command with Multiple Bytes Read Data Example 7: Multiple Bytes Command with Multiple Bytes Write Data Example 8: Multiple Bytes Command with Multiple Bytes Read Data Both command and data field length can be program with write the CMD_LEN (REG 0x1731[2:0]) and DATA_LEN (REG 0x1732[7:0]). The MAX command field length is 5 bytes. The MAX data field length is 256 bytes. - 133 - Publication Release Date: May, 2007 Revision 1.3 W681307 16.4 FSM There have 3 states in the DF_SPI module : IDLE, CMD and DATA. Step1. While power on reset, the FSM initial is in the IDLE state. Step2. After enable the DF_SPI function (write REG 0x1730[7]=1), the FSM start to wait the CPU control to change to CMD state (write REG 0x1731), then force control logic to shift out the command bytes sequentially to serial data flash. Step3. After finished shift out the command bytes, the FSM will change to DATA state if the Data_enb (REG 0x1731[4]) is true, or run back to IDLE state if the Data_enb is false. Step4. When FSM goes into Data state, the control logic will start to shift out the write out data to serial data flash if DF_RD (REG 0x1731[3]) is false, or shift in the read back data from serial data flash if DF_RD (REG 0x1731[3]) if true. Step5. After finished shift out/in the data bytes, the FSM will go back to IDLE state, and wait for next transition. 16.5 FIFO/RAM The DF_SPI module takes 5 bytes register to write the control command and takes the 256x8 bytes RAM to do the Read/Write access FIFO. It supports 2 kinds of memory access method Type1. FIFO like method: The CPU always read/write the same address, then the hardware control the memory read/write address, and increase the read/write point automatically after each read/write. The current write/read point can be read back at REG 0x173E/0x173F. Type2. Direct access method: The CPU can read/write any byte of the memory with write the read (REG 0x173F)/write (REG 0x173E) point first. 16.6 Interrupt The DF_SPI module supports two kinds of interrupt source. One is the TX/RX finish interrupt, occur while TX/RX byte counts (REG 0x173D) is equal to DATA_LEN, the other is middle flag interrupt, occur while TX/RX byte counts (REG 0x173D) is equal to the 16 * INTR_CNT (REG 0x1733[7:4]). Any other concept, please reference to the description of the registers. 16.7 16.7.1 DF_SPI Register Group DF_CLK Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Bit 4 Bit 3 CLK_REG [6:0] Clock Divider Base to decide the DF_clk clock frequency. DF_CLK freq. = CPU CLK freq. / (CLK_REG + 1) EX: CLK_REG [6:0] = 0x01→ DF_CLK freq. = CPU CLK freq. / 2 CLK_REG [6:0] = 0x03 → DF_CLK freq. = CPU CLK freq. / 4 Note: CLK_REG [6:0] must 1 while DF_CLK active. Address 0x1730 Bit 7 DF_ENB CLK_REG ≧ ≧ ≧ ≧ ： Nominal Value Bit 2 Bit 1 Bit 0 - 134 - Publication Release Date: May, 2007 Revision 1.3 W681307 DF_ENB When set, enable DF_SPI module. When reset, disable DF_SPI module. Note: The FIFO/RAM only can be access while this bit is set enable. 16.7.2 Address 0x1731 Bit 7 DF_CMD_LEN Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Bit 4 DATA_ENB Bit 3 DF_RD Bit 2 Bit 1 CMD_LEN [2:0] Bit 0 Nominal Value CMD_LEN Command Field Length. (unit: byte,CMD_LEN 4) Command Field Length = CMD_LEN + 1 EX: CMD_LEN = 0x03 → Command Field Length = 4 bytes. Read/Write Flag. (1: Read,0: Write) Enable Data Field. (1: Enable, 0: Disable) DF_RD DATA_ENB Note: While DF_ENB = 1, write this byte will force DF module start to TX/RX 16.7.3 Address 0x1732 Bit 7 DF_DATA_LEN Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nominal Value DATA_LEN [7:0] DATA_LEN Data Field Length.(unit: byte) Data Field Length = DATA_LEN + 1 EX: DATA_LEN = 0x0F → Data Field Length = 16 bytes. 16.7.4 Address 0x1733 Bit 7 DF_INTR_REG Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Bit 4 Bit 3 RD_FLAG Bit 2 RX_OK Bit 1 TX_OK Bit 0 INTR_ENB Nominal Value INTR_CNT [3:0] INTR_ENB When set, enable DF module interrupt. When reset, disable DF module interrupt. This module support 2 kind of interrupt source. One is the TX/RX Finished interrupt (occurred while TX/RX bytes = DATA_LEN), the other is internal pre-interrupt (occurred while TX/RX bytes = INTR_CNT * 16). TX Finish Interrupt.( Read Only) This bit will be clear automatically while next TX/RX TX_OK - 135 - ≦ Publication Release Date: May, 2007 Revision 1.3 W681307 RX_OK RX Finish Interrupt.( Read Only) This bit will be clear automatically while next TX/RX The same with DF_RD. ( Read Only) Internal Pre Interrupt. Internal interrupt @ TX/RX byte count = (INTR_CNT * 16). If want to disable the internal pre-interrupt, please set INTR_CNT = 0 While internal pre-interrupt occurred, the interrupt status TX_OK/RX_OK will be both zero. The RD_FLAG will indicate the pre-interrupt is TX or RX. EX:INTR_CNT [3:0] = 0x01 → internal interrupt @ TX/RX = byte 16. RD_FLAG INTR_CNT 16.7.5 Address 0x1734 Address 0x1735 Address 0x1736 Address 0x1737 Address 0x1738 Bit 7 DF_CMD_B1 ~ DF_CMD B5 Access Mode R/W Access Mode R/W Access Mode R/W Access Mode R/W Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Value At Reset 00 Value At Reset 00 Value At Reset 00 Value At Reset 00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nominal Value Nominal Value Nominal Value Nominal Value Nominal Value CMD_B1 [7:0] CMD_B2 [7:0] CMD_B3 [7:0] CMD_B4 [7:0] CMD_B5 [7:0] CMD_B1 CMD_B2 CMD_B3 CMD_B4 CMD_B5 Command Byte 1.(0x1734) Command Byte 2.(0x1735) Command Byte 3.(0x1736) Command Byte 4.(0x1737) Command Byte 5.(0x1738) - 136 - Publication Release Date: May, 2007 Revision 1.3 W681307 16.7.6 Address 0x173B Bit 7 DF_CLK_FORMAT Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Bit 4 Bit 3 CSN_MORE Bit 2 CK_MORE Bit 1 CP Bit 0 CI Nominal Value There have 4 control bits (CSN_MORE, CK_MORE, CP and CI) to decide the DF_SPI data format. CSN_MORE When set, DF_CSN toggling only while DF_CLK stable. CK_MORE CP Extend one more clock before/after signal DF_CSN active. DF_CLK transition position setting. When CP = 1, DF_CLK start toggling in the middle of transfer. When CP = 0, DF_CLK start toggling at the beginning of transfer. DF_CLK level while DF_CSN is non active. When CI = 1, DF_CLK is high while DF_CSN is non active. When CI = 0, DF_CLK is low while DF_CSN is non active. When set, DF_CSN toggling only while DF_CLK stable. CI CSN_MORE CK_MORE Extend one more clock before/after signal DF_CSN active. CP DF_CLK transition position setting. -- When CP = 1, DF_CLK start toggling in the middle of transfer. -- When CP = 0, DF_CLK start toggling at the beginning of transfer. - 137 - Publication Release Date: May, 2007 Revision 1.3 W681307 CI DF_CLK level while DF_CSN is non active -- When CI = 1, DF_CLK is high while DF_CSN is non active. -- When CI = 0, DF_CLK is low while DF_CSN is non active. Note: For W25X and W25P serial SPI-Flash, these control bits are all zeros. 16.7.7 Address 0x173C Bit 7 DF_FIFO_DATA Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nominal Value FIFO_DATA [7:0] FIFO_DATA TX/RX FIFO Read/Write data. When write this byte, i.e. put transmit data into FIFO. When read this byte, i.e. read back the current data in FIFO. After Read/Write this byte, the CPU read/write point will increase one automatically. 16.7.8 Address 0x173D Bit 7 DF_CNT Access Mode R Bit 6 Bit 5 Value At Reset 00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nominal Value DF_CNT [7:0] DF_CNT Current TX/RX byte count point. - 138 - Publication Release Date: May, 2007 Revision 1.3 W681307 16.7.9 Address 0x173E Bit 7 DF_WR_CNT Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nominal Value DF_WR_CNT [7:0] DF_WR_CNT CPU current write-point. (unit: byte) Write this byte will force CPU write point set to the DF_WR_CNT value. 16.7.10 Address 0x173F Bit 7 DF_RD_CNT Access Mode R/W Bit 6 Bit 5 Value At Reset 00 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Nominal Value DF_RD_CNT [7:0] DF_RD_CNT CPU current read-point. (unit: byte) Write this byte will force CPU read point set to the DF_RD_CNT value. 16.8 1. Example of W25X20/40/80 Serial Flash Write Enable(0x1734 = 06) / Write Disable(0x1734 = 04) / Chip Erase(0x1734 = C7) / Power-down(0x1734 = B9) 0x1730 = 0x81// Set DF_enb, CLK = CPU clock / 2 0x1734 = 0x06// Set CMD Byte1 0x06 / 0x04 / 0xC7 / 0xB9 (code) 0x1731 = 0x00// Force 1 byte TX (CMD) 2. Read Status Register(0x1734 = 05) 0x1730 = 0x87// Set DF_enb, CLK = CPU clock / 8 0x1732 = 0x00// Set CMD Data Field Length = 1 byte 0x1734 = 0x05// Set Byte1 0x05 (code) 0x1731 = 0x18// Force 1 byte TX (CMD), and 1 byte RX 3. Write Status Register(0x1734 = 01) 0x1730 = 0x8A// Set DF_enb, CLK = CPU clock / 11 0x1734 = 0x01// Set CMD Byte1 0x01 (code) 0x1735 = 0x04// Set CMD Byte2 0x04 (S7-S0) 0x1731 = 0x01// Force 2 bytes TX (CMD) 4. Block Erase(0x1734 = D8) / Sector Erase(0x1734 = 20) 0x1730 = 0x8A// Set DF_enb, CLK = CPU clock / 11 0x1734 = 0xD8// Set CMD Byte1 0xD8 / 0x20 (code) 0x1735 = 0x34// Set CMD Byte2 0x34 (A23-A16) 0x1736 = 0x35// Set CMD Byte3 0x35 (A15-A8) 0x1737 = 0x36// Set CMD Byte4 0x36 (A7-A0) 0x1731 = 0x03// Force 4 bytes TX (CMD) - 139 - Publication Release Date: May, 2007 Revision 1.3 W681307 5. Read Data (0x1734 = 03) 0x1730 = 0x8B// Set DF_enb, CLK = CPU clock / 12 0x1732 = 0x0F// Set Data Field Length = 16 bytes 0x1733 = 0x01// Enable Interrupt 0x1734 = 0x03// Set CMD Byte1 0x03 (code) 0x1735 = 0x04// Set CMD Byte2 0x04 (A23-A16) 0x1736 = 0x05// Set CMD Byte3 0x05 (A15-A8) 0x1737 = 0x06// Set CMD Byte4 0x06 (A7-A0) 0x1731 = 0x1B// Force 4 bytes TX (CMD), and 16 bytes RX (DATA) 6. Page Program (0x1734 = 02) 0x1730 = 0x83// Set DF_enb, CLK = CPU clock / 4 0x1732 = 0x0F// Set Data Field Length = 16 bytes 0x1734 = 0x02// Set CMD Byte1 0x02 (code) 0x1735 = 0x52// Set CMD Byte2 0x54 (A23-A16) 0x1736 = 0x51// Set CMD Byte3 0x55 (A15-A8) 0x1737 = 0x50// Set CMD Byte4 0x56 (A7-A0) 0x173E = 0x00// Reset CPU write point to 0x00 0x173C = 0xD0// Write Data Byte 1 (first data byte) 0x173C = 0xDF// Write Data Byte 16 (last data byte) 0x1731 = 0x13// Force 4 bytes TX (CMD), and 16 bytes TX (DATA) 7. Release Power-down and Device ID (0x1734 = AB) 0x1730 = 0x84// Set DF_enb, CLK = CPU clock / 5 0x1732 = 0x00// Set Data Field Length = 1 bytes 0x1734 = 0xAB// Set CMD Byte1 0xAB (code) 0x1735 = 0x00// Set CMD Byte2 0x00 (dummy) 0x1736 = 0x00// Set CMD Byte3 0x00 (dummy) 0x1737 = 0x00// Set CMD Byte4 0x00 (dummy) 0x1731 = 0x1B// Force 4 bytes TX (CMD), and 1 byte RX (DATA) Manufacturer-Device ID(0x1734 = 90) 0x1730 = 0x85// Set DF_enb, CLK = CPU clock / 6 0x1732 = 0x01// Set Data Field Length = 2 bytes 0x1734 = 0x90// Set CMD Byte1 0x90 (code) 0x1735 = 0x00// Set CMD Byte2 0x00 (dummy) 0x1736 = 0x00// Set CMD Byte3 0x00 (dummy) 0x1737 = 0x00// Set CMD Byte4 0x00 (00h) 0x1731 = 0x1B// Force 4 bytes TX (CMD), and 2 bytes RX (DATA) 8. 9. JEDECID(0x1734 = 9F) 0x1730 = 0x85// Set DF_enb, CLK = CPU clock / 6 0x1732 = 0x02// Set Data Field Length = 3 bytes 0x1734 = 0x9F// Set CMD Byte1 0x9F (code) 0x1731 = 0x18// Force 1 bytes TX (CMD), and 3 bytes RX (DATA) - 140 - Publication Release Date: May, 2007 Revision 1.3 W681307 17. WINBOND 2-WIRE SERIAL BUS 17.1 Introduction to Winbond 2-Wire Serial bus Winbond 2-wire serial bus (W2S) is a simple bi-directional 2-wire bus for efficient inter-IC control. This design is for W2S master use only, and governed by micro controller, typically an 8032. The W2S used in the chip is used to both read/write from/to EEPROM and control melody device. The W2S master controller equips 35 bytes FIFO performing W2S formatting and de-formatting. The micro controller can simply fill up the FIFO contents which consists of target device ID, high/low address (depend on the device format); for reading, just set read enable , for writing, keep writing data to FIFO then set write enable to launch transmission. The W2S master controller supports up to 3 kinds of page writing, i.e. 8, 16, 32 bytes. The W2S master controller designed to support maximum 32 bytes per page, and the FIFO depth is calculated as 3 header bytes (one device ID, two address) plus 32 bytes for data. It has various bus speed configurations to support wide range of EEPROM bus speed. 17.2 17.2.1 The Description of W2S Register W2S_Enable Access Mode R/W Bit 6 W2S_Port_Sel Bit 5 RESERVED Address 0x1740 Bit 7 W2S_ENA Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 W2S_HW _Protection W2S_ENA: Set this bit will activate W2S bus controller. W2S_Port_Sel: Pin selection for hardware W2S bus function. W2S_Port_Sel Pin name 0 P1.2 : SDA0 P1.3 : SCL0 1 P1.3 : SDA1 P1.4 : SCL1 If W2S_HW_Protection is set to 1, the couple of pins set by bit W2S_Port_Sel become tri-state as core power below the operation voltage (see following table). Micro-C must set W2S_ENA bit before setup Force_Activity (0x1745) register, and the content of W2S Status (0x1746) is valid only if W2S_ENA bits is set to 1. W2S_HW_Protection: Set this bit will force W2S bus pins into tri-state output mode, when the CPWR_Det is low activity. Which pins will be forced to tri-state output is dependent on the W2S_ENA and W2S_Port_Sel bits setting. The forced pins are listed as below when the bit CPWR_Det is low. That means the core power voltage is below 1.7V. And the hardware W2S bus will into protection mode to avoid the E2PROM data corruption. Table 17-1 CPWR_Det 0 1 (Read only) W2S_HW_Protection 0 1 Don’t care X W2S_ENA Don’t care Don’t care X W2S_Port_Sel 0 1 Don’t care X V X X P1.2 X V V X P1.3 X X X P1.4 V PS V means this pin is forced to tri-state output mode. X means this pin state no any change. ： ※ ※ - 141 - Publication Release Date: May, 2007 Revision 1.3 W681307 17.2.2 Address 0x1741 Bit 7 RESERVED EEPROM_Config Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 Bit 1 Bit 0 HEADER EEPROM_Format This register is used for W2S bus read cycle. EEPROM_Format is used for different Page Mode: EEPROM_format Page Mode 00 8-byte 01 16-byte 10 32-byte 11 RESERVED HEADER bit is used to support different page size of EEPROM. “0” is for C16, “1” is for C32/64/128/256 17.2.3 Address 0x1742 Bit 7 Prescale_Lo Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Prescale_Lo This register is used to control W2S bus speed, companion with Prescale_Hi register. For 100KHz W2S bus operation, set Prescale_Lo to 22H, and Prescale_Hi to 00H. 17.2.4 Address 0x1743 Bit 7 Prescale_Hi Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Prescale_Hi This register is used to control W2S bus speed, companion with Prescale_Lo register. For 100KHz W2S bus operation, set Prescale_Lo to 22H, and Prescale_Hi to 00H. Prescale Reg. Value W2S Bus Clock 0x0068 33 KHz 0x0034 66 KHz 0x0022 100 KHz 0x0019 133 KHz 0x0014 166 KHz 0x0006 500 KHz System Clock: 13.824 MHz W2S Bus Clock = System Clock 4 × (Prescale + 1) Publication Release Date: May, 2007 Revision 1.3 - 142 - W681307 17.2.5 Address 0x1744 Bit 7 RdWrFIFO Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 8-bit data from/to FIFO This register can be used for W2S both read and write W2S-bus compatible device. Writing data (including target device ID, high address, low address, and repeat ID, Data) to this register will be automatically stored in W2S controller FIFO. When micro-C receives interrupt from W2S, micro-C need to check W2SStatus (0x1746) register to confirm the transmission is OK. If there is no error during W2S read process, micro-C can start reading FIFO content by reading RdWrFIFO register. Micro-C must set RDActive bit (0x1745[5]) before start reading RdWrFIFO (0x1744) W2S FIFO content. RDActive: Set RDActive bit will enable the read capability of RdWrFIFO (0x1744). To achieve STOP pattern on W2S bus at power on initial, it can send “acknowledge polling” pattern. How to send “acknowledge polling” pattern: After bit W2S_ENA (of register 1470) set 1, writes 0x00H or 0xA0H to FIFO (0x1744H). Finally, sets Force_Activity (0x1745) to 0x01H. After these operations, W2C controller can start reading from or writing to EEPROM. This mechanism used for once when power on is an option to enhance EEPROM stability. Set Rst_Rd_Ptr bit will rest W2S controller internal FIFO read pointer. Set Rst_Wr_Ptr bit will rest W2S controller internal FIFO write pointer. RDWRn: For Read operation, reset RDWRn to 0, for Write operation, set RDWRn to 1. Set RDWR_en bit will enable read or write operation depend on RDWRn. Micro-C must set W2S_ENA bit before setup Force_Activity. Write 0xFF to 0x1746 to reset all W2S_Status bits and reset W2S-FIFO both read and write pointer (0x1745[3] and 0x1745[2] set to 1) and then clear (0x1745[3] and 0x1745[2] reset to 0) before enable read or write operation. FIFO_empty bit will generate W2S interrupt during write operation. FIFO_full bit will generate W2S interrupt during read operation. ACK_Fail bit indicates that there is no response for target device during ACK period Rread or Write process, this bit will generate W2S interrupt. W2S_Status register content is valid only if W2S_ENA bit has been set. ※ ※ ※ ※ 17.2.6 Address 0x1745 Bit 7 RESERVED Force_Activity Access Mode R/W Bit 6 RESERVED Bit 5 RDActive Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 Rst_Rd_Ptr Bit 2 Rst_Wr_Ptr Bit 1 RDWRn Bit 0 RDWR_en 17.2.7 Address 0x1746 Bit 7 RESERVED W2S_Status Access Mode R Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 FIFO_empty Bit 1 FIFO_full Bit 0 ACK_Fail - 143 - Publication Release Date: May, 2007 Revision 1.3 W681307 17.2.8 Address 0x1747 Bit 7 RESERVED FIFORdPtr Access Mode R Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 FIFORdPtr Bit 2 Bit 1 Bit 0 This register is used to monitor W2S FIFO read pointer. 17.2.9 Address 0x1748 Bit 7 RESERVED FIFOWrPtr Access Mode R Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 FIFOWrPtr Bit 2 Bit 1 Bit 0 This register is used to monitor W2S FIFO write pointer. 17.2.10 Address 0x1749 Bit 7 AckFailEna ForceAckFail Access Mode R/W Bit 6 RESERVED Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 AckFailPtr Bit 2 Bit 1 Bit 0 AckFailEna: Enable Ack Fail Event AckFailPtr: During write data to EEPROM or Melody devices, the Ack Fail event will occur at the AckFailPtr-th data of W2S FIFO content. 17.2.11 Address 0x174A Bit 7 RESERVED W2S_Misc Access Mode R Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 SCL_in Nominal Value Bit 3 Bit 2 C_STATE Bit 1 Bit 0 W2SIntrpt This register only monitor several status. SCL_in: 0: current SCL_in is pull low, 1: current SCL_in pull high. C_STATE: current finite state machine state. W2SIntrpt: current interrupt signal indication. - 144 - Publication Release Date: May, 2007 Revision 1.3 W681307 18. 18.1 USB DEVICE CONTROLLER AND TRANSCEIVER Overview W9681307 is built in a fully functional USB 1.1 controller to be an USB device. It supports most functions of USB 1.1 standard specification and some required functions of USB audio class and HID class profiles for driver free on Microsoft OS in Skype or VOIP wireless applications. In ISP mode application, users also can download program code between PC and external ROM flash memory via USB now. The USB core embeds one 512x8 byte rom to store default descriptors. In the setting, the USB core includes four interfaces and seven endpoints to handle above applications. 18.2 Functionality Figure 18-1 The USB block diagram The USB block diagram is shown in Figure 18-1. The USB module supports all transfer types (Control Endpoint 0, Bulk In, Bulk Out, Interrupt In, Isochronous In, and Isochronous Out) in. USB 1.1 spec and W681307 USB embeds seven Endpoints include Control Endpoint 0. The default descriptors are stored in the 512x8 Bytes ROM. The SIE module is for handle USB series-interface-engine functions. UCOM module is a bridge to communicate SIE and all transfer type modules. Register Control module is for handle CPU read/write and data signals of W681307 USB registers. Gain Stage is required for adjust gain of pcm data in audio volume control application. USB Test module connects many internal signals to test pins for help monitor them from outside. The feature of the USB module is as follows USB Specification version 1.1 compliant Full-Speed (12MHz) Audio Class Interface and Command support (Volume Control, Mute Control) HID Class Interface and Command support (Set Report) USB ISP mode support Vendor Command support Programmable to connect/disconnect 1.5Kohm pull-up resistance on D+ bus Support five interfaces and seven endpoints (Control, Bulk In, Bulk Out, Interrupt In, Isochronous In, and Isochronous Out) Ping-Pong FIFO control for Bulk In/Bulk Out transfer to get better performance Provide one of three bytes isochronous in endpoint to synchronize isochronous out endpoint for let PC trim the speed of data stream to improve voice quality. ： - 145 - Publication Release Date: May, 2007 Revision 1.3 W681307 Mass Storage Class Command support (GER_MAX_LUN) 18.2.1 Endpoints The definitions of embedded Endpoints are in Table 18-1. Address 0 1 2 3 4 5 6 Type Control ISO ISO Bulk Bulk Interrupt ISO Direction IN/OUT IN OUT IN OUT IN IN Maximum Packet Size (Bytes) 8 16 18 64 64 8 3 Memory Type Registers 64x16 (Shared – double buffer) 128 x 8 (double buffer) 128 x 8 (double buffer) Registers Registers Table 18-1 W681307 USB Endpoint Definitions 18.2.2 Descriptor Rom The default descriptors are stored in the 512x8 Bytes ROM. The address mapping and bank definition of this ROM are shown in Figure 18-2. The logical topology from these descriptors is shown in Figure 18-3. 0x000H ~ 0x011H Device Descriptor Configuration Descriptor + Interface Descriptor + Endpoint Descriptor + 18 Bytes 0x012H ~ 0x17FH Audio Class Descriptor + HID Descriptor + Report Descriptor 366 Bytes 0x180H ~ 0x183H 0x184H ~ 0x1BFH 0x1C0H ~ 0x1DFH 0x1E0H ~ 0x1FFH String Descriptor Index 0 String Descriptor Index 1 String Descriptor Index 2 String Descriptor Index 3 4 Bytes 60 Bytes 32 Bytes 32 Bytes Figure 18-2 Descriptor ROM Definitions - 146 - Publication Release Date: May, 2007 Revision 1.3 W681307 Figure 18-3 The Local Topology of Embedded Descriptors 18.2.3 Configurations and Interfaces The configuration and interface settings in W681307 USB are shown in Figure 18-3. The descriptions are as follows Configuration 0 : The default configuration for all usb devices Interface 0 : The default interface for all usb devices Configuration 1 Interface 0 : Audio Class Interface Interface 1 : Audio Class Interface for record mode Alternate 0 : record off Alternate 1 : record on Interface 2 : Audio Class Interface for play mode Alternate 0 : play off Alternate 1 : play on Interface 3 : HID Class Interface for commands/status communications Interface 4 : Non-Class Interface for USB ISP mode or mass data transfer ： - 147 - Publication Release Date: May, 2007 Revision 1.3 W681307 18.2.4 Audio Class W681307 USB provides Audio Class interfaces so it does not need extra driver to be an USB audio device in Microsoft O/S (Windows 2000/XP). Figure 18-4 is shown an USB audio class device topology from embedded descriptors. Audio Function ID1 MIC ID3 ID2 OT USB Streaming (USB IN) ISO IN (EP1) IT USB Streaming (USB OUT) ISO OUT (EP2) ISO IN (EP6) ID4 IT ID6 ID5 OT Speaker Interface 1 (alternate 1) Interface 2 (alternate 1) Figure 18-4 USB Audio Class Device Topology W681307 USB implements Volume Control and Mute Control in Play and Record modes. 18.2.4.1 Play Mode We define the play mode as the traffic flows from the host to the USB device and to the baseband. The Host can turn on/off the play mode by setting the alternative value from SET INTERFACE 2 command. 18.2.4.2 Record Mode Define the record mode as the traffic flows from the baseband to the USB host. The Host can turn on/off the record mode by setting the alternative value from SET INTERFACE 1 command. 18.2.4.3 Mute Control The host can issue SET_CUR command with wValue equals to 0x100 to change the Mute function of the USB device. The host can turn on/off the Mute as requests by the users. If the host selects Feature Unit number 1 (ID is 3), the Mute of audio stream from Mic to USB is changed; if the host selects Feature Unit number 2 (ID is 6), the Mute of audio stream from USB to speaker is updated. The host also can issue GET_CUR command to read back current Mute status. Play Mode ON ON OFF OFF Record Mode ON OFF ON OFF Play Data to Baseband If Play Mute is On, send 16’h0000; otherwise same as data from host If Play Mute is On, send 16’h0000; otherwise same as data from host 16’h0000 16’h0000 Record Data to Host If Record Mute is On, send 16’h0000; otherwise same as data from Baseband No data to host If Record Mute is On, send 16’h0000; otherwise same as data from Baseband No data to host - 148 - Publication Release Date: May, 2007 Revision 1.3 W681307 Play Mute On/Off means SET_CUR for Mute Control and Feature Unit ID 6 then received data = 1/0 Record Mute On/Off means SET_CUR for Mute Control and Feature Unit ID 3 then received data = 1/0 18.2.4.4 Volume Control The host can issue SET_CUR commands with wValue equals to 0x0200 to change the Volumes of the USB device. If the host selects Feature Unit number 1 (ID is 3), the Volume of audio stream from Mic to USB (means Record Volume) is changed; if the host selects Feature Unit number 2 (ID is 6), the Volume of audio stream from USB to speaker (means Play Volume) is updated. The host also can issue GET_CUR command to read back current volume gain value. Data Settings & Gain Mapping Play Data to BASEBAND Record Data to Host 0x7FFF +24 dB If host sends SET_CUR for volume control If host sends SET_CUR for volume in Play path, device will adjust gain of control in Record path, device will adjust … +24 dB pcm_tx[15:0] via the command then enter gain of pcm_rx[15:0] via the command 0x18xx +24 dB BASEBAND after leave ISO out FIFO then enter ISO IN FIFO 0x17xx +23 dB … … 0x01xx +1 dB 0x00xx 0 dB 0xFFxx -1 dB 0xFExx -2 dB … … 0xE2xx -29 dB 0xE1xx -30 dB … -30 dB 0x8000 -30 dB The default value of GET_CUR for Volume Control is 0x0000 (0 dB) GET_MIN is 0xE100 (-30dB), GET_MAX is 0x1800 (+24 dB) and GET_RES is 0x0100 (+1 dB) 18.2.4.5 Synchronization for Data Transfer To better synchronization, an endpoint (endpoint 6) is dedicated to provide rate adjustment information to host. The descriptor can set a time interval, so the host will request the rate information (3 bytes) from that endpoint by using that frequency. 18.2.4.6 Audio Data Format The data format is 16 bits linear PCM in Audio path and the sample frequency is 8 KHz. 18.2.5 HID Class Interface 3 is a HID Class interface and it has one Interrupt In endpoint. The device can receive commands from host via SET REPORT and report hardware’s status to host via Interrupt In transfer in Skype application. 18.2.5.1 Set (Feature) Report In default descriptors, define 8 bytes feature report descriptors in Report Descriptor. Host can send Set Report command to device then the device can do the action after receive and analyze these 8 bytes data. We use the way to deliver Skype or Winbond commands from host to device. 18.2.5.2 Interrupt In We use the interrupt in transfer to report the device status to host. The maximum packet size is 8 bytes and the time of polling interval is about 64 ms. - 149 - Publication Release Date: May, 2007 Revision 1.3 W681307 18.2.6 USB ISP mode Interface 4 does not belong to any class. It has one Bulk In and Bulk Out endpoints. Both maximum packet sizes are 64 bytes. For gain better performance, we implement ping-pong FIFO control in Bulk In/Out transfer. USB ISP mode uses interface 4. It can download code from PC to external flash by Bulk Out or read the code of external flash on PC by Bulk In via USB bus after install the driver. 18.2.7 Vendor Command The Vendor command is supported. The bits [6:5] = 2 means Vendor command and bit 7 means data transfer direction in byte 0 of SETUP data in USB 1.1 spec. Based on the rules, users can define individual vendor commands and use them to communicate host and device. 18.3 18.3.1 USB Registers USB Enable Register Access Mode R/W Bit 6 RESERVED Bit 5 SE0_Dis Address 0x1800 Bit 7 RESERVED Value At Reset 0x00 Bit 4 R_PullUp Nominal Value Bit 3 TRX_EN Bit 2 PLL_EN Bit 1 Suspend_EN Bit 0 USB_Reset USB_Rese Suspend_EN PLL_EN TRX_EN R_PullUp SE0_Dis Active High. Reset USB digital part. And when S/W receive RESET Interrupt (from host), could use this bit to reset USB. Active High. Active High and disable the bias current of Transceiver. Active High. Enable charge pump and VCO. Active High. Enable Transceiver. Active High. Enable a pull-up resister (1.5K ohm) to D+. Active High, disable SE0. Default is Low, and set D+ and D- to “0”. When USB device need to enable a pull-up resister to D+, it also need to disable SE0 state. 18.3.2 18.3.2.1 Address 0x1801 Bit 7 SET_HID _Intrpt USB Interrupt Register A Enable Access Mode R/W Bit 6 RESERVED Bit 5 CDI_Intrpt Value At Reset 0x00 Bit 4 CDO_Intrpt Nominal Value Bit 3 IRQI_Intrpt Bit 2 BKO_Intrpt Bit 1 BKI_Intrpt Bit 0 VENDER _Intrpt 18.3.2.2 Address 0x1802 Status Access Mode R Value At Reset 0x00 Publication Release Date: May, 2007 Revision 1.3 Nominal Value - 150 - W681307 Bit 7 SET_HID _Intrpt Bit 6 RESERVED Bit 5 CDI_Intrpt Bit 4 CDO_Intrpt Bit 3 IRQI_Intrpt Bit 2 BKO_Intrpt Bit 1 BKI_Intrpt Bit 0 VENDER _Intrpt 18.3.2.3 Address 0x1803 Bit 7 SET_HID _Intrpt Clear Access Mode W Bit 6 RESERVED Bit 5 CDI_Intrpt Value At Reset 0x00 Bit 4 CDO_Intrpt Nominal Value Bit 3 IRQI_Intrpt Bit 2 BKO_Intrpt Bit 1 BKI_Intrpt Bit 0 VENDER _Intrpt VENDER_Intrpt BKI_Intrpt BKO_Intrpt IRQI_Intrpt CDO_Intrpt CDI_Intrpt SET_HID_Intrpt Detection of Vender request Detection of Bulk In(EP3) request Detection of Bulk Out(EP4) request Detection of Interrupt In(EP5) request Detection of Control Out (EP0) request Detection of Control In(EP0) request Detection of Set HID report request 18.3.3 18.3.3.1 Address 0x1804 Bit 7 PlayOn _Intrpt USB Interrupt Register B Enable Access Mode R/W Bit 6 RecordOn _Intrpt Bit 5 RESERVED Value At Reset 0x00 Bit 4 CONNECT _Intrpt Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Host_RESET _Intrpt USB_ERROR_I Host_RESUME_I Host_SUSPEND ntrpt ntrpt _Intrpt 18.3.3.2 Address 0x1805 Bit 7 PlayOn _Intrpt Status Access Mode R Bit 6 RecordOn _Intrpt Bit 5 RESERVED Value At Reset 0x00 Bit 4 CONNECT _Intrpt Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Host_RESET _Intrpt USB_ERROR_I Host_RESUME_I Host_SUSPEND_I ntrpt ntrpt ntrpt - 151 - Publication Release Date: May, 2007 Revision 1.3 W681307 18.3.3.3 Address 0x1806 Bit 7 PlayOn _Intrpt Clear Access Mode W Bit 6 RecordOn _Intrpt Bit 5 RESERVED Value At Reset 0x00 Bit 4 CONNECT _Intrpt Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Host_RESET _Intrpt USB_ERROR Host_RESUME_I Host_SUSPEND ntrpt _Intrpt _Intrpt Host_RESET_Intrpt Host_SUSPEND_Intrpt Host_RESUME_Intrpt USB_ERROR_Intrpt CONNECT_Intrpt RecordOn_Intrpt PlayOn_Intrpt Detection of Reset request. Detection of Suspend request Detection of Resume request Detection of Error request (ex: CRC) Detection of connect Detection of Record On Detection of Play On 18.3.4 18.3.4.1 Address 0x1810 Bit 7 RESERVED EndPoint 0 – Control In/Out Registers Control Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 HID_FIFO _Empty Bit 1 SDO_RD Bit 0 CTL_IN_RDY CTL_IN_RDY SDO_RD HID_FIFO_Empty Active High. Control In(EP0) Data is ready. S/W needs to set this bit when they finished writing the Control In Data (Max: 8 bytes) Setup or Data out packet is reading for control transfer. While S/W complete to read the control HID Out Data (0x1820 ~0x1827), set “HID_FIFO_Empty” to High. USB device will send NAK before “HID_FIFO_Empty” setting to High. 18.3.4.2 Address 0x1811 Bit 7 Control In Data Access Mode W/R Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 CTLI_D [7:0] CTLI_D Control in Data. Internal FIFO has 8 bytes. - 152 - Publication Release Date: May, 2007 Revision 1.3 W681307 18.3.4.3 Address 0x1820 ~ 0x1827 Bit 7 Control HID Out Data Access Mode R Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 CTLO_HID0 [7:0] ~ CTLO_HID7 [7:0] 18.3.4.4 Address 0x1828 ~ 0x182F Bit 7 Control Out Data Access Mode R Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 CTLO_D0 [7:0] ~ CTLO_D7 [7:0] 18.3.5 18.3.5.1 Address 0x1830 Bit 7 RESERVED EndPoint 1 and 2 – ISO In/Out Registers Control Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 ISO_EN Bit 0 ISO_RST ISO_RST ISO_EN Active High reset ISO In/Out function Active High, enables ISO In/Out function. 18.3.5.2 Address 0x1838~0x1839 Bit 7 ISO SYNC Speed Register Access Mode R/W Bit 5 Value At Reset 0xFFC0 Bit 4 Nominal Value Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_0[15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_0[7:0] - 153 - Publication Release Date: May, 2007 Revision 1.3 W681307 Address 0x183A~0x183B Bit 7 Bit 6 Access Mode R/W Bit 5 Value At Reset 0xFFE0 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_1[15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_1[7:0] Address 0x183C~0x183D Bit 7 Bit 6 Access Mode R/W Bit 5 Value At Reset 0xFFF0 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_2[15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_2[7:0] Address 0x183E~0x183F Bit 7 Bit 6 Access Mode R/W Bit 5 Value At Reset 0xFFFE Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_3[15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_3[7:0] Address 0x1840~0x1841 Bit 7 Bit 6 Access Mode R/W Bit 5 Value At Reset 0x0002 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_4[15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_4[7:0] Address 0x1842~0x1843 Access Mode R/W Value At Reset 0x0010 Nominal Value - 154 - Publication Release Date: May, 2007 Revision 1.3 W681307 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_5[15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_5[7:0] Address 0x1844~0x1845 Bit 7 Bit 6 Access Mode R/W Bit 5 Value At Reset 0x0020 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_6[15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_6[7:0] Address 0x1846~0x1847 Bit 7 Bit 6 Access Mode R/W Bit 5 Value At Reset 0x0040 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_7[15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISO_SYNC_SPEED_7[7:0] 18.3.6 18.3.6.1 Address 0x1848 Bit 7 RESERVED EndPoint 3 – Bulk In Registers Control Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 BKI_EN Bit 0 BKI_RST BKI_RST BKI_EN: Active High, reset Bulk In function Active High, enable Bulk In function. - 155 - Publication Release Date: May, 2007 Revision 1.3 W681307 18.3.6.2 Address 0x1849 Bit 7 Bulk In Data Access Mode W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 BKI_DATA[7:0] BKI_DATA Bulk_In Data except final data. 18.3.6.3 Address 0x184A Bit 7 Bulk In Final Data Access Mode W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 BKI_EOP_DATA[7:0] BKI_EOP_DATA Bulk_In end of packet data. 18.3.6.4 Address 0x184B Bit 7 RESERVED Bulk In FIFO Empty Flag Access Mode R Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 BKI_FIFO _Empty Value At Reset Nominal Value BKI_FIFO_Empty FIFO 0 or FIFO 1 empty flag. S/W needs to check this bit to decide if there still had empty FIFO to write. 18.3.7 18.3.7.1 Address 0x1850 Bit 7 RESERVED EndPoint 4 – Bulk Out Registers Control Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 BKO_EN Bit 0 BKO_RST BKO_RST BKO_EN Active High, reset Bulk Out function Active High, enable Bulk Out function - 156 - Publication Release Date: May, 2007 Revision 1.3 W681307 18.3.7.2 Address 0x1851 Bit 7 RESERVED Bulk Out FIFO Length Access Mode R Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 BKO_FIFO_LEN[6:0] Bit 2 Bit 1 Bit 0 BKO_FIFO_LEN [6:0] It will show the present FIFO length. 18.3.7.3 Address 0x1852 Bit 7 Bulk Out Data Access Mode R Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 BKO_D [ 7:0 ] BKO_D Bulk Out Data. 18.3.8 18.3.8.1 Address 0x1858 Bit 7 RESERVED EndPoint 5 – Interrupt In Registers Control Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 IRQI_EN Bit 0 IRQI_RST IRQI_RST IRQI_EN Active High, reset IRQI (EP5) function Active High, enable IRQI (EP5) function 18.3.8.2 Address 0x1859 Bit 7 RESERVED USB Interrupt Data Length Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 IRQI_Start Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 IRQI_LEN [3:0] IRQI_LEN [3:0] IRQI_Start Interrupt In (EP5) data length. Active High, Interrupt In (EP5) active. - 157 - Publication Release Date: May, 2007 Revision 1.3 W681307 18.3.8.3 Address 0x1860 ~0x186F Bit 7 Interrupt In Data Access Mode R/W Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 IRQI_D0 [7:0] ~ IRQI_D15 [7:0] Total 16 bytes Interrupt In Data. 18.3.9 Address 0x1870 -1873 Bit 7 Specific Register Access Mode R/W Bit 6 Bit 5 Value At Reset 0x00 Bit 4 Nominal Value Bit 3 Bit 2 Bit 1 Bit 0 Blocked (for test modes) 18.3.10 Address 0x1874 Bit 7 RESERVED Specific Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 Bit 1 Bit 0 Blocked Blocked Blocked (for test modes) (for test modes) (for test modes) 18.3.11 Address 0x1875 Bit 7 RESERVED Specific Register Access Mode R/W Bit 6 RESERVED Bit 5 RESERVED Value At Reset 0x00 Bit 4 RESERVED Nominal Value Bit 3 RESERVED Bit 2 RESERVED Bit 1 RESERVED Bit 0 Blocked (for test modes) - 158 - Publication Release Date: May, 2007 Revision 1.3 W681307 19. PACKAGE DIMENSIONS 100pin LQFP (14x14x1.4 mm footprint 2.0mm) HD D 7 5 7 6 51 A A2 A1 50 HE E 100 26 L 1 e b 25 c L1 θ Y Controlling Dimension : Millimeters Symbol A A1 A 2 b c D E e HD HE L L1 y θ 0 0.002 0.053 0.007 0.004 0.547 0.547 0.622 0.622 0.018 0.055 0.009 0.006 0.551 0.551 0.020 0.630 0.630 0.024 0.039 0.004 7 0 0.638 0.638 0.030 15.80 15.80 0.45 0.057 0.011 0.008 0.556 0.556 Dimension in inch Min Nom Max 0.063 Dimension in mm Min Nom Max 1.60 0.05 1.35 0.17 0.10 13.90 13.90 1.40 0.22 0.15 14.00 14.00 0.50 16.00 16.00 0.60 1.00 1.45 0.27 0.20 14.10 14.10 16.20 16.20 0.75 0.10 7 - 159 - Publication Release Date: May, 2007 Revision 1.3 W681307 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 160 - Publication Release Date: May, 2007 Revision 1.3