W681360W

W681360 3V SINGLE-CHANNEL 13-BIT LINEAR VOICE-BAND CODEC Data Sheet -1- Publication Release Date: September 2005 Revision A.2 W681360 1. GENERAL DESCRIPTION The W681360 is a general-purpose single channel 13–bit linear PCM CODEC with 2s complement data format. It operates from a single +3V power supply and is available in 20-pin SOG(SOP), SSOP and TSSOP package options. The primary function of the device is the digitization and reconstruction of voice signals, including the band limiting and smoothing required for PCM systems. The W681360 performance is specified over the industrial temperature range of –40°C to +85°C. The W681360 includes an on-chip precision voltage reference. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The VAG reference pin allows for decoupling of the internal circuitry that generates the reference voltage to the VSS power supply ground, minimizing clock noise on the analog circuitry when external analog signals are referenced to VSS. The data transfer protocol supports both long-frame and short-frame, synchronous and asynchronous communications for PCM applications. The W681360 accepts eight master clock rates between 256kHz and 4.800MHz, and an on-chip pre-scaler automatically determines the division ratio for the required internal clock. An additional on-chip power amplifier is capable of driving 300Ω loads differentially up to a level of 3.544V peak-to-peak. For fast evaluation a development kit (W681360DK) is available. For fast prototyping purposes a low-cost evaluation board (W681360ES) is also available. Applications • VoIP, Voice over Networks equipment • Digital telephone and communication systems • Wireless Voice devices • DECT/Digital Cordless phones • Broadband Access Equipment • Bluetooth Headsets • Fiber-to-curb equipment • Enterprise phones • Digital Voice Recorders 2. FEATURES • • • • • • • • • • • • Single +3V power supply (2.7V to 5.25V) Typical power dissipation: 9.8mW Standby power dissipation: 3µW Power-Down dissipation: 0.09µW Fully-differential analog circuit design for low noise 13-bit linear A/D & D/A conversions with 2s complement data format CODEC A/D and D/A filtering compliant with ITU G.712 Eight master clock rates of 256kHz to 4.800 MHz 256KHz – 4.8MHz bit clock rates on the serial PCM port On-chip precision reference of 0.886 V for a -5 dBm TLP at 600 Ω (436mVRMS) Programmable receive gain: 0 to –21dB in 3dB steps Industrial temp. range (–40°C to +85°C) 20-pin SOG (SOP), SSOP and TSSOP as well as a QFN-32L package Pb-Free / RoHS package options available -2- Publication Release Date: September 2005 Revision A2 W681360 3. BLOCK DIAGRAM Transmit Receive PCM PCM Interface Interface BCLKR FSR PCMR BCLKT FST PCMT PAO+ PAOPAI G.712 CODEC ROAO AI+ AIHB 256 kHz MCLK 256 256 kHz 512 kHz 1536 kHz 1544 kHz 2048 kHz 2560 kHz 4096 kHz 4800 kHz Voltage reference VAG VAGREF Pre-scaler 8 kHz Power Conditioning VDD PUI VSS -3- Publication Release Date: September 2005 Revision A.2 W681360 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM............................................................................................................................... 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION............................................................................................................ 8 7.1. Transmit Path................................................................................................................................ 8 7.1.1 Input Operational Amplifier Gain ............................................................................................. 9 7.2. Receive Path............................................................................................................................... 10 7.2.1. Receive Gain Adjust Mode................................................................................................... 11 7.3. Power Management.................................................................................................................... 11 7.3.1. Analog and Digital Supply .................................................................................................... 11 7.3.2. Analog Ground Reference Bypass ...................................................................................... 11 7.3.3. Analog Ground Reference Voltage Output .......................................................................... 11 7.4. PCM Interface ............................................................................................................................. 12 7.4.1. Long Frame Sync................................................................................................................. 12 7.4.2. Short Frame Sync ................................................................................................................ 12 7.4.3. Special 16-bit Receive Modes.............................................................................................. 13 7.4.3.1. Sign-Extended Mode Timing............................................................................................. 13 7.4.3.2. Receive Gain Adjust Mode Timing.................................................................................... 13 7.4.4. System Timing ..................................................................................................................... 14 7.5. On-Chip Power Amplifier ............................................................................................................ 14 8. TIMING DIAGRAMS.......................................................................................................................... 15 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20 9.1. Absolute Maximum Ratings ........................................................................................................ 20 9.2. Operating Conditions .................................................................................................................. 20 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21 10.1. General Parameters ................................................................................................................. 21 10.2. Analog Signal Level and Gain Parameters............................................................................... 22 10.3. Analog Distortion and Noise Parameters ................................................................................. 23 10.4. Analog Input and Output Amplifier Parameters ........................................................................ 24 10.5. Digital I/O .................................................................................................................................. 26 10.5.1. PCM Codes for Zero and Full Scale .................................................................................. 26 10.5.2. PCM Codes for 1kHz Digital Milliwatt ................................................................................ 26 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 27 12. PACKAGE DRAWING AND DIMENSIONS .................................................................................... 28 12.1. 20L SOG (SOP)-300mil ............................................................................................................ 28 12.2. 20L SSOP-209 mil .................................................................................................................... 29 12.3. 20L TSSOP - 4.4X6.5mm ......................................................................................................... 30 12.3. QFN-32L ................................................................................................................................... 31 -4- Publication Release Date: September 2005 Revision A.2 W681360 13. ORDERING INFORMATION........................................................................................................... 32 14. VERSION HISTORY ....................................................................................................................... 33 -5- Publication Release Date: September 2005 Revision A.2 W681360 5. PIN CONFIGURATION VREF ROPAI PAOPAO+ VDD FSR PCMR BCLKR PUI 1 2 3 4 5 6 7 8 9 10 20 19 18 17 W681360 SINGLE CHANNEL CODEC 16 15 14 13 12 11 VAG AI+ AIAO HB VSS FST PCMT BCLKT MCLK SOG, SSOP,TSSOP VREF VAG NC 32 31 RO- 1 PAI PAO2 3 NC 30 29 28 27 26 25 NC 24 AI23 AO 22 HB 21 NC 20 VSS 19 FST 18 NC 17 PCMT NC 4 PAO+ 5 VDD FSR 6 7 PCMR 8 BCLKR 9 10 NC 11 12 PUI NC 13 14 MCLK NC 15 16 BCLKT NC QFN-32L NC -6- Publication Release Date: September 2005 Revision A.2 AI+ NC W681360 6. PIN DESCRIPTION Pin Name VREF Pin No. nonQFN QFN Functionality This pin is used to bypass the on–chip VDD/2 voltage reference for the VAG output pin. This pin should be bypassed to VSS with a 0.1μF ceramic capacitor using short, low inductance traces. The VREF pin is only used for generating the reference voltage for the VAG pin. Nothing is to be connected to this pin except the bypass capacitor. Inverting output of the receive smoothing filter. This pin can typically drive a 2kΩ load to 0.886VPEAK referenced to analog ground. Inverting input to the power amplifier. The non-inverting input is tied internally to VAG voltage. Inverting power amplifier output. The PAO- and PAO+ can drive a 300Ω load differentially to 1.772VPEAK. Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300Ω load differentially to 1.772VPEAK. Power supply. Should be decoupled to VSS with a 0.1μF ceramic capacitor. 8kHz Frame Sync input for the PCM receive section. FSR can be asynchronous to FST in either Long Frame Sync or Short Frame Sync mode. PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins. PCM receive bit clock input pin. Can accept any bit clock frequency from 256 to 4800kHz. When not clocked it can be used to select the 16 sign-bit extended synchronous mode (BCLKR=0) or the receive gain adjust synchronous mode (BCLKR=1) Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS, the part is powered down. System master clock input. Possible input frequencies are 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz & 4800kHz. For performance reasons, it is recommended that MCLK be synchronous and aligned to the FST signal. This is a requirement in the case of 256 and 512kHz frequencies. PCM transmit bit clock input pin. Can accept any bit clock frequency from 256 to 4800kHz. PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins. 8kHz transmit frame sync input. This pin synchronizes the transmit data bytes. This is the supply ground. This pin should be connected to 0V. High-pass Bypass. Determines if the transmit high-pass filter is used (HB=’0’) or bypassed (HB=’1’). When the high pass is bypassed the frequency response extends to DC. Analog output of the first gain stage in the transmit path. Inverting input of the first gain stage in the transmit path. Non-inverting input of the first gain stage in the transmit path. Mid-Supply analog ground pin, which supplies a VDD/2 volt reference voltage for allanalog signal processing. This pin should be decoupled to VSS with a 0.01μF capacitor. This pin becomes high impedance when the chip is powered down. 1 30 ROPAI PAOPAO+ VDD FSR PCMR BCLKR PUI MCLK 2 3 4 5 6 7 8 9 10 11 1 2 3 5 6 7 8 9 12 13 BCLKT PCMT FST VSS HB AO AIAI+ VAG 12 13 14 15 16 17 18 19 20 16 17 19 20 22 23 24 26 29 -7- Publication Release Date: September 2005 Revision A.2 W681360 7. FUNCTIONAL DESCRIPTION W681360 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC block diagram in Section 3 illustrates the main components of the W681360. The chip consists of a PCM interface, which can process long and short frame sync formats. The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. The calibration level for both the Analog to Digital Converter (ADC) and the Digital to Analog Converter (DAC) is referenced to μ-Law with the same bit voltage weighing about the zero crossing, resulting in the 0dBm0 calibration level 3.2dB below the peak sinusoidal level before clipping, Based on the reference voltage of 0.886V the calibration level is 0.436 Vrms or –5dBm at 600Ω. VAG + - + PAO+ PAOPAI 13 13 DATA Receive 13 bit linear DAC fC = 3400 Hz Smoothing Filter a High Pass Bypass Buffer1 Av=1 Smoothing Filter b RO- AO AIAI+ 13 DATA Transmit 13 bit linear ADC fC = 200 Hz High Pass Filter fC = 3400 Hz Anti-Aliasing Filter a + Anti-Aliasing Filter b FIGURE 7.1: THE W681360 SIGNAL PATH 7.1. Transmit Path The first stage of the A-to-D path of the CODEC is an analog input operational amplifier with externally configurable gain settings. A differential analog input may be applied to the Inputs AI+ and AI-. Alternately the input amplifier may be powered down and a single-ended input signal can be applied to either the AO pin or the AIpin. The input amplifier can be powered down by connecting the AI+ pin to either VDD or VSS which also determines whether AO or AI+ is selected as input according to -8- Publication Release Date: September 2005 Revision A.2 W681360 Table 7.1. When the input operational amplifier is powered down the AO pin becomes high input impedance. TABLE 7.1: INPUT AMPLIFIER MODES OF OPERATION AI+ (Pin 19) VDD 1.2 to VDD-1.2 VSS Input Amplifier Powered Down Powered Up Powered Down Input AO (Pin 17) AI+, AI- (Pins 19, 18) AI- (Pin 18) When the input amplifier is powered down, the input signal at AO or AI- should be referenced to the analog ground voltage VAG. The output of the input operational amplifier is first fed through a low-pass filter to prevent aliasing at the switched capacitor 3.4kHz low pass filter. Subsequently the 3.4kHz switched capacitor low pass filter bandlimits the input signals well below 4kHz. Signals above 4kHz would be aliased at the sampling rate of 8kHz. A high pass filter with a 200Hz cut-off frequency prevents DC coupling. All filters are designed according to the G.712 ITU-T specification. The high-pass filter may be bypassed depending on the logic level on the HB pin. If the high pass is removed the frequency response of the device extends down to DC. After filtering the signal is digitized as a 13-bit linear PCM code and fed to the PCM interface for serial transmission at the sample rate supplied by the external frame sync FST. 7.1.1 Input Operational Amplifier Gain The gain of the input operational amplifier can be adjusted using external resistors. For single-ended input operation the gain is given by a simple resistive ratio. FIGURE 7.2: INPUT OPERATIONAL AMPLIFIER GAIN – SINGLE-ENDED INPUT Ro AO AI+ AI+ Ri Vin VAG Gin = Ro/Ri For differential input operation the external resistor network is more complex but the gain is expressed in the same way. Of course, a differential input also has an inherent 6dB advantage over a corresponding single-ended input. -9- Publication Release Date: September 2005 Revision A.2 W681360 Ro AO AI+ AI+ Ri Ri VinVin+ Gin = Ro/Ri Ro VAG FIGURE 7.3: INPUT OPERATIONAL AMPLIFIER GAIN – DIFFERENTIAL INPUT The gain of the operational amplifier will be typically be set to 30dB for microphone interface circuits. However the gain may be used for more than 30dB but this will require a compact layout with minimal trace lengths and good isolation from noise sources. It is also recommended that the layout be as symmetrical as possible as imbalances work against the noise canceling advantages of the differential design. 7.2. Receive Path The 13-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the 13-bit linear DAC and converted to analog samples. The analog samples are filtered by a low-pass smoothing filter with a 3.4kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO-. The output may be also be attenuated when the device is in the receive path adjust mode. If the device is operated half–channel with the FST pin clocking and FSR pin held LOW, the receive filter input will be connected to the VAG voltage. This minimizes transients at the RO– pin when full–channel operation is resumed by clocking the FSR pin. The RO- output can be externally connected to the PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external resistors various gain settings of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDD. The bias voltage and signal reference of the PAO+ & PAO– outputs is the VAG pin. The VAG pin cannot source or sink as much current as these pins, and therefore low impedance loads must be placed between PAO+ and PAO–. The PAO+ and PAO– differential drivers are also capable of driving a 100Ω resistive load or a 100nF piezoelectric transducer in series with a 20Ω resister with a small increase in distortion. These drivers may be used to drive resistive loads of 32Ω when the gain of PAO– is set to 1/4 or less. - 10 - Publication Release Date: September 2005 Revision A.2 W681360 7.2.1. Receive Gain Adjust Mode The W681360 can be put in the receive path adjust mode by applying a logic “1” to the BCLKR pin while all other clocks are clocked normally. The device is then in a position to read 16-bits of data, with three additional coefficient bits an addend to the 13-bit digital voice data. These three coefficients are used to program a receive path attenuation, thereby allowing the receive signal to be attenuated according to the values in the following table. If the feature is not used the default value is 0dB. TABLE 7.2: ATTENUATION COEFFICIENT RELATIONSHIP IN RECEIVE GAIN ADJUST MODE Coefficient 000 001 010 011 100 101 110 111 Attenuation (dB) 0 3 6 9 12 15 18 21 7.3. POWER MANAGEMENT 7.3.1. Analog and Digital Supply The power supply for the analog and digital parts of the W681360 must be 2.7V to 5.25V. This supply voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. 7.3.2. Analog Ground Reference Bypass The system has an internal precision voltage reference which generates the VDD/2 mid-supply analog ground voltage. This voltage needs to be decoupled to VSS at the VREF pin through a 0.1 μF ceramic capacitor. 7.3.3. Analog Ground Reference Voltage Output The analog ground reference voltage is available for external reference at the VAG pin. This voltage needs to be decoupled to VSS through a 0.01 μF ceramic capacitor. The analog ground reference voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing. - 11 - Publication Release Date: September 2005 Revision A.2 W681360 7.4. PCM INTERFACE The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 256kHz to 4.800 MHz clock and connecting the FSR or FST pin to the 8kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal. Long Frame Sync is recognized when the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. Short Frame Sync Mode is recognized when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. 7.4.1. Long Frame Sync The device recognizes a Long Frame Sync when the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 13-bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. Long Frame Sync mode is illustrated below. More detailed timing information can be found in the interface timing section. BCLKT (BCLKR) FST (FSR) PCMT PCMR don't care 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 13 12 13 don't care Long Frame Sync (Transmit and Receive Have Individual Clocking) FIGURE 7.4: LONG FRAME SYNC PCM MODE 7.4.2. Short Frame Sync The W681360 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the bit-clock, the W681360 starts clocking out the data on the PCMT pin, which will also change from high to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway through the LSB. The Short Frame Sync operation of the W681360 is based on a 13-bit data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. Short Frame Sync mode is illustrated below. More detailed timing information can be found in the interface timing section. - 12 - Publication Release Date: September 2005 Revision A.2 W681360 BCLKT (BCLKR) FST (FSR) PCMT PCMR don't care 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 13 12 13 don't care Short Frame Sync (Transmit and Receive Have Individual Clocking) FIGURE 7.5: SHORT FRAME SYNC PCM MODE 7.4.3. Special 16-bit Receive Modes 7.4.3.1. Sign-Extended Mode Timing The Sign-bit extended mode is entered by applying a logic “0” to the BCLKR pin while all other clocks are clocked normally. In standard 13-bit mode the first bit is the sign bit. In this mode the device transmits and receives 16-bit data where the sign bit is extended to the first four data bits. The PCM timing for this mode is illustrated below. BCLKT (BCLKR) FST (FSR) SHORT OR LONG FRAME SYNC PCMT PCMR don't care 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 13 12 13 14 14 15 16 15 16 don't care don't care Sign-Extended (BCLKR=0) Transmit and Receive both use BCLKT, and the first four data bits are the sign bit. FST may occur at a different time than FSR FIGURE 7.6: SIGN EXTENDED MODE 7.4.3.2. Receive Gain Adjust Mode Timing The Receive Path Adjust Mode is entered by applying a logic “1” to the BCLKR pin while all other clocks are clocked normally. In this mode the device receives 16-bit data where the last three bits are coefficients to program the Receive Gain Adjust Attenuation described above. The PCM timing for this mode is illustrated below. - 13 - Publication Release Date: September 2005 Revision A.2 W681360 BCLKT (BCLKR) FST (FSR) SHORT O R LONG FRAM E SYNC PCMT PCMR don't care 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 13 12 13 14 15 16 don't care don't care R eceive Gain Adjust (BCLKR=1) Transm it and Receive both use BCLKT. FST m ay occur at a different tim e than FSR. Bits 14, 15, and 16, clocked into PCMR, are used for attenuation control for the receive analog output. FIGURE 7.7: RECEIVE GAIN ADJUST TIMING MODE 7.4.4. System Timing The system can work at 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz & 4800kHz master clock rates. The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256kHz and 8kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the division ratio accordingly. If both Frame Syncs are LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W681360 will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the transmit Frame Sync pulse needs to be present. It will take two transmit Frame Sync cycles before the pin PCMT becomes low impedance. 7.5. ON-CHIP POWER AMPLIFIER The on-chip power amplifier is typically used to drive an external loudspeaker. The inverting input to the power amplifier is available at pin PAI. The non-inverting input is tied internally to VAG. The inverting output PAO– is used to provide a feedback signal to the PAI pin to set the gain of the power amplifier outputs (PAO+ and PAO-). These push–pull outputs are capable of driving a 300Ω load to 1.772 VPEAK. Connecting PAI to VDD will power down the power driver amplifiers and the PAO+ and PAO– outputs will be high impedance. - 14 - Publication Release Date: September 2005 Revision A.2 W681360 8. TIMING DIAGRAMS TFTRHM MCLK TMCKH TMCKL TBCK TFTRSM TMCK TRISE TFALL BCLKT TFTRS TFTRH TFTFH TFS TFSL FST TFDTD PCMT MSB BCLKR (BCLKT) TBCK LSB TFDTD TBDTD THID THID TBCKH TBCKL TFRRS TFRRH TFRFH TBCKH TBCKL FSR TDRS PCMR MSB TDRH LSB FIGURE 8.1: LONG FRAME SYNC PCM TIMING NOTE: The Data is clocked out on the rising edge of BCLK. The Data is clocked in on the falling edge of BCLK. - 15 - Publication Release Date: September 2005 Revision A.2 W681360 TABLE 8.1: LONG FRAME SYNC PCM TIMING PARAMETERS SYMBOL 1/TFS TFSL 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFDTD TBDTD THID DESCRIPTION FST, FSR Frequency FST / FSR Minimum LOW Width 1 BCLKT, BCLKR Frequency 1 BCLKT, BCLKR HIGH Pulse Width BCLKT, BCLKR LOW Pulse Width BCLKT Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT Falling edge Setup Time BCLKT Falling Edge to FST Falling Edge Hold Time The later of BCLKT rising edge, or FST rising edge to first valid PCMT Bit Delay Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the Later of FST Falling Edge, or BCLKT Falling Edge of last PCMT Bit to PCMT Output High Impedance BCLKR Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR Falling edge Setup Time BCLKR Falling Edge to FSR Falling Edge Hold Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge MIN --TBCK 256 50 50 20 80 50 ----10 TYP 8 ------------------MAX --4800 ----------60 60 60 UNIT kHz sec kHz ns ns ns ns ns ns ns ns TFRRH TFRRS TFRFH TDRS TDRH 20 80 50 1 50 ----------- ----------- ns ns ns ns ns 1 TFSL must be at least ≥ TBCK - 16 - Publication Release Date: September 2005 Revision A.2 W681360 TFTRHM MCLK TFTRSM TMCK TRISE TFALL TMCKH TMCKL TBCK BCLKT TFTRS TFTRH TBCKH TFTFS TFTFH TFS TBCKL FST TBDTD PCMT MSB BCLKR (BCLKT) TBCK LSB TBDTD THID TFRRS TFRRH TFRFH FSR TFRFS TBCKH TBCKL TDRS PCMR MSB TDRH LSB FIGURE 8.2: SHORT FRAME SYNC PCM TIMING - 17 - Publication Release Date: September 2005 Revision A.2 W681360 TABLE 8.2: SHORT FRAME SYNC PCM TIMING PARAMETERS SYMBOL 1/TFS 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFTFS TBDTD THID TFRRH TFRRS TFRFH TFRFS TDRS TDRH DESCRIPTION FST, FSR Frequency BCLKT, BCLKR Frequency BCLKT, BCLKR HIGH Pulse Width BCLKT, BCLKR LOW Pulse Width BCLKT Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT Falling edge Setup Time BCLKT Falling Edge to FST Falling Edge Hold Time FST Falling Edge to BCLKT Falling Edge Setup Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from BCLKT Falling Edge at last PCMT bit (LSB) to PCMT Output High Impedance BCLKR Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR Falling edge Setup Time BCLKR Falling Edge to FSR Falling Edge Hold Time FSR Falling Edge to BCLKR Falling Edge Setup Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge MIN --256 50 50 20 80 50 50 10 10 20 80 50 50 1 50 TYP 8 ------------------------------MAX --4800 ------------60 60 ------------UNIT kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns - 18 - Publication Release Date: September 2005 Revision A.2 W681360 TABLE 8.3: GENERAL PCM TIMING PARAMETERS SYMBOL 1/TMCK DESCRIPTION Master Clock Frequency MIN --TYP 256 512 1536 1544 2048 2560 4096 4800 ------------MAX --UNIT kHz TMCKH / TMCK TMCKH TMCKL TFTRHM TFTRSM TRISE TFALL MCLK Duty Cycle for 256kHz Operation Minimum Pulse Width HIGH for MCLK(512kHz or Higher) Minimum Pulse Width LOW for MCLK (512kHz or Higher) MCLK falling Edge to FST Rising Edge Hold Time FST Rising Edge to MCLK Falling edge Setup Time Rise Time for All Digital Signals Fall Time for All Digital Signals 45% 50 50 50 50 ----- 55% --------50 50 ns ns ns ns ns ns - 19 - Publication Release Date: September 2005 Revision A.2 W681360 9. ABSOLUTE MAXIMUM RATINGS 9.1. ABSOLUTE MAXIMUM RATINGS Condition Junction temperature Storage temperature range Voltage applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) VDD - VSS 150 C -650C to +1500C (VSS - 0.3V) to (VDD + 0.3V) (VSS – 1.0V) to (VDD + 1.0V) -0.5V to +6V 0 Value 1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. 9.2. OPERATING CONDITIONS Condition Industrial operating temperature Supply voltage (VDD) Ground voltage (VSS) Value -400C to +850C +2.7V to +5.25V 0V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. - 20 - Publication Release Date: September 2005 Revision A.2 W681360 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS VDD=2.7V – 3.6V; VSS=0V; TA=-40°C to +85°C; Symbol VIL VIH VOL VOH IDD ISB IPD IIL IOL CIN COUT 1. 2. Parameters Input LOW Voltage Input HIGH Voltage PCMT Output LOW Voltage PCMT Output HIGH Voltage VDD Current (Operating) - ADC + DAC VDD Current (Standby) VDD Current (Power Down) Input Leakage Current PCMT Output Leakage Current Digital Input Capacitance PCMT Output Capacitance Typical values: TA = 25°C , VDD = 3.0 V Conditions Min (2) Typ (1) Max (2) Units V V 0.6 2.2 IOL = 1.6 mA IOL = -1.6 mA No Load FST&FSR =Vss ; PUI=VDD (3) PUI= Vss (3) 0.4 VDD–0.5 3.25 1 0.03 -10 -10 4.7 100 10 +10 +10 10 V V mA μA μA μA μA pF pF VSS