W682310

ADVANCED W682510/W682310 DUAL-CHANNEL VOICEBAND CODECS -1- Publication Release Date: April 2005 Revision A10 W682510/W682310 1. GENERAL DESCRIPTION The W682510 and W682310 are general-purpose dual channel PCM CODECs with pin-selectable μLaw or A-Law companding. The device is compliant with the ITU G.712 specification. It operates from a single power supply (+5V for the W682510, +3V for the W682310) and is available in 20-pin PDIP (W682510 only), SSOP, and 24-pin SOP package options. Functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are compliant with ITU G.712 specification. The W682510 and W682310 performance is specified over the industrial temperature range of –40°C to +85°C. The W682510 includes an on-chip precision voltage reference and receive output buffer amplifiers, capable of driving 600Ω loads (line transformers.) The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The data transfer protocol supports either parallel or serial synchronous communications for PCM applications. The W682510 and W682310 have a build in PLL that eliminates the need for a master clock and automatically determines the division ratio for the required internal clock. For fast evaluation and prototyping purposes, the W682510DK & W682310DK development kits are available. 2. FEATURES • Single power supply o o • • • 4.5V to 5.5V (W682510) 2.7V to 3.8V (W682310) APPLICATIONS • • • • • • • • • • Digital Telephone Systems Central Office Equipment Switches, Routers) PABX/SOHO Systems Hands free system Speakerphone devices VoIP Terminals Enterprise Phones ISDN Terminals Analog line cards (Gateways, Typical power dissipation of 35 mW, power-down mode of 5 μW Fully-differential analog circuit design On-chip precision referenceo o W682510: 1.73V for a 0.8 dBm 0TLP at 600 Ω W682310: 1.41V reference for a 0TLP of –3.8 dBm into 1200 Ω PBX Systems (Gateways, Switches) • • • • Pin-selectable μ-Law and A-Law companding (compliant with ITU G.711) CODEC A/D and D/A filtering compliant with ITU G.712 Industrial temperature range (–40°C to +85°C) Three packages: 20-pin SSOP, 20-pin PDIP, and 24-pin SOP -2- W682510/W682310 3. BLOCK DIAGRAM DATA T1 PCMT1 PCMT2 FST BCLK FSR FSR PCMMS PCMR1 PCMR2 DATA R2 PC M Int erf ac PCM Interface DATA R1 μ/A-Law CODEC Filter 1 RO1 RO1 AO1 AI1 μ /A-Law DATA T2 μ/A-Law CODEC Filter 2 RO2 RO2 AO2 AI2 PLL PLL Voltage reference VREF Power Power Conditioning PUI V SSA V SSD V DD -3- Publication Release Date: April 2005 Revision A10 W682510/W682310 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION ................................................................................................................. 2 1. GENERAL DESCRIPTION ................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM ............................................................................................................................. 3 4. TABLE OF CONTENTS...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION ........................................................................................................... 8 7.1. Transmit Path............................................................................................................................. 8 7.1.1. AI1, AI2, AO1-, AO2-.............................................................................................................. 9 7.1.2. PCMT1 ................................................................................................................................... 9 7.1.3. PCMT2 ................................................................................................................................. 10 7.2. Receive Path ............................................................................................................................ 10 7.2.1. RO1, RO2 ............................................................................................................................ 10 7.2.2. PCMR1................................................................................................................................. 11 7.2.3. PCMR2................................................................................................................................. 11 7.3. Power Signals .......................................................................................................................... 11 7.3.1. VDD ........................................................................................................................................ 11 7.3.2. VSSA ...................................................................................................................................... 11 7.3.3. VSSD ...................................................................................................................................... 11 7.3.4. VREF ...................................................................................................................................... 12 7.3.5. PUI ....................................................................................................................................... 12 7.4. PCM Interface .......................................................................................................................... 12 7.4.1. μ/A-Law ................................................................................................................................ 12 7.4.2. BCLK .................................................................................................................................... 13 7.4.3. FSR ...................................................................................................................................... 13 7.4.4. FST....................................................................................................................................... 13 7.4.5. PCMMS ................................................................................................................................ 13 7.5. Power State Modes................................................................................................................. 13 7.5.1. Power Save Mode................................................................................................................ 13 7.5.2. Power Down Mode............................................................................................................... 14 7.5.3. Power Save/Down Output pin state ..................................................................................... 14 8. TIMING DIAGRAMS ......................................................................................................................... 15 9. ABSOLUTE MAXIMUM RATINGS................................................................................................... 19 -4- W682510/W682310 10. ELECTRICAL CHARACTERISTICS .............................................................................................. 20 10.1. General Parameters 10.2. General Parameters W682510 W682310 4.5V – 5.5V ............................................................... 20 2.7V – 3.8V ............................................................... 20 10.3. Analog Signal Level and Gain Parameters ....................................................................... 22 10.4. Analog Distortion and Noise Parameters .......................................................................... 24 10.5. Analog Input and Output Amplifier Parameters ................................................................ 25 10.6. Digital I/O ................................................................................................................................ 26 11. TYPICAL APPLICATION CIRCUIT................................................................................................ 29 12. PACKAGE DRAWING AND DIMENSIONS................................................................................... 31 12.1. 20L (PDIP) Plastic Dual Inline Package Dimensions (W682510 only) ......................... 31 12.2. 20L SSOP – 209 mil Shrink Small Outline Package Dimensions ................................. 32 12.3. 24 SOP – 300 mil .................................................................................................................. 33 13. ORDERING INFORMATION .......................................................................................................... 34 14. VERSION HISTORY ....................................................................................................................... 35 -5- Publication Release Date: April 2005 Revision A10 W682510/W682310 5. PIN CONFIGURATION VREF RO2 NC RO1 PUI PCMMS NC V DD VSSD FSR PCMR2 PCMR1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 W682510/ W682310 DUAL CHANNEL CODEC AI2 AO2 AO1 AI1 NC μ/ A-Law VSSA NC BCLK FST PCMT2 PCMT1 SOP VREF RO2 RO2 RO1 PUI PCMMS V DD VSSD FSR PCMR2 PCMR1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 W682510/ W682310 DUAL CHANNEL CODEC AI2 AO2 AO1 AI1 μ/A- Law VSSA BCLK FST PCMT2 PCMT1 PDIP (W682510 only), SSOP -6- W682510/W682310 6. PIN DESCRIPTION Pin Name VREF Pin # SSOP PDIP 1 Pin # SOP 1 Functionality (CH1 = Channel 1, CH2 = Channel 2) This pin is used to bypass the signal ground. It needs to be decoupled to VSS through a 0.1 μF ceramic decoupling capacitor. No external loads should be tied to this pin. CH2 Non-Inverting output of the receive smoothing filter. This pin can typically drive a 600 Ω load (W682510) or 1200 Ω load (W682310). CH1 Non-Inverting output of the receive smoothing filter. This pin can typically drive a 600 Ω load (W682510) or 1200 Ω load (W682310).. Power up input signal. When this pin is HIGH (tied to VDD) the part is powered up. When LOW (tied to VSS) the part is powered down. PCM mode select input (serial or parallel data interface) HIGH = Parallel, LOW = Serial Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor. This is the digital supply ground. This pin should be connected to 0V. 8 kHz Frame Sync input for the PCM receive section. It can also be connected to the FST pin when transmit and receive are synchronous operations. CH2 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLK pins. CH1 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLK pins. CH1 PCM output data transmit pin. The output data is synchronous with the FST and BCLK pins. CH2 PCM output data transmit pin. The output data is synchronous with the FST and BCLK pins. 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. PCM transmit and receive bit clock input pin for CH1 and CH2 transmit. This is the analog supply ground. This pin should be connected to 0V. Compander mode select pin. μ-Law companding is selected when this pin is LOW (tied to VSS.) A-Law companding is selected when pin is HIGH (tied to VDD.) CH1 Non-Inverting input of the first gain stage in the transmit path. CH1 Inverting analog output of the first gain stage in the transmit path. CH2 Inverting analog output of the first gain stage in the transmit path CH2 Non-Inverting input of the first gain stage in the transmit path. RO2 2 2 RO1 3 4 PUI PCMMS VDD VSSD FSR PCMR2 PCMR1 PCMT1 PCMT2 FST BCLK VSSA μ/A-Law 4 5 6 5 6 8 7 8 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 18 19 AI1 AO1AO2AI2 17 18 19 20 21 22 23 24 -7- Publication Release Date: April 2005 Revision A10 W682510/W682310 7. FUNCTIONAL DESCRIPTION W682510/W682310 is a single-rail, dual channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC includes two complete μ-Law and A-Law companders. The μ-Law and A-Law companders are designed to comply with the specifications of the ITU-T G.711 recommendation. The block diagram in section 3 shows the main components of the W682510/W682310. The chip consists of a PCM interface, which can process the data in parallel or serial formats. The PLL of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power-conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. 8 DATA R1 8 bit μ/A - Law DAC RO1 fC = 3400 Hz Smoothing Filter 1a + Smoothing Filter 1b RO2 fC = 3400 Hz Smoothing Filter 2a + Smoothing Filter 2b Buffer2 Av=1 AO1 fC = 200 Hz High Pass Filter fC = 3400 Hz Anti- Aliasing Anti-Aliasin Filter 1a + Anti- Aliasing Anti-Aliasin Filter 1b fC = 200 Hz High Pass Filter fC = 3400 Hz AntiAnti-Aliasing Anti-Aliasin Filter 2a + Anti- Aliasing Anti-Aliasin Filter 2b AO2 AI2 AI1 Buffer1 Av=1 μ/AControl 8 DATA R2 8 bit μ/A - Law DAC μ/AControl 8 DATA T1 8 bit μ/A - Law ADC μ/AControl 8 DATA T1 2 8 bit μ/A - Law ADC μ/AControl FIGURE 7.1: THE W682510 AND W682310 SIGNAL PATH 7.1. TRANSMIT PATH The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). The transmit amplifier output is the input to the encoder section. The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or A- -8- W682510/W682310 Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression format can be selected according to Table 7.1. TABLE 7.1: PIN-SELECTABLE COMPRESSION FORMAT μ/A-Law Pin VDD (HIGH) VSSA (LOW) Format A-Law μ-Law The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial or parallel transmission at the sample rate supplied by the external frame sync FST. 7.1.1. AI1, AI2, AO1-, AO2AI1 and AI2 are the transmit analog inputs for channels 1 and 2. AO1- and AO2- are the transmit level feedback for channels 1 and 2. AI1 and AI2 are inverting inputs for the Op-Amps. AO1- and AO2- are connected to the outputs of the Op-Amps and are used to set the level, as illustrated below. When AI1 and AI2 are not used, connect AI1 to AO1- and AI2 to AO2-. During power saving mode and power down mode, the AO1- and AO2- outputs are tied weakly to VSSA on the W682510 or are high impedance on the W682310 (See table on page 14). R2 C1 CH1 Analog Input R1 AO1AI1 + Gain=R2/R1 ≤ 10 R2 > 20 k Ohm R4 C2 CH2 Analog Input R3 AO2AI2 + Gain=R4/R3 ≤ 10 R4 > 20 k Ohm 7.1.2. PCMT1 The PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is sent from PCMT1 in a sequential order, synchronizing with the rising edge of the BCLK signal. The MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST. This output pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down. When serial operation is selected, this pin is configured to be the output of the serial multiplexed two channel PCM signal. A pull-up resistor must -9- Publication Release Date: April 2005 Revision A10 W682510/W682310 be connected to this pin , as it is an open drain output. This device is compatible with the ITU-T coding law and output coding format recommendation. TABLE 7.15: PCM CODES FOR ZERO AND FULL SCALE Level + Full Scale + Zero - Zero - Full Scale μ-Law Sign bit 1 1 0 0 Chord bits 000 111 111 000 Step bits 0000 1111 1111 0000 Sign Bit 1 1 0 0 A-Law Chord Bits 010 101 101 010 Step Bits 1010 0101 0101 1010 7.1.3. PCMT2 The PCM signal output for channel 2 when the parallel mode is selected. The PCM output signal is sent from PCMT2 in a sequential order, synchronized with the rising edge of the BCLK signal. The MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down. When the serial operation is selected, this pin is left open. A pull-up resistor must be connected to this pin , as it is an open drain output. This device is compatible with the ITU-T coding law and output coding format recommendation. 7.2. RECEIVE PATH The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO. 7.2.1. RO1, RO2 RO1 and RO2 are the receive analog outputs for channel 1 and channel 2. The output signal of the W682510 has an amplitude of 3.46 Vpp (2.03 Vpp for W682310) around the signal ground voltage (VREF). When the digital PCM signal of +3 dBm0 is presented to PCMR1 or PCMR2, it can drive a load of 600 Ohms or more at 5 V supply voltage for the W682510 and 1200 Ohms at 3V supply for the W682310. During power saving mode, these outputs are at the voltage level of VREF with a high impedance. These outputs have a feature that reduces audio “pop” noises when switching between active and inactive states and back. - 10 - W682510/W682310 7.2.2. PCMR1 The PCM signal input for channel 1 when in the parallel mode. D/A conversion is performed on the serial PCM signal input to this pin. The FSR signal, synchronous with the serial PCM signal, and the BCLK signal, processes the code. Then the analog output is output from the RO1 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted in on the falling edge of the BCLK signal. It is latched into the internal 8-bit register. The start of the PCM data (MSB) is synchronized with the rising edge of FSR. In the serial mode, this pin is not used and should be connected to GND (0V). 7.2.3. PCMR2 PCM signal input for channel 2 when the parallel mode is selected. D/A conversion is performed with the serial PCM signal input to this pin, the FSR signal, synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is output from the RO2 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSB) is identified at the rising edge of FSR. In the serial mode this pin is used for the two channel multiplexed PCM signal input. 7.3. POWER SIGNALS 7.3.1. VDD The power supply for the analog and digital parts of the W682510 must be 5V +/- 10% and 2.7V to 3.8V for the W682310. This supply voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. A power supply for an analog circuit in the system to which the device is applied should be used. A bypass capacitor of 0.1 µF to 1 µF with good high-frequency characteristics (Low ESR) and a capacitor of 10 µF to 20 µF should be connected between this pin and the VSSA pin if needed. 7.3.2. VSSA Ground for the analog signal circuits. This ground is separate from the digital signal ground. The VSSA pin must be connected to the VSSD pin on the printed circuit board to make a common ground. However, it’s advised to connect the PCB traces of these pins at the main supply hookup of the PCB and run the VSSA and VSSD traces separately to the device. 7.3.3. VSSD Ground for the digital signal circuits. This ground is separate from the analog signal ground. The VSSD pin must be connected to the VSSA pin on the printed circuit board to make a common ground. However, it’s advised to connect the PCB traces of these pins at the main supply hookup of the PCB and run the VSSA and VSSD traces separately to the device - 11 - Publication Release Date: April 2005 Revision A10 W682510/W682310 7.3.4. VREF This pin carries the signal ground voltage level and requires a bypass capacitor. A 0.1μF ceramic (with low ESR for good high frequency response) capacitor needs to be connected between the VSSA pin and the VREF pin. 7.3.5. PUI Power up input signal. When the PUI pin is set to logic “0” level, the CODEC will go into power down mode. 7.4. PCM INTERFACE The PCM interface is controlled by pins PCMMS, BCLK, FSR & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of operation of the interface are shown in Table 7.2. TABLE 7.2: PCM INTERFACE MODE SELECTIONS PCMMS VDD [HIGH] VSS [LOW] PCM Mode Parallel Mode Serial Mode Data Available CH1 data on PCMT1 & PCMR1 CH2 data on PCMT2 and PCMR2 (same timing as CH1) CH1 data followed by CH2 receive data on PCMR2 (total 16 bits) CH1 data followed by CH2 transmit data on PCMT1 (total 16 bits) 7.4.1. μ/A-Law This pin selects the desired companding law. The CODEC will operate in the μ-law when this pin is at a logic “0” level and in the A-law when at a logic “1” level. The CODEC operates μ-law if the pin is left open, since this pin is internally pulled down. TABLE 7.25: PIN-SELECTABLE COMPRESSION FORMAT μ/A-Law pin Format HIGH (VDD ) LOW (VSS), Floating A-Law μ-Law - 12 - W682510/W682310 7.4.2. BCLK This is the shift clock signal input for the PCMR1, PCMR2, PCMT1, and PCMT2 signals. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or 200 kHz. Setting this signal to a steady logic “1” or “0” sets both transmit and receive circuits to the power saving state. 7.4.3. FSR This is the receive synchronizing signal input. The required eight-bits of PCM data are selected from the PCM data signal to the PCMR1 and PCMR2 pins by the receive synchronizing signal. All timing signals in the receive section are synchronized by this synchronizing signal. This signal must be in phase with the BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics. This device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in the data sheet are not guaranteed. 7.4.4. FST The transmit synchronizing signal input. The PCM output signal from PCMT1 and PCMT2 is sent in synchronization with this transmit synchronizing signal. This FST signal triggers the PLL and synchronizes all timing signals of the transmit section. The synchronizing signal must be in phase with BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics. This device can operate in the range of 6 kHz to 9 kHz sample rates, but the electrical characteristics are not guaranteed. Setting this signal to logic HIGH or LOW drives both transmit and receive circuits to power saving state. 7.4.5. PCMMS The control signal for mode selection of the PCM input and output. When this signal is HIGH, the PCM input and output are in the parallel mode. The PCM data of CH1 and CH2 is input to PCMR1 and PCMR2, and output from PCMT1 and PCMT2, with the same timing. When this signal is at a LOW level, the PCM input and output are in the serial mode. The PCM data of CH1 and CH2 is input to PCMR2 and output from PCMT1 as two serial 8-bit bytes. 7.5. POWER STATE MODES 7.5.1. Power Save Mode In the power save mode, all internal analog circuits except the internal reference are powered down. The CODEC automatically enters the power save mode when the FST or BCLK signal is set to digital “1” or digital “0”; Upon power up with FST and BCLK signals present, it will take 2 to 10 milliseconds for the internal PLL to lock. In addition to the PLL lock-in time, the analog outputs will be set to the internal signal ground for 1 millisecond. This will avoid power up glitches at the outputs. The digital open drain outputs will remain at high impedance during this power up delay. Publication Release Date: April 2005 Revision A10 - 13 - W682510/W682310 7.5.2. Power Down Mode When the power up indicator pin, PUI, is set LOW all internal circuits will go into the power down state. It will take 2 to 10 milliseconds for the PLL to lock when operation is resumed with the FST and BCLK signals applied and PUI set HIGH. An additional 1-millisecond delay is used to set the analog outputs to the signal ground reference in order to avoid power up glitches. The digital open drain outputs will remain at high impedance during this power up delay. 7.5.3. Power Save/Down Output pin state The following table shows the states of the output pins in the power save or power down mode. TABLE 7.5: OUTPUT PIN STATES Product Name W682510 W682310 Output Pin AO1-, A02VSSA High Z RO1, RO2 Signal Ground Signal Ground - 14 - W682510/W682310 8. TIMING DIAGRAMS BCLK FST PCMT1 MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 D5 D4 D3 D2 D1 D0 Channel 1 Transmit PCM Data Channel 2 Transmit PCM Data Figure 8-1a. Transmit Side Serial Mode Timing (PCMMS=0) BCLK FSR PCMR2 MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 D5 D4 D3 D2 D1 D0 Channel 1 Receive PCM Data Channel 2 Receive PCM Data Figure 8-1b. Receive Side Serial Mode Timing (PCMMS=0) FIGURE 8.1: SERIAL MODE PCM TIMING BCLK FST PCMT1 PCMT2 MSB D6 D5 D4 D3 D2 D1 D0 Figure 8-2a. Transmit Side Parallel Mode Timing (PCMMS=1) BCLK FSR PCMR1 PCMR2 MSB D6 D5 D4 D3 D2 D1 D0 Figure 8-2b. Receive Side Parallel Mode Timing (PCMMS=1) FIGURE 8.2: PARALLEL MODE PCM TIMING - 15 - Publication Release Date: April 2005 Revision A10 W682510/W682310 BCLK FST FSR PCMT1 PCMR2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 D5 D4 Channel 1 PCM Data D3 D2 D1 D0 Channel 2 PCM Data Figure 8-3a. Burst Mode with Serial Timing (PCMMS=0) BCLK FST FSR PCMTx PCMRx MSB D6 D5 D4 D3 D2 D1 D0 Figure 8-3b. Burst Mode with Parallel Timing (PCMMS=1) 1 2 3 4 5 6 7 8 9 FIGURE 8.3: BURST MODE PCM TIMING - 16 - W682510/W682310 TABLE 8.1: PCM SYNCHRONIZATION PARAMETERS SYMBOL fFS tWS tj fBCLK DESCRIPTION FST, FSR frequency FST, FSR Pulse Width FST, FSR allowable jitter BCLK frequency MIN --1 0 TYP 8 ----MAX --7 500 UNIT KHz TBCLK nsec kHz 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 40 ----50 ----60 50 50 DC tIr tIf BCLK Duty Cycle FSR, FST, BCLK, PCMR1, PCMR2, PUI, PCMMS input rise time FSR, FST, BCLK, PCMR1, PCMR2, PUI, PCMMS input fall time % nsec nsec tIr TBCLK=1/fBCLK DC tIf BCLK FSR FST 1 tW S tj 2 3 4 5 TFS=1/fFS 6 7 8 FIGURE 8.4: PCM SYNCHRONIZATION PARAMETERS - 17 - Publication Release Date: April 2005 Revision A10 W682510/W682310 TABLE 8.2: PCM TIMING PARAMETERS SYMBOL tWS tXS tSX tSD tXD1 tXD2 tXD3 tRS tSR tDS tDH RTL CTL DESCRIPTION FST, FSR Pulse Width BCLK low to FST high setup time FST high to BCLK low hold time PCMT1, PCMT2 output delay; Cl = 100 pF PCMT1, PCMT2 output delay; Cl = 100 pF PCMT1, PCMT2 output delay; Cl = 100 pF PCMT1, PCMT2 output delay; Cl = 100 pF BCLK low to FSR high setup time FSR high to BCLK low hold time PCMR1, PCMR2 Data in setup time PCMR1, PCMR2 Data in hold time PCMT1, PCMT2 Pull-up resistor PCMT1, PCMT2 Load capacitance MIN TBCLK 100 100 20 20 20 20 100 100 100 100 500 --TYP --------------------------MAX 100 µ ----200 200 200 200 ----------100 UNIT sec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec Ohm pF tXS BCLK FST PCMT1 PCMT2 1 tSX tWS tSD 2 3 4 tXD2 5 6 7 8 9 tXD3 10 11 tXD1 MSB D6 D5 D4 D3 D2 D1 D0 Figure 8-5a. Transmit Timing tRS BCLK FSR PCMR1 PCMR2 1 tSR tWS 2 3 4 5 6 7 8 9 10 11 tDS tDH MSB D6 D5 D4 D3 D2 D1 D0 Figure 8-5b. Receive Timing FIGURE 8.5 PCM TIMING PARAMETERS - 18 - W682510/W682310 9. ABSOLUTE MAXIMUM RATINGS TABLE 9.1: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) Condition Junction temperature Storage temperature range Voltage Applied to any pin Voltage applied to any pin (Input current limited to +/-20 mA) Lead temperature (soldering VDD - VSS – 10 seconds) 150 C 0 Value -650C to +1500C (VSS - 0.3V) to (VDD + 0.3V) (VSS – 1.0V) to (VDD + 1.0V) 3000C -0.5V to +6V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Functional operation is not implied at these conditions. TABLE 9.2: OPERATING CONDITIONS (PACKAGED PARTS) Condition Industrial operating temperature Supply voltage (VDD) Supply voltage (VDD) Ground voltage (VSS) W682510 W682310 5V 3V 0 Value -40 C to +85 C +4.5V to +5.5V +2.7V to +3.8V 0V 0 - 19 - Publication Release Date: April 2005 Revision A10 W682510/W682310 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS W682510 4.5V – 5.5V Symbol VIL VIH VOL IDD ISB IPD IIL IIH IOL CIN COUT 1. 2. Parameters Input Low Voltage Input High Voltage PCMT1, PCMT2 Low Voltage Output Conditions Min (2) 0.0 2.2 Typ (1) Max (2) 0.8 VDD Units V V V mA μA μA μA μA μA pF pF Rpullup>500 Ω No Load, No Signal FST or BCLK =OFF; PUI=VDD PUI= Vss VSS