W742C816

Deleted: SA5505 Deleted: W742C811 W742E/C816 4-BIT MICROCONTROLLER Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATION ............................................................................................................... 5 PIN DESCRIPTION..................................................................................................................... 6 FUNCTIONAL DESCRIPTION.................................................................................................... 7 5.1 5.2 5.3 Program Counter (PC).................................................................................................... 7 Stack Register (STACK) ................................................................................................. 8 Program Memory (ROM) ................................................................................................ 8 5.3.1 5.3.2 ROM Page Register (ROMPR)......................................................................................... 9 ROM Addressing Mode .................................................................................................. 10 Architecture .................................................................................................................... 11 RAM Page Register (PAGE) .......................................................................................... 12 WR Page Register (WRP) .............................................................................................. 12 Data Bank Register (DBKRH, DBKRL)........................................................................... 13 RAM Addressing Mode................................................................................................... 14 5.4 Data Memory (RAM)..................................................................................................... 11 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 Accumulator (ACC) ....................................................................................................... 15 Arithmetic and Logic Unit (ALU) ................................................................................... 15 Main Oscillator .............................................................................................................. 16 Sub-oscillator ................................................................................................................ 16 Dividers ......................................................................................................................... 16 Dual-clock Operation .................................................................................................... 17 Watchdog Timer (WDT)................................................................................................ 18 Timer/Counter ............................................................................................................... 19 5.12.1 5.12.2 5.12.3 5.12.4 Timer 0 (TM0)............................................................................................................... 19 Timer 1 (TM1)............................................................................................................... 20 Mode Register 0 (MR0) ................................................................................................ 21 Mode Register 1 (MR1) ................................................................................................ 22 5.13 5.14 5.15 Interrupts....................................................................................................................... 22 Stop Mode Operation.................................................................................................... 24 5.14.1 5.15.1 5.15.2 Stop Mode Wake-up Enable Flag for RC and RD Port (SEF) ...................................... 24 Hold Mode Release Enable Flag (HEF, HEFD)............................................................ 26 Interrupt Enable Flag (IEF) ........................................................................................... 26 Hold Mode Operation.................................................................................................... 24 -1- Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 5.15.3 5.15.4 5.15.5 Port Enable Flag (PEF, P1EF) ..................................................................................... 27 Hold Mode Release Condition Flag (HCF, HCFD) ....................................................... 27 Event Flag (EVF, EVFD) .............................................................................................. 28 5.16 5.17 Reset Function.............................................................................................................. 29 Input/Output Ports RA, RB & P0................................................................................... 29 5.17.1 5.17.2 5.17.3 5.17.4 Port Mode 0 Register (PM0)......................................................................................... 30 Port Mode 1 Register (PM1)......................................................................................... 31 Port Mode 2 Register (PM2)......................................................................................... 31 Port Mode 6 Register (PM6)......................................................................................... 32 5.18 5.19 5.20 5.21 5.22 5.23 Serial I/O interface ........................................................................................................ 32 Input Ports RC .............................................................................................................. 35 5.19.1 5.20.1 Port Status Register 0 (PSR0)...................................................................................... 36 Port Status Register 1 (PSR1)...................................................................................... 37 Input Ports RD .............................................................................................................. 36 Output Port RE & RF .................................................................................................... 38 Input Port P1 ................................................................................................................. 38 DTMF Output Pin (DTMF) ............................................................................................ 38 5.23.1 5.23.2 DTMF Register ............................................................................................................. 39 Dual Tone Control Register (DTCR)............................................................................. 39 FSK Transmit Control Register (FSKC)........................................................................ 41 FSK Transmit Data Buffer (FSKB)................................................................................ 41 5.24 FSK Output ................................................................................................................... 40 5.24.1 5.24.2 5.25 5.26 MFP Output Pin (MFP) ................................................................................................. 41 LCD Controller/Driver ................................................................................................... 43 5.26.1 5.26.2 5.26.3 5.26.4 LCD RAM Addressing Method...................................................................................... 44 LCD Voltage and Contrast Adjusting ............................................................................ 44 SEG32 − SEG39 Using as DC Output (NMOS Open Drain Type) ............................... 46 The Output Waveforms for the LCD Driving Mode ....................................................... 46 6. 7. 8. 9. 10. 11. ABSOLUTE MAXIMUM RATINGS............................................................................................ 47 DC CHARACTERISTICS .......................................................................................................... 47 AC CHARACTERISTICS .......................................................................................................... 48 INSTRUCTION SET TABLE ..................................................................................................... 49 PACKAGE DIMENSIONS ......................................................................................................... 57 REVISION HISTORTY.............................................................................................................. 58 -2- Deleted: SA5505 Deleted: W742C811 W742E/C816 1. GENERAL DESCRIPTION The W742E/C816 [W742E 816 is EEPROM type, W742C816 is mask type] is a high-performance 4bit microcontroller (µC) that built in 640-dot LCD driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers in dual-clock operation, a 40 × 16 LCD driver, ten 4-bit I/O ports (including 2 output port for LED driving), multiple frequency output, one channel DTMF generator and FSK modulator of CCITT V.23 or Bellcore 202. There are also eleven interrupt sources and 16-level stack buffer. The W742E/C816 operates on very low current and has three power reduction modes, hold mode, stop mode and slow mode, which help to minimize power dissipation. 2. FEATURES • Operating voltage − 2.4V - 6.0V for mask type − 2.4V - 4.8V for EEPROM type • Dual-clock operation • Main oscillator − 3.58 MHz or 400 KHz can be selected by code option − Crystal or RC oscillator can be selected by code option • Sub-oscillator − Connect to 32.768 KHz crystal only • Memory − 32768(32K) x 16 bit program ROM (including 64K x 4 bit look-up table) − 5120(5K) x 4 bit data RAM (including 16 nibbles x 16 pages working registers) − 40 x 16 LCD data RAM • 40 input/output pins − Port for input only: 3 ports/12 pins − Input/output ports: 3 ports/12 pins − High sink current output port for LED driving: 2 port /8 pins − DC output port: 2 ports/ 8 pins (selected by code option) • Power-down mode − Hold mode: no operation (main oscillator and sub-oscillator still operate) − Stop mode: no operation (main oscillator and sub-oscillator are stopped) − Slow mode: main oscillator is stopped, system is operated by the sub-oscillator (32.768 KHz) -3- Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 • Eleven interrupt sources − Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1) − Seven external interrupts (RC.0 − 3, P1.2 ( INT0 ), Serial Port, P1.3 ( INT1 )) • LCD driver output − 40 segments x 16 commons − 1/8 or 1/16 duty (selected by code option) 1/5 bias driving mode − Clock source should be the sub-oscillator clock in the dual-clock operation mode − 8 level software LCD contrast adjusting − LCD operating voltage source could come from VDD or VLCD1 pin input • MFP output pin − Output is software controlled to generate modulating or non-modulating frequency − Works as frequency output specified by Timer 1 − Key tone generator • DTMF output pin − Output is one channel Dual Tone Multi-Frequency signal for dialing • FSK output − Output FSK signal of CCITT V.23 or Bellcore 202 by mask option • 8-bit Serial I/O Interface − 8-bit transmit/receive mode by internal or external clock source • Two built-in 14-bit frequency dividers − Divider0: the clock source is the main oscillator (FOSC) − Divider1: the clock source is the sub-oscillator (Fs) • Two built-in 8-bit programmable countdown timers − Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected − Timer 1: with auto-reload function and one of two internal clock frequencies (FOSC or FOSC/64 or Fs) can be selected (signal output through MFP pin) • Built-in 18/14-bit watchdog timer selectable for system reset, enable/disable by code option • 16-level stack buffer • Packaged in 100-pin QFP -4- Deleted: SA5505 Deleted: W742C811 W742E/C816 3. PIN CONFIGURATION S E G 3 0 S E G 2 9 S E G 2 8 S E G 2 7 S E G 2 6 S E G 2 5 S E G 2 4 S E G 2 3 S E G 2 2 S E G 2 1 S E G 2 0 S E G 1 9 S E G 1 8 S E G 1 7 S E G 1 6 S E G 1 5 S E G 1 4 S E G 1 3 S E G 1 2 S E G 1 1 SEG31 (K0.0) SEG32 (K0.1) SEG33 (K0.2) SEG34 (K0.3) SEG35 (K1.0) SEG36 (K1.1) SEG37 (K1.2) SEG38 (K1.3) SEG39 COM08 COM09 COM10 COM11 COM12 COM13 COM14 COM15 RA0 RA1 RA2 [Data_IO] RA3 RB0 RB1 RB2 RB3 MFP DTMF/FSK XOUT2 XIN2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 80 79 78 77 76 75 74 73 72 71 70 69 SEG10 SEG09 SEG08 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM00 COM01 COM02 COM03 COM04 COM05 COM06 COM07 VLCD1 CP CN P13 [m ode] P12 P11 P10 P03 P02 P01 P00 W 742E/C816 100-pin QFP 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 34 90 44 12 4 3 4 4 4 5 4 6 44 78 4 9 5 0 X I N 1 XRRR RRRRRRRRRRRRR / V OCCC CDD DDE E E E F F F F RD U0 1 2 301 2 3 0 1 2 3 0 1 2 3 ED T S 1 E T [Vpp] -5- Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 4. PIN DESCRIPTION SYMBOL XIN2 XOUT2 XIN1 XOUT1 RA0 − RA3 Data_IO RB0 − RB3 RC0 − RC3 RD0 − RD3 I/O I I I/O I O I O I/O FUNCTION Input pin for sub-oscillator. Connected to 32.768 KHz crystal only. Output pin for sub-oscillator with internal oscillation capacitor. Connected to 32.768 KHz crystal only. Input pin for main-oscillator. Connected to 3.58 MHz crystal or resistor to generate system clock. Output pin for main-oscillator. Connected to 3.58 MHz crystal or resistor to generate system clock. Input/Output port. Input/output mode specified by port mode 1 register (PM1). RA.3: Serial data input/output for EEPROM type Input/Output port. Input/output mode specified by port mode 2 register (PM2). Input port only. Each pin has an independent interrupt capability. Input port only. This port can release hold mode but can not occur interrupt service routine. Output port only. CMOS type with high sink current capacity for the LED application. Input/Output port. Input/output mode specified by port mode 6 register (PM6). P0.0 and P0.1 can be a serial I/O interface selected by SIR register. P0.0 indicates serial clock, P0.1indicates serial data. RE0 − RE3 RF0 − RF3 P00 − P03 O I/O P10 − P13 Mode I Input port only. P1.2 & P1.3 indicates hardware interrupt ( INT0 & INT1 ) P1.3: Mode select for EEPROM type Output pin only, default in low state. This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1). This pin can output dual-tone multi-frequency signal for dialing or FSK signal. System reset pin with internal pull-high resistor. VPP: supply programming voltage, without internal pull-high resistor for EEPROM type for avoiding high voltage programming damage MFP DTMF/FSK RES O O I VPP SEG0 − SEG31 O LCD segment output pins. -6- Deleted: SA5505 Deleted: W742C811 W742E/C816 Pin Description, continued SYMBOL COM0 − COM15 SEG32 − SEG39 CP, CN VLCD1 VDD VSS I/O O O I I I I FUNCTION LCD common signal output pins. The LCD alternating frequency can be selected by code option. LCD segment output pins or DC N-MOS open drain output pins selected by code option. Connection terminals for LCD voltage doubler capacitor (0.1 µF), tuning the capacitor value can reduce the LCD driving current. LCD supply voltage input or connect capacitor (0.1µF) to ground when enable internal pump LCD voltage Positive power supply (+). Negative power supply (-). (K00 − K03, K10 − K13) 5. FUNCTIONAL DESCRIPTION 5.1 Program Counter (PC) Organized as an 15-bit binary counter (PC0 to PC14), the program counter generates the addresses of the 32768(32K) × 16 on-chip ROM containing the program instruction words. When the interrupt or initial reset conditions are to be executed, the corresponding address will be loaded into the program counter directly. From address 0000h to 0023h are reserved for reset and interrupt service routine. The format used is shown below. Table 1 Vector address and interrupt priority ITEM Initial Reset INT 0 (Divider0) INT 1 (Timer 0) INT 2 (Port RC) INT 3 (Port 1.2 ( INT0 )) INT 4 (Divider1) INT 5 (Serial I/O or FSK baud rate) INT 6 (Port1.3 ( INT1 )) INT 7 (Timer 1) Code Start ADDRESS 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H INTERRUPT PRIORITY 1st 2nd 3rd 4th 5th 6th 7th 8th - -7- Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 5.2 Stack Register (STACK) The stack register is organized as 53 bits x 16 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter (PC), TAB0, TAB1, TAB2, TAB3, DBKRL, DBKRH, WRP, ROMPR, PAGE, ACC and CF will be pushed into the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN (only restore the program counter) and RTN #I instruction could pop the contents of the stack register into the corresponding registers. It can restore part of contents of stack buffer. When the stack register is pushed over the 16th level, the contents of the first level will be overwritten. In the other words, the stack register is always 16 levels deep. The bit definition of #I is listed below. I = 0000 0000 Bit0 = 1 Bit1 = 1 Bit2 = 1 Bit3 = 1 Bit4 = 1 Bit5 = 1 Bit6 = 1 Pop PC from stack only Pop TAB0, TAB1, TAB2, TAB3 from stack Pop DBKRL, DBKRH from stack Pop WRP from stack Pop ROMPR from stack Pop PAGE from stack Pop ACC from stack Pop CF from stack 5.3 Program Memory (ROM) The read-only memory (ROM) is used to store program codes or the look-up table that can be arranged up to 65536(64K) × 4 bits. The program ROM is divided into sixteen pages; the size of each page is 2048(2K) × 16 bits. So the total ROM size is 32768(32K) × 16 bits. Before the jump or subroutine call instructions are to be executed, the destination ROM page register (ROMPR) must be determined firstly. The ROM page can be selected by executing the MOV ROMPR, #I or MOV ROMPR, RAM instructions. But the branch decision instructions (e.g. JB0, SKB0, JZ, JC, ...) must jump into the same ROM page. The look-up table area is allocated in lower half part of ROM (PC: 4000H to 7FFFH). Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 65536(64K) elements. It uses instructions MOV TAB0, R MOV TAB1, R MOV TAB2, R MOV TAB3, R to determine the look-up table element address. The look-up table address is 4 times PC counter, and the offset value is 4000H. Instruction MOVC R is used to read the look-up table content and save data into the RAM. The organization of the program memory is shown in Figure 5-1. -8- Deleted: SA5505 Deleted: W742C811 W742E/C816 16 bits 0000H : 07FFH 0800H : 0FFFH 1000H : 17FFH 1800H : 1FFFH 2000H : 27FFH 2800H : 2FFFH 3000H : 37FFH 3800H : 3FFFH Page 0 Page 1 4000H : 47FFH 4800H : 4FFFH 5000H : 57FFH 5800H : 5FFFH 6000H : 67FFH 6800H : 6FFFH 7000H : 77FFH 7800H : 7FFFH 16 bits Page 8 : : Page A : Page B : Page C : : Page E : : 16384 * 16 bits Page F Page D Page 9 Each element (4 bits) of the look-up table Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 16384 * 16 bits All Program memory can be used to store instruction code, but the look-up table just can be stored in the lower half ROM (4000H - 7FFFH). Figure 5-1 Program Memory Organization 5.3.1 ROM Page Register (ROMPR) The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 ROMPR Note: W means write only. 2 R/W 1 R/W 0 R/W R/W Bit 3, Bit 2, Bit 1, Bit 0 ROM page bits: 0000 = ROM page 0 (0000H − 07FFH) 0001 = ROM page 1 (0800H − 0FFFH) 0010 = ROM page 2 (1000H − 17FFH) 0011 = ROM page 3 (1800H − 1FFFH) 0100 = ROM page 4 (2000H − 27FFH) 0101 = ROM page 5 (2800H − 2FFFH) 1000 = ROM page 8 (4000H − 47FFH) 1001 = ROM page 9 (4800H − 4FFFH) 1010 = ROM page A (5000H − 57FFH) 1011 = ROM page B (5800H − 5FFFH) 1100 = ROM page C (6000H − 67FFH) 1101 = ROM page D (6800H − 6FFFH) -9- Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 0110 = ROM page 6 (3000H − 37FFH) 0111 = ROM page 7 (3800H − 3FFFH) 1110 = ROM page E (7000H − 77FFH) 1111 = ROM page F (7800H − 7FFFH) 5.3.2 ROM Addressing Mode 1. Direct Addressing Bit 14-0 PC 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 2. Far Jump or Call Bit 14-0 PC 14 P3 13 P2 12 11 10 9 8 7 6 5 4 3 2 1 0 P1 P0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 P0-3 is ROM page register(ROMPR) Example: MOV ROMPR, #I JMP or MOV CALL 3. Conditional JMP Bit 14-0 PC 14 0 13 0 12 0 11 0 10 9 8 7 6 5 4 3 2 1 0 Label_A ROMPR, #I SUB_A A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 jmp into the same page Example: JB0 JB1 JB2 JB3 JZ JNZ JC JNC Lable_A0 Lable_A1 Lable_A2 Lable_A3 Label_Az Label_Anz Label_Ac Label_Anc - 10 - Deleted: SA5505 Deleted: W742C811 W742E/C816 4. Look-up Table Bit 15-0 15 14 13 12 11 10 9 8 7 6 543 21 0 (PC-4000H)*4 TA33 TA32 TA31 TA30 TA23 TA22 TA21 TA20 TA13 TA12 TA11 TA10 TA03 TA02 TA01 TA00 Look-up table address = (PC address - 4000H) *4 Example: TABLE TAB_addr ; Real_TAB_addr (PC value) = TAB_addr/4 + 4000H 00h, 01h, 02h, 0Ah, 0Ch, 0Dh, 0Eh, 0Fh ENDT MOV MOV MOV MOV MOVC TAB0, TAB_addr_B0_3 ; set Look-up table address TAB1, TAB_addr_B4_7 TAB2, TAB_addr_B8_11 TAB3, TAB_addr_B12_15 RAM ; get Look-up table value to RAM 5.4 Data Memory (RAM) 5.4.1 Architecture The static data memory (RAM) used to store data is arranged up to 5120(5K) × 4 bits. The data RAM is divided into 40 banks; each bank has 128 × 4 bits. Executing the MOV DBKRL, WR, MOV DBKRH, WR or MOV DBKRL, #I, MOV DBKRH, #I instructions can determine which data bank is used. The data memory can be accessed directly or indirectly and the data bank register has to be confirmed firstly. In the indirect addressing mode, each data bank will be divided into eight pages. The RAM page register has to be setting when in the indirect accessing RAM. The instructions MOV WRn, @WRq MOV @WRq, WRn could Read or Write the whole memory in the indirect addressing mode. The RAM address of @WRq indicates to (DBKRH)*800H + (DBKRL)*80H + (RAM page)*10H + (WRq). The organization of the data memory is shown in Figure 5-2. 4 bits 0000H : 007FH 0080H : 00FFH Data Bank 00 (or Working Registers Bank) 1st Data RAM Page (or 1st WR Page) 2nd Data RAM Page (or 2nd WR Page) 3rd Data RAM Page (or 3rd WR Page) : : 8th Data RAM Page (or 8th WR Page) 70H : 7FH 00H : 0FH 10H : 1FH 20H : 2FH Data Bank 01 (or Working Registers Bank) 5120 address : : : 1380H : 13FFH Bata Bank 39 5120 * 4 bits Figure 5-2 Data Memory Organization - 11 - Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 The 1st and 2nd data bank (00H to 7FH & 80H to 0FFH) in the data memory can also be used as the working registers (WR). It is also divided into sixteen pages. Each page contains 16 working registers. When one page is used as Working Register, the others can be used as the normal data memory. The WR page register can be switched by executing the MOV WRP, R or MOV WRP, #I instructions. The data memory can not do the logical operation directly with the immediate data, it has to via the Working Register. 5.4.2 RAM Page Register (PAGE) The page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 PAGE Note: R/W means read/write available. 2 R/W 1 R/W 0 R/W Bit 3 is reserved. Bit 2, Bit 1, Bit 0 RAM page bits: 000 = Page 0 (00H − 0FH) 001 = Page 1 (10H − 1FH) 010 = Page 2 (20H − 2FH) 011 = Page 3 (30H − 3FH) 100 = Page 4 (40H − 4FH) 101 = Page 5 (50H − 5FH) 110 = Page 6 (60H − 6FH) 111 = Page 7 (70H − 7FH) 5.4.3 WR Page Register (WRP) The WR page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 WRP R/W 2 R/W 1 R/W 0 R/W Note: R/W means read/write available. Bit 3, Bit 2, Bit 1, Bit 0 Working registers page bits: 0000 = WR Page 0 (00H − 0FH) 0001 = WR Page 1 (10H − 1FH) 0010 = WR Page 2 (20H − 2FH) 0011 = WR Page 3 (30H − 3FH) 0100 = WR Page 4 (40H − 4FH) 0101 = WR Page 5 (50H − 5FH) 0110 = WR Page 6 (60H − 6FH) 0111 = WR Page 7 (70H − 7FH) 1000 = WR Page 8 (80H − 8FH) - 12 - Deleted: SA5505 Deleted: W742C811 W742E/C816 1001 = WR Page 9 (90H − 9FH) 1010 = WR Page A (A0H − AFH) 1011 = WR Page B (B0H − BFH) 1100 = WR Page C (C0H − CFH) 1101 = WR Page D (D0H − DFH) 1110 = WR Page E (E0H − EFH) 1111 = WR Page F (F0H − FFH) 5.4.4 Data Bank Register (DBKRH, DBKRL) The data bank register is organized as two 4-bit binary register. The bit descriptions are as follows: 3 DBKRL R/W 3 DBKRH Note: R/W means read/write available. 2 R/W 2 1 R/W 1 R/W 0 R/W 0 R/W Bit5, Bit 4, Bit3, Bit 2, Bit 1, Bit 0 Data memory bank bits: 000000 = Data bank 0 (000H − 07FH) 000001 = Data bank 1 (080H − 0FFH) 000010 = Data bank 2 (100H − 17FH) 000011 = Data bank 3 (180H − 1FFH) 000100 = Data bank 4 (200H − 27FH) 000101 = Data bank 5 (280H − 2FFH) 000110 = Data bank 6 (300H − 37FH) 000111 = Data bank 7 (380H − 3FFH) 001000 = Data bank 8 (400H − 47FH) 001001 = Data bank 9 (480H − 4FFH) 001010 = Data bank 10 (500H − 57FH) 001011 = Data bank 11 (580H − 5FFH) 001100 = Data bank 12 (600H − 67FH) 001101 = Data bank 13 (680H − 6FFH) 001110 = Data bank 14 (700H − 77FH) 001111 = Data bank 15 (780H − 7FFH) 010000 = Data bank 16 (800H − 87FH) 010001 = Data bank 17 (880H − 8FFH) 010010 = Data bank 18 (900H − 97FH) - 13 - Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 010011 = Data bank 19 (980H − 9FFH) 010100 = Data bank 20 (0A00H − 0A7FH) 010101 = Data bank 21 (0A80H − 0AFFH) 010110 = Data bank 22 (0B00H − 0B7FH) 010111 = Data bank 23 (0B80H − 0BFFH) 011000 = Data bank 24 (0C00H − 0C7FH) 011001 = Data bank 25 (0C80H − 0CFFH) 011010 = Data bank 26 (0D00H − 0D7FH) 011011 = Data bank 27 (0D80H − 0DFFH) 011100 = Data bank 28 (0E00H − 0E7FH) 011101 = Data bank 29 (0E80H − 0EFFH) 011110 = Data bank 30 (0F00H − 0F7FH) 011111 = Data bank 31 (0F80H − 0FFFH) 100000 = Data bank 32 (1000H − 107FH) 100001 = Data bank 33 (1080H − 10FFH) 100010 = Data bank 34 (1100H − 117FH) 100011 = Data bank 35 (1180H − 11FFH) 100100 = Data bank 36 (1200H − 127FH) 100101 = Data bank 37 (1280H − 12FFH) 100110 = Data bank 38 (1300H − 137FH) 100111 = Data bank 39 (1380H − 13FFH) 5.4.5 RAM Addressing Mode 1. Direct Addressing Bit 12-0 12 11 10 9 8 7 6 5 4 3 2 1 0 RAM addr BH1 BH0 BL3 BL2 BL1 BL0 RA6 RA5 RA4 RA3 RA2 RA1 RA0 RA0-6 is RAM address ; BL0-3 is DBKRL register ; BH0-1 is DBKRH register Example: MOV MOV MOV DBKRL, #BL_value DBKRH, #BH_value A, RAM ; set RAM bank ; get RAM data to ACC - 14 - Deleted: SA5505 Deleted: W742C811 W742E/C816 2. Working Register Addressing Bit 7-0 7 6 5 4 3 2 1 0 RAM addr WP3 WP2 WP1 WP0 WA3 WA2 WA1 WA0 WA0-3 is Working register address ; WP0-3 is WR page register(WRP) Example: MOV MOV MOV MOVA 3. Indirect Addressing DBKRL, #BL_value DBKRH, #BH_value WRP, #I WRn, RAM ; set RAM bank ; set WR page register ; mov RAM data to Working register and ACC Bit 12-0 12 11 10 9 8 7 6 5 4 3 2 1 0 RAM addr BH1 BH0 BL3 BL2 BL1 BL0 DP2 DP1 DP0 (WA3 WA2 WA1 WA0) (WA0-3) is Working register contents ; DP0-3 is RAM page register(PAGE) BL0-3 is DBKRL register ; BH0-1 is DBKRH register Example: MOV MOV MOV MOV MOV DBKRL, BL_value DBKRH, BH_value PAGE, #Ip WRq, #In WRn, @WRq ; set RAM bank ; set RAM page address, (0 − 07H) ; set WR pointer address; (0 − 0FH) ; get the contents of WRq pointing addr to WRn 5.5 Accumulator (ACC) The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers. 5.6 Arithmetic and Logic Unit (ALU) This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions: Logic operations: ANL, XRL, ORL Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3 • Shift operations: SHRC, RRC, SHLC, RLC • Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC • • After any of the above instructions is executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOV R, CF. - 15 - Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 5.7 Main Oscillator The W742E/C816 provides a crystal oscillation circuit to generate the system clock through external connections. The 3.58 MHz or 400 KHz crystal must be connected to XIN1 and XOUT1, and a capacitor must be connected to XIN1 and VSS if an accurate frequency is needed. XIN1 Crystal 3.58 MHz XOUT1 Figure 5-3. System Clock Oscillator Configuration 5.8 Sub-oscillator The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the 32768 Hz crystal could be connected to XIN2 and XOUT2. 5.9 Dividers Divider 0 is organized with a 14-bit binary up-counter that is designed to generate periodic interrupt. When the main clock starts action, the Divider0 is incremented by each clock (FOSC). The main clock can come from main oscillator or sub-oscillator by setting SCR register. When an overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. And the last 4-stage of the Divider0 can be reset by executing CLR DIVR0 instruction. If the main clock is connected to the 32.768 KHz crystal, the EVF.0 will be set to 1 periodically at the period of 500 mS. Divider 1 is orginized with 13/12 bits up-counter that only has sub-oscillator clock source. If the suboscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.4 = 1), the hold state is terminated. And the last 4-stage of the Divider1 can be reset by executing CLR DIVR1 instruction. There are two period time (125 mS & 250 mS) that can be selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 250 mS period time is selected; SCR.3 = 1, the 125 mS period time is selected. - 16 - Deleted: SA5505 Deleted: W742C811 W742E/C816 5.10 Dual-clock Operation In this dual-clock mode, the normal operation is performed by generating the system clock from the main-oscillator clock (Fm). As required, the slow operation can be performed by generating the system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation is performed by setting the bit 0 of the System clock Control Register (SCR). If the SCR.0 is set to 0, the clock source of the system clock generator is main-oscillator clock; if the SCR.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. In the dual-clock mode, the mainoscillator can stop oscillating when the SCR.1 is set to 1. When the main clock switch, we must care the following cases: 1. X000B → X011B (FOSC = Fm→ FOSC = Fs): we should not exchange the FOSC from Fm into Fs and disable Fm simultaneously. We could first exchange the FOSC from Fm into Fs, then disable the main-oscillator. So it should be X000B→X001B→X011B. 2. X011B → X000B (FOSC = Fs→ FOSC = Fm): we should not enable Fm and exchange the FOSC from Fs into Fm simultaneously. We could first enable the main-oscillator; the 2nd step is calling a delay subroutine to wait the main-oscillator oscillating stabely; then exchange the FOSC from Fs into Fm is the last step. So it should be X011B→X001B→delay the Fm oscillating stable time→X000B. We must remember that the X010B state is inhibitive, because it will induce the system shutdown. The organization of the dual-clock operation mode is shown in Figure 5-4. HOLD SCR.0 XIN1 XOUT1 SCR.1 Fm Fs enable/disable M ain O scillator Fosc S ystem Clock Generator Divider 0 T1 T2 T3 T4 STOP XIN2 XOUT2 Sub-oscillator Divider 1 LCD Frequency Selector INT4 HCF.4 F LCD SCR.3(13/12 bit) SCR: System clock Control Register (default = 00H) Bit3 Bit2 Bit1 Bit0 0 : Fosc = Fm 1 : Fosc = Fs 0 1 0 1 0 1 Daul clock operation m ode: - SCR.0 = 0, Fosc = Fm : SCR.0 = 1, Fosc = Fs - Flcd = Fs, In STOP m ode LCD is turned off. : : : : : : Fm enable Fm disable W DT input clock is Fosc/1024 W DT input clock is Fosc/16384 13 bit 12 bit Figure 5-4. Organization of the dual-clock operation mode - 17 - Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 5.11 Watchdog Timer (WDT) The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from unknown errors. The WDT can be enabled by mask option code. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 by setting SCR.2 register. The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The WDT overflow period is about 500 mS when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/1024. The organization of the Divider0 and watchdog timer is shown in Figure 5-5. The minimum WDT time interval is 1/(FOSC/16384 x 16) - 1/(FOSC/16384). Divider0 Fosc Q1 Q2 HEF.0 S R ... Q9 Q10 Q11 Q12 Q13 Q14 EVF.0 Q IEF.0 Hold m ode release (HCF.0) Divider interrupt 1. Reset 2. CLR EVF,#01H Option code is reset to "0" S CR.2 Disable Qw1 R 3. CLR DIVR0 W DT Qw2 R Fosc/16384 Fosc/1024 Qw3 R Qw4 R Overflow signal System Reset Enable Option code is set to "1" 1. Reset 2. CLR W DT Figure 5-5. Organization of Divider0 and Watchdog Timer - 18 - Deleted: SA5505 Deleted: W742C811 W742E/C816 5.12 Timer/Counter 5.12.1 Timer 0 (TM0) Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L(TM0H), R instructions. When the MOV TM0L(TM0H), R instructions are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to 0, and the specified value can be loaded into TM0. Then we can set MR0.3 to 1, that will cause the event flag 1 (EVF.1) is reset and the TM0 starts to down count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag has been set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set (HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting MR0 bit 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 5-6. If the Timer 0 clock input is FOSC/4: Desired Timer 0 interval = (preset value +1) × 4 × 1/FOSC If the Timer 0 clock input is FOSC/1024: Desired Timer 0 interval = (preset value +1) × 1024 × 1/FOSC Preset value: Decimal number of Timer 0 preset value FOSC: Clock oscillation frequency 1. Reset 2. CLR EVF, #02H 3. Reset MR0.3 to 0 4. MOV TM0L, R or MOV TM0H, R MR0.0 Fosc/1024 Fosc/4 Enable Set MR0.3 to 1 MOV TM0H, R MOV TM0L, R 1. Reset 2. CLR EVF, #02H 3. Set MR0.3 to 1 Disable 8-Bit Binary Down Counter (Timer 0) 4 4 HEF.1 S R Q EVF.1 IEF.1 Timer 0 interrupt (INT1) Hold mode release (HCF.1) Figure 5-6 Organization of Timer 0 - 19 - Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 5.12.2 Timer 1 (TM1) Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 5-7. Timer 1 can output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: FOSC/64, FOSC or FS. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. When the MOV TM1L, R or MOV TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will be disabled that is MR1.3 is reset to 0 at the same time. If the bit 3 of MR1 is set (MR1.3 = 1), the content of the auto-reload buffer will be loaded into the TM1 down counter, and Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the timer decrements to 0FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. Then, if interrupt enable flag 7 has been set to 1 (IEF.7 = 1), an interrupt is executed; if hold mode release enable flag 7 is set to 1 (HEF.7 = 1), the hold state is terminated. The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting. In a case where Timer 1 clock input is FT: Desired Timer 1 interval = (preset value +1) / FT Desired frequency for MFP output pin = FT ÷ (preset value + 1) ÷ 2 (Hz) Preset value: Decimal number of Timer 1 preset value FOSC: Clock oscillation frequency MOV TM1H, R 4 MR1.3 MOV TM1L, R 4 S Q EVF.7 1. Reset 2. INT7 accept 3. CLR EVF, #80H 4. Set MR1.3 to 1 Auto-reload Buffer MR1.1 Fs FT Fosc/64 Disable MR1.0 Enable 8 bits 8-Bit Binary Dow n Counter (Tim er 1) Reset R Underflow signal 2 Circuit Reset Fosc MFP output pin MR1.2 Set MR1.3 to 1 MFP signal MOV TM1L, R or MOV TM1H, R Figure 5-7. Organization of Timer 1 - 20 - Deleted: SA5505 Deleted: W742C811 W742E/C816 For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below. Table 2 The relation between the tone frequency and the preset value of TM1 3rd Octave Tone Frequency 4th Octave 5th Octave TM1 Preset Value Tone & MFPFrequency Frequency 7CH 75H 6FH 68H 62H 5DH 58H 53H 4EH 49H 45H 41H 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 TM1 Preset Value Tone TM1 Preset Value & MFPFrequency Frequency & MFPFrequency 3EH 3AH 37H 34H 31H 2EH 2BH 29H 26H 24H 22H 20H 260.06 277.69 292.57 309.13 327.68 372.36 390.09 420.10 443.81 442.81 468.11 496.48 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77 1EH 1CH 1BH 19H 18H 16H 15H 14H 13H 12H 11H 10H 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76 T O N E C C# D D# E F F# G G# A A# B 130.81 138.59 146.83 155.56 164.81 174.61 185.00 196.00 207.65 220.00 233.08 246.94 Note: Central tone is A4 (440 Hz). 5.12.3 Mode Register 0 (MR0) Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows: 3 MR0 Note: W means write only. 2 1 0 W W Bit 0 = 0 =1 Bit 3 = 0 =1 The fundamental frequency of Timer 0 is FOSC/4. The fundamental frequency of Timer 0 is FOSC/1024. Timer 0 stops down-counting. Timer 0 starts down-counting. Bit 1 & Bit 2 are reserved - 21 - Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 5.12.4 Mode Register 1 (MR1) Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows: 3 MR1 Note: W means write only. 2 W 1 W 0 W W Bit 0 = 0 =1 Bit 1 = 0 =0 The internal fundamental frequency of Timer 1 is FOSC. The internal fundamental frequency of Timer 1 is FOSC/64. The fundamental frequency source of Timer1 is the internal clock. The fundamental frequency source of Timer1 is the sub-oscillator frequency Fs (32.768 KHz). Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin. = 1 The specified frequency of Timer 1 is delivered at the MFP output pin. Bit 3 = 0 Timer 1 stops down-counting. = 1 Timer 1 starts down-counting. 5.13 Interrupts The W742E/C816 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and seven external interrupt source (port P1.2 ( INT0 ), RC.0-3, Serial port, P1.3 ( INT1 )). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 023H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, the corresponding bit of EVF will be clear, and all of the interrupts will be inhibited until the EN INT or MOV IEF, #I instruction is invoked. Normally, the EN INT instruction will be asserted before the RTN instruction. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in the hold mode, the hold mode will be released momentarily and interrupt service routine will be executed. After executing interrupt service routine, the µC will enter hold mode automatically. The operation flow chart is shown in Figure 5-9. The control diagram is shown Figure 5-8. - 22 - Deleted: SA5505 Deleted: W742C811 W742E/C816 EN INT Divider 0 Overflow Signal M OV IEF, #I S R Tim er 0 Underflow Signal Q EVF.0 Initial Reset Enable IEF.0 S R Q EVF.1 IEF.1 Interrupt Process Circuit Interrupt Vector Generator 004H 008H RC.0-3 Signal S R Q EVF.2 IEF.2 020H P1.2 (/INT0) Signal S R Q EVF.3 IEF.3 Divider 1 Overflow Signal S R Q EVF.4 IEF.4 Serial I/O Signal S R Q EVF.5 IEF.5 P1.3(/INT1) Signal S R Q EVF.6 IEF.6 Tim er 1 Underflow Signal S R Q EVF.7 IEF.7 Initial Reset Disable CLR EVF, #I Instruction DIS INT Instruction Figure 5-8. Interrupt event control diagram - 23 - Publication Release Date: April 15, 2005 Revision A2 Deleted: SA5505 Deleted: W742C811 W742E/C816 5.14 Stop Mode Operation In stop mode, all operations of the µC cease. The µC enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a falling signal on the RC or RD port). When the designated signal is accepted, the µC awakens and executes the next instruction. In the dual-clock slow operation mode, the STOP instruction will disable both the main-oscillator and sub-oscillator oscillating; to avoid erroneous execution, the NOP instruction should follow the STOP command. 5.14.1 Stop Mode Wake-up Enable Flag for RC and RD Port (SEF) The stop mode wake-up flag for port RC and RD is organized as an 8-bit binary register (SEF.0 to SEF.7). Before port RC and RD can be used to exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows: 7 SEF Note: W means write only. 6 w 5 w 4 w 3 w 2 w 1 w 0 w w SEF.0 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.0 SEF.1 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.1 SEF.2 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.2 SEF.3 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.3 SEF.4 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.0 SEF.5 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.1 SEF.6 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.2 SEF.7 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.3 5.15 Hold Mode Operation In hold mode, all operations of the µC cease, except for the operation of the oscillator, Timer, Divider, and LCD driver. The µC enters hold mode when the HOLD instruction is executed. The hold mode can be released in one of nine ways: by the action of timer 0, timer 1, divider 0, divider 1, RC port, P1.2 ( INT0 ), Serial I/O, P1.3 ( INT1 ) and RD port. Before the device enters the hold mode, the HEF, HEFD, PEF, and IEF flags must be set to control the hold mode release conditions. When any of the HCF bits is "1," the hold mode will be released. Regarding to RC and RD port, PSR0 and PSR1 registers indicate signal change on which pin of the port. The HCF and HCFD are set by hardware and clear by software. When EVF, EVFD and HEF, HEFD have been reset by the CLR EVF, #I CLR EVFD and MOV HEF, #I CLR HEFD instructions, the corresponding bit of HCF, HCFD is reset simultaneously. The HCF and HCFD should be clear every time before enter the hold mode. For more details, refer to the following flow chart. - 24 - Deleted: SA5505 Deleted: W742C811 W742E/C816 D ivider 0, Divider 1, Tim er 0, Tim er 1, Signal Change at RC, RD port, falling edge at P1.2, P1.3, Serial I/O Yes In HOLD Mode? No Interrupt Enable? Yes No Interrupt Enable? Yes No IEF Flag Set? Yes No IEF Flag Set? Yes No Reset EVF Flag Execute Interrupt Service Routine (Note) HEF Flag Set? No Yes Reset EVF Flag Execute Interrupt Service Routine (Note) (Hold release) Disable interrupt Disable interrupt HOLD PC