W78C374P

Preliminary W78E378/W78C378/W78C374 MONITOR CONTROLLER GENERAL DESCRIPTION The W78E378, W78C378 and W78C374B are ASIC which is a stand-alone high-performance microcontroller specially designed for monitor control applications. The device integrates the embedded 80C31 microcontroller core, on-chip MTP or Mask ROM, 576 bytes of RAM, and a number of dedicated hardware monitor functions. Additional special function registers are incorporated to control the on-chip peripheral hardware. The chip is used to control the interface signal of other devices in the monitor and to process the video sync signals. Because of the highly integration and Flash cell for program memory, the device can offer users the competitive advantages of low cost and reduced development time. FEATURES • • • • • • • • • • • • • • • • • 80C31 MCU Core Embedded 32K Bytes MTP-ROM (W78E378) 32K Bytes Mask-ROM (W78C378) 16K Bytes Mask-ROM (W78C374B) Total 576 Bytes of On-chip Data RAM − 256 bytes accessed as in the 80C32 − 320 bytes accessed as external data memory via "MOVX @Ri" PWM DACs − Eight 8-bit Static PWM DACs: DAC0−DAC8 − Three 8-bit Dynamic PWM DACs: DAC9−DAC10 Sync Processor − Horizontal & Vertical Polarity Detector − Sync Separator for Composite Sync − 12-bit Horizontal & Vertical Frequency Counter − Programmable Dummy Frequency Generator − Programmable H-clamp Pulse Output − SOA Interrupt − Hsync/2 Output Serial Ports: − DDC1 Port- support DDC1 − SIO1 & SIO2 Ports - each can support DDC2B/2B+/2Bi/2AB (each has 2 slave addresses) Two 16-bit Timer/Counters (8031's Timer0 & Timer1) One External Interrupt Input (8031's INT0 ) One Parabola Interrupt Generator One ADC with 7 Multiplexed Analog Inputs Two 12 mA(min) Output Pins for Driving LEDs 22 Watchdog Timer (2 /Fosc = 0.42s @Fosc = 10 MHz) Power Low Reset Frequency: 10 MHz max. (with the same performance as a normal 8051 that uses 20 MHz) Packaged in 40/32-pin 600 mil DIP & 44-pin PLCC -1- Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 PIN CONFIGURATIONS 40-pin DIP: W78E378E W78C378E W78C374E P4.1 P4.0 (HFI) P3.5 (ADC4, T0)* P1.1 (DAC1)* 40-pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32-pin DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P4.2 P4.3 P3.6 (ADC5, T1)* P1.2 (DAC2)* P1.3 (DAC3)* P1.4 (DAC4)* P1.5 (DAC5)* P1.6 (DAC6)* P1.7 (DAC7)* P2.0 (DAC8) P2.1 (DAC9) P2.2 (DAC10) P2.3 (Hclamp) P2.4 (ADC0) P2.5 (ADC1) P2.6 (ADC2) P2.7 (ADC3) P3.7 (ADC6)* P4.4 (SCL2)* P4.5 (SDA2)* 32-pin DIP: W78E378 W78C378 W78C374 P1.0 (DAC0)* P3.4 (VOUT) P3.3 (HOUT) HIN VIN RESET VDD VSSA OSCOUT OSCIN P3.2 ( INT0 ) P3.1 (SCL)* P3.0 (SDA)* VSS P4.7 (HFO) P4.6 44-pin PLCC P 3 . 4 P 1 . 0 P 1 . 1 P 3 . 5 P 4 . 0 P 4 . 1 P 4 . 2 P 4 . 3 P 3 . 6 P 1 . 2 P 1 . 3 P3.3 H IN VIN RESET VDD VDDA VDD VSSA OSCOUT OSCIN P3.2 7 8 9 10 11 12 13 14 15 16 17 1 1 2 890 P 3 . 1 65432144444 43210 W78E378P W78C378P W78C374P 22222 12345 P 4 . 5 P 4 . 4 39 38 37 36 35 34 33 32 31 30 2 2 2 29 678 P 3 . 7 P 2 . 7 P 2 . 6 P1.4 NC P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 PVVPP 3SS44 . SS. . 0 76 -2- Preliminary W78E378/W78C378/W78C374 PIN DESCRIPTION PIN NAME RESET I/O I/O DESCRIPTION Chip reset input (active low) input & Internal reset output (generated by WDT or power low) TTL Schmitt trigger input, internal pull-up ~30 KΩ IOL = +12 mA @VOL = 0.45V VDD VSS VSS OSCOUT OSCIN HIN O I I Positive power supply Ground Ground Output from the inverting oscillator amplifier Input to the inverting oscillator amplifier, 10 MHz max. Hsync input TTL Schmitt trigger input , w/o PMOS VIH/VIL = 2.0V/0.8V, V+/ V- = ~1.6V/ 1.1V VIN I Vsync input TTL Schmitt trigger input, w/o PMOS VIH/VIL = 2.0V/0.8V, V+/ V- = ~1.6V/ 1.1V P1.0 (DAC0) P1.1 (DAC1) P1.2 (DAC2) P1.3 (DAC3) P1.4 (DAC4) P1.5 (DAC5) P1.6 (DAC6) P1.7 (DAC7) I/O I/O I/O I/O I/O I/O I/O I/O General purpose I/O, DAC0 special function output Open-drain output, sink current: 15 mA General purpose I/O, DAC1 special function output Open-drain output, sink current: 15 mA General purpose I/O, DAC2 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC3 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC4 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC5 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC6 special function output Open-drain output, sink current: 4 mA General purpose I/O, DAC7 special function output Open-drain output, sink current: 4 mA -3- Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 Pin Description, Continued PIN NAME P2.0 (DAC8) P2.1 (DAC9) P2.2 (DAC10) P2.3 (Hclamp) P2.4 (ADC0) P2.5 (ADC1) P2.6 (ADC2) P2.7 (ADC3) P3.0 (SDA) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION General purpose I/O, DAC8 Special Function output Sink/Source current: 4 mA/-100 µA (-4 mA for SF output) General purpose I/O, DAC9 Special Function output Sink/Source current: 4 mA/-100 µA (-4 mA for SF output) General purpose I/O, DAC10 Special Function output Sink/Source current: 4 mA/-100 µA (-4 mA for SF output) General purpose I/O, Hclamp Special Function output Sink/Source current: 4 mA/-100 µA (-4 mA for SF output) General purpose I/O, ADC input channel 0 Sink/Source current: 4 mA/-100 µA General purpose I/O, ADC input channel 1 Sink/Source current: 4 mA/-100 µA General purpose I/O, ADC input channel 2 Sink/Source current: 4 mA/-100 µA General purpose I/O, ADC input channel 3 Sink/Source current: 4 mA/-100 µA General purpose I/O, DDC port serial data I/O Schmitt trigger input VIH/VIL = 0.7 VDD/0.3 VDD, V+/V- = ~0.6 VDD/ 0.4 VDD Open-drain output, sink current: 8 mA General purpose I/O, DDC port serial clock I/O Schmitt trigger input VIH/VIL = 0.7 VDD/0.3 VDD, V+/V- = ~0.6 VDD/ 0.4 VDD Open-drain output, sink current: 8 mA General purpose I/O, INT0 input Sink/Source current: 1 mA/ -100 µA General purpose I/O, HOUT special function output Sink/Source current: 4 mA/-100 µA (-4 mA for SF output) General purpose I/O, VOUT special function output Sink/Source current: 4 mA/-100 µA (-4 mA for SF output) General purpose I/O, ADC input channel 4 Open-drain output, sink current: 4 mA General purpose I/O, ADC input channel 5 Open-drain output, sink current: 4 mA General purpose I/O, ADC input channel 6 Open-drain output, sink current: 4 mA P3.1 (SCL) I/O P3.2 ( INT0 ) P3.3 (HOUT) P3.4 (VOUT) P3.5 (ADC4, T0) P3.6 (ADC5, T1) P3.7 (ADC6) I/O I/O I/O I/O I/O I/O -4- Preliminary W78E378/W78C378/W78C374 Pin Description, Continued PIN NAME P4.0 (HFI) P4.1 P4.2 P4.3 P4.4 (SCL2) I/O I/O O O O I/O P4.0 Output, HFI Input DESCRIPTION Sink/Source current: 4 mA/-4 mA P4.1 Output Sink/Source current: 4 mA/-4 mA P4.2 Output Sink/Source current: 4 mA/-4 mA P4.3 Output Sink/Source current: 4 mA/-4 mA P4.4 Output, SIO2 port serial clock I/O Schmitt trigger input VIH/VIL = 0.7 VDD/0.3 VDD, V+/V- = ~0.6 VDD/0.4 VDD Open-drain output, sink current: 8 mA P4.5 (SDA2) I/O P4.5 Output, SIO2 port serial data I/O Schmitt trigger input VIH/VIL = 0.7 VDD/0.3 VDD, V+/V- = ~0.6 VDD/0.4 VDD Open-drain output, sink current: 8 mA P4.6 P4.7 (HFO) O O P4.6 Output Sink/Source current: 4 mA/-4 mA P4.7 Output, HFO Output Sink/Source current: 4 mA/-4 mA -5- Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 BLOCK DIAGRAM VDD VSS 80C31 Core excluding internal RAM Note: freq1 = freq2 freq2 CPU Interrupt Processor Timer 0 Timer 1 INT0 (P3.2) OSCIN OSCOUT freq1 Osc. Circuit T0 (P3.5) T1 (P3.6) RESET Reset Circuit P1, P2, P3 Power Low Detection I/O Port P4 Note: P1, P4.4~P4.5 P3.0~P3.1 & P3.5~P3.7 are open-drain. Watch Dog Timer VPP (P3.2) Program Memory SCL (P3.1) SIO1 SDA (P3.0) SCL2 (P4.4) SIO2 SDA2 (P4.5) Data Memory RAM: 576 Bytes HIN, VIN HFI (P4.0) VOUT (P3.4) HOUT (P3.3) Hclamp (P2.3) HFO (P4.7) ADC0 (P2.4) ADC1 (P2.5) ADC2 (P2.6) ADC3 (P2.7) ADC4 (P3.5) ADC5 (P3.6) ADC6 (P3.7) Sync. Processor Static DACs DAC0~7 (P1.0~P1.7) Dynamic DACs ADC 8-bit Internal Bus DAC8~10 (P2.0~P2.2) -6- Preliminary W78E378/W78C378/W78C374 FUNCTIONAL DESCRIPTION Address Space 7FFFh (3FFFh) Internal Program Memory FFh Internal RAM 256 Bytes Indirect Addressing "MOV @Ri" 8051SFRs & Serial Ports SFRs Direct Addressing "MOV" FFh On-Chip Data Memory C0h BFh 64 Bytes External Access "MOVX @Ri" new SFRs External Access External Access "MOVX @Ri" 80h 7Fh Direct or Indirect Addressing "MOV" or "MOV @Ri" 80h "MOVX @Ri" 7Fh On-Chip Data Memory 128 Bytes 7Fh On-Chip Data Memory 128 Bytes External Access "MOVX @Ri" External Access "MOVX @Ri" 0000h 00h 00h BANK0 00h BANK1 Program/Data/SFRs Address Space SFRs accessed using 'Direct Addressing' REGISTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A* B* PSW* SP DPL DPH IE* IP* TCON* TMOD TL0 TH0 TL1 TH1 PCON ADDRESS E0h F0h D0h 81h 82h 83h A8h B8h 88h 89h 8Ah 8Ch 8Bh 8Dh 87h BITS 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 POWER ON RESET 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h RESET 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h x0h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -7- Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 SFRs accessed using 'Direct Addressing', continued REGISTER 16 17 18 19 20 21 22 23 24 25 26 27 28 28 P1* P2* P3* TMREG* S1CON* S1STA S1DAT S1ADR1 S1ADR2 S2CON* S2STA S2DAT S2ADR1 S2ADR2 ADDRESS 90h A0h B0h C0h D8h D9h DAh DBh DCh E8h E9h EAh EBh ECh BITS 8 8 8 3 8 8 8 8 8 8 8 8 8 8 POWER ON RESET 00h FFh 1Fh 00h 00h F8h FFh 00h 00h 00h F8h FFh 00h 00h RESET 00h FFh 1Fh xxh 00h F8h FFh 00h 00h 00h F8h FFh 00h 00h R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W Notes: 1. The SFRs marked with an asterisk (*) are both bit- and byte-addressable. 2. Port 1 and P3.5−P3.7 outputs low during & after reset. 3. "x" means no reset action. 4. The SFRs in the shaded region are new-defined. * Modified PCON BIT 0 1 2 3 4 5 6 7 NAME ADCS2 PD GF0 GF1 TEST0 TEST1 ADCcal CPUhalt ADC channel Select bit 2 Power Down bit General purpose flag bit General purpose flag bit Test purpose flag bit Test purpose flag bit Set 0/1 to select 1.0V/3.0V for ADC calibration Set to let CPU halt when the chip runs internally FUNCTION * TMREG: Test Mode Register BIT 0 1 2 NAME TM1 TM2 TM3 Test Mode1 Test Mode2 Test Mode3 FUNCTION -8- Preliminary W78E378/W78C378/W78C374 SFRs accessed using 'MOVX @Ri' REGISTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 CTRL1 CTRL2 P1SF P2SF P3SF PARAL PARAH HFCOUNTL HFCOUNTH VFCOUNTL VFCOUNTH WDTCLR SOARL SOARH SOACLR INTMSK INTVECT INTCLR DDC1 ADC DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 DAC9 DAC10 P4 CTRL3 ADDRESS 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BITS 8 8 8 8 8 8 5 8 8 8 8 8/6 8/6 6 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 POWER ON RESET 00h 00h 00h 00h 00h 00h 00h x x x x x x x x 00h 00h x x x 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh 00h RESET 00h 00h xxh xxh 00h 00h 00h x x x x x x x x 00h 00h x x x x x x x x x x x x x x FFh 00h R/W TYPE W W W W W R/W R/W R R R R W R/W R/W W R/W R W W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W Note: "x" means no reset action. -9- Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 * CTRL1: Control Register 1 (Write Only) BIT 0 NAME ADCSTRT FUNCTION A-to-D Conversion START control Set by S/W to start conversion. Cleared by H/W while conversion completed (read SOARH.6 to check). ADC channel Select bit 0 ADC channel Select bit 1 Enable DDC1 H-Clamp Edge Select 0: Select leading edge of restored Hsync 1: Select trailing edge of restored Hsync H-Clamp Width Select bit Dummy signal Enable Vsync Separator Disable, 0: Enable, 1: Disable 1 2 3 4 ADCS0 ADCS1 ENDDC1 HCES 5 6 7 HCWS DUMMYEN VSDIS * CTRL2: Control Register 2 (Write Only) BIT 0 1 2 3 4 5 6 7 NAME HSPS VSPS HDUMS0 VDUMS DDC1B9 WDTEN SOAHDIS OSCHI FUNCTION HSync Polarity Select 0: Positive, 1: Negative VSync Polarity Select 0: Positive, 1: Negative H Dummy frequency Select 0 V Dummy frequency Select Bit 9 in DDC1 mode Enable Watch Dog Timer Disable SOA low to high detection OSC freq. Higher than 10 MHz * CTRL3: Control Register 3 (Write Only) BIT 0 1 2 3 4 5−7 NAME ENHFO HDUMS1 HFO_POL HFO_HALF ENBNK1 FUNCTION Enable HF input/output for P4.0/P4.7, respectively 0: Disable, 1: Enable H Dummy frequency Select 1 Select HFO polarity 0: Positive, 1: Negative Select HFO output freq. 0: the same as HFI, 1: half of the HFI Select on-chip ext. RAM bank 0: Bank 0, 1: Bank 1 - - 10 - Preliminary W78E378/W78C378/W78C374 *P1SF: Port1 special function output enable register (Write Only) BIT 0 1 2 3 4 5 6 7 NAME P10SF P11SF P12SF P13SF P14SF P15SF P16SF P17SF FUNCTION Port 1.0 Special Function enable (DAC0 output) Port 1.1 Special Function enable (DAC1 output) Port 1.2 Special Function enable (DAC2 output) Port 1.3 Special Function enable (DAC3 output) Port 1.4 Special Function enable (DAC4 output) Port 1.5 Special Function enable (DAC5 output) Port 1.6 Special Function enable (DAC6 output) Port 1.7 Special Function enable (DAC7 output) *P2SF: Port2 special function output enable register (Write Only) BIT 0 1 2 3 4 5 6 7 NAME P20SF P21SF P22SF P23SF P24SF P25SF P26SF P27SF FUNCTION Port 2.0 Special Function enable (DAC8 output) Port 2.1 Special Function enable (DAC9 output) Port 2.2 Special Function enable (DAC10 output) Port 2.3 Special Function enable (Hclamp output) Port 2.4 Special Function enable (ADC0 input) Port 2.5 Special Function enable (ADC1 input) Port 2.6 Special Function enable (ADC2 input) Port 2.7 Special Function enable (ADC3 input) *P3SF: Port3 special function output enable register (Write Only) BIT 0−2 3 4 5−7 NAME P33SF P34SF FUNCTION Port 3.3 Special Function enable (HOUT) Port 3.4 Special Function enable (VOUT) - *HFCOUNTL: Horizontal frequency counter register, low byte (Read Only) BIT 0 1 2 3 4 5 6 7 NAME HF0 HF1 HF2 HF3 HF4 HF5 HF6 HF7 FUNCTION H frequency count bit 0 H frequency count bit 1 H frequency count bit 2 H frequency count bit 3 H frequency count bit 4 H frequency count bit 5 H frequency count bit 6 H frequency count bit 7 - 11 - Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 *HFCOUNTH: Horizontal frequency counter register, high byte (Read Only) BIT 0 1 2 3 4−5 6 7 NAME HF8 HF9 HF10 HF11 NOH HPOL FUNCTION H frequency count bit 8 H frequency count bit 9 H frequency count bit 10 H frequency count bit 11 Set by hardware if no Hin signal Hin polarity. 0: Positive, 1: Negative *VFCOUNTL: Vertical frequency counter register, low byte (Read Only) BIT 0 1 2 3 4 5 6 7 NAME VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 FUNCTION V frequency count bit 0 V frequency count bit 1 V frequency count bit 2 V frequency count bit 3 V frequency count bit 4 V frequency count bit 5 V frequency count bit 6 V frequency count bit 7 *VFCOUNTH: Vertical frequency counter register, high byte (Read Only) BIT 0 1 2 3 4−5 6 7 NAME VF8 VF9 VF10 VF11 NOV VPOL FUNCTION V frequency count bit 8 V frequency count bit 9 V frequency count bit 10 V frequency count bit 11 Set by hardware if no VIN signal VIN polarity. 0: Positive, 1: Negative * INTVECT: Interrupt Vector Register (Read Only) BIT 0 1 2 3 4 NAME SCLINT ADCINT DDC1INT SOAINT VEVENT FUNCTION SCL pin pulled low detected ADC conversion completed DDC1 port buffer empty SOA condition happen Vsync pulse detected or NOV = 1 (V counter overflow) (The VEVENT is designed to be generated only 'one' time if no Vsync input.) Parabola Interrupt generated 5 PARAINT - 12 - Preliminary W78E378/W78C378/W78C374 * INTMSK: Interrupt Mask Register (Read/Write) BIT 0 1 2 3 4 5 NAME MSCLINT MADCINT MDDC1INT MSOAINT MVEVENT MPARAINT FUNCTION Set/clear to enable/disable SCLINT Set/clear to enable/disable ADCINT Set/clear to enable/disable DDC1INT Set/clear to enable/disable SOAINT Set/clear to enable/disable VEVENT Set/clear to enable/disable PARAINT * INTCLR (Write Only) BIT 0 1 2 3 4 5 NAME CSCLINT CADCINT CDDC1INT CSOAINT CVEVENT CPARAINT FUNCTION Write 1 to this bit to clear SCLINT in INTVECT Write 1 to this bit to clear ADCINT in INTVECT Write 1 to this bit to clear DDC1INT in INTVECT Write 1 to this bit to clear SOAINT in INTVECT Write 1 to this bit to clear VEVENT in INTVECT Write 1 to this bit to clear PARAINT in INTVECT *PARAL: Parabola interrupt generator register, low byte (Read/Write) BIT 0 1 2 3 4 5 6 7 NAME PARA0 PARA1 PARA2 PARA3 PARA4 PARA5 PARA6 PARA7 FUNCTION PARAINT period register bit 0 PARAINT period register bit 1 PARAINT period register bit 2 PARAINT period register bit 3 PARAINT period register bit 4 PARAINT period register bit 5 PARAINT period register bit 6 PARAINT period register bit 7 *PARAH: Parabola interrupt generator register, high byte (Read/Write) BIT 0 1 2 3 4 NAME PARA8 PARA9 PARA10 PARA11 PARA12 FUNCTION PARAINT period register bit 8 PARAINT period register bit 9 PARAINT period register bit 10 PARAINT period register bit 11 PARAINT period register bit 12 - 13 - Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 *SOARL: SOA register, low byte (Read/Write) BIT 0 1 2 3 4 5 6 7 NAME SL0 SL1 SL2 SL3 SL4 SL5 (OVL) (OVH) FUNCTION SOA Low register bit 0 SOA Low register bit 1 SOA Low register bit 2 SOA Low register bit 3 SOA Low register bit 4 SOA Low register bit 5 OVL = 1: current H count larger than SOARL, for test OVH = 1: current H count smaller than SOARH, for test *SOARH: SOA register, high byte (Read/Write) BIT 0 1 2 3 4 5 6 7 * ADC * DAC0~DAC8 * DAC9~DAC10 * WDTCLR * SOACLR * DDC1 * S1CON * S1STA * S1DAT * S1ADR1, S1ADR2 * S2CON * S2STA * S2DAT * S2ADR1, S2ADR2 NAME SH0 SH1 SH2 SH3 SH4 SH5 (ADCSTRT) (WDTQ10) FUNCTION SOA High register bit 0 SOA High register bit 1 SOA High register bit 2 SOA High register bit 3 SOA High register bit 4 SOA High register bit 5 ADCSTRT bit status, for test Watch Dog Timer, bit 10, for test Result of the A-to-D conversion. 8-bit PWM static DAC register. 8-bit PWM dynamic DAC register. Watchdog-timer-clear register, without real hardware but an address. Writing any value to WDTCLR will clear the watchdog timer. Safe-Operation-Area Clear register, without real hardware but an address. Writing any value to SOACLR will clear the SOAINT. DDC1 latch buffer. SIO1 control register. SIO1 status register. SIO1 data register. SIO1 address registers. SIO2 control register. SIO2 status register. SIO2 data register. SIO2 address registers. - 14 - Preliminary W78E378/W78C378/W78C374 Modified Timer 0 & Timer 1 Modified point in Timer 0 (Not divided by 12) OSC . .6 C/T = 0 To TL0 T0 pin (P3.5) TR0 C/T = 1 GATE INT0 pin (P3.2) Modified point in Timer 1 (Not divided by 12) OSC . .6 C/T = 0 To TL1 T1 pin (P3.6) TR1 C/T = 1 GATE VDD Modified point in Timer 1 (No INT1 pin) - 15 - Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 DDC1/SIO1 and SIO2 Ports 1. DDC1/SIO1 port DDC Port SIO1 IN SCL OUT SCL IN SDA OUT SDA 0 Support DDC2B/2B+ 1 DDC1 SDA SCL OUT Vsync Support DDC1 ENDDC1 • ENDDC1 = 1, used as DDC1 (Display Data Channel) port: To support DDC1, use Vsync signal for shift clock and P3.0 (SDA) for data output. • ENDDC1 = 0, used as SIO1 port: To support DDC2B/2B+/2Bi/2AB, use P3.1 (SCL) for serial clock and P3.0 (SDA) for serial data. SCLINT interrupt is generated when SCL (P3.1) has a high-to-low transition and then keeps at low for 16 × 1/Fosc. Fosc SCL low 2. SIO2 port: 8 MHz 2 µS 10 MHz 1.6 µS • To support DDC2B/2B+/2Bi/2AB, use P4.4 (SCL) for serial clock and P4.5 (SDA) for serial data. DDC1 Port The DDC1 is a serial output port that supports DDC1 communication. To enable the DDC1 port, ENDDC1 (bit 3 of CTRL1) should be set to '1'. Once previous eight data bits in the shift register and one null bit (the 9th bit) are shifted out to the SDA sequentially on each rising edge of the VIN signal, the DDC1 control circuit loads the next data byte from the latch buffer (the DDC1 register) to the shift register and generates a DDC1INT signal to the CPU. In the interrupt service routine, the S/W should fetch the next byte of EDID data and write it to the DDC1 register. If ENDDC1 is cleared, the shift register is stopped, and the SDA output is kept high. The bit DDC1B9 (bit 4 of CTRL2) decides the 9th bit in a DDC transmission. If DDC1B9 is set, the 9th bit will be '1', otherwise '0'. - 16 - Preliminary W78E378/W78C378/W78C374 To use DDC1 port, a user should pay attention to the following items: (1) When the chip is powered-on or after reset , the 8-bit shift register in DDC1 H/W contains all 0s. If you write a data to the latch buffer (the DDC1 register), it will be loaded to the shift register at the 9th clock (on VIN), so from the 10th clock, the real data bit begins to shift out. (2) Because there is no reset signal to the latch buffer, it contains a random data after power-on. If you enable DDC1 without writing data to the latch buffer, SDA will have the random data shifted out after 9 clocks. The shift register is reset to 00H during CPU reset. (3) The DDC1 H/W has a counter that counts how many bits shifted out. This counter is initialized to 0 when power-up or reset. When you firstly enable DDC1 after power-on, the first bit is already shifted out without clock, so the first clock triggers the second data bit (D6) to shift out and "0000 0001 1" will be got. After the first 9 clocks that shift out an invalid byte, the counter counts from 1 to 9 cyclically according to the clock pulse on VIN-pin. See the following illustration. After power on, the counter count: shifted-out data bit: VIN clock pulse: 012345678 9 12 34 5 67 89 12 3 456 7 89 ... 000000001 1 12345678 9 |--> invalid data D7 D6 D5 D4 D3 D2 D1 D0 ack 12 34 5 67 89 D7 D6 D5 D4 D3 D2 D1 D0 ack … 12 3 456 7 89 ... |--> normal data (4) The interrupt happens on the failing edge of the following first clock. The next data, which is about to be shifted out, in the latch buffer is loaded into the shift register at the rising edge of the following first clock. At the same time, data bit D7 is shifted out and the counter value is "1". SIO1 Port (with two slave addresses) The SIO1 port is a serial I/O port, which supports all transfer modes from and to the I C bus. The SIO1 port handles byte transfers autonomously. To enable this port, the bit ENDDC1 in CTRL1 should be cleared to '0'. The CPU interfaces to the SIO1 port through the following five special function registers: S1CON (control register, D8h), S1STA (status register, D9h), S1DAT (data register, DAh) and S1ADR1/S1ADR2 (address registers, DBh/DCh). The SIO1 H/W interfaces to the 2 I C bus via two pins: SDA (P3.0, serial clock line) and SCL (P3.1, serial data line). The output latches of P3.0 and P3.1 must be set to "1" before using this port. SIO2 Port (with two slave addresses) The function of this port is the same as SIO1 port. The CPU interfaces to the SIO2 port through the following five special function registers: S2CON (control register, E8h), S2STA (status register, E9h), S2DAT (data register, EAh) and S2ADR1/S2ADR2 (address registers, EBh/ECh). The SIO2 H/W 2 interfaces to the I C bus via two pins: SDA2 (P4.5, serial clock line) and SCL2 (P4.4, serial data line). The output latches of P4.5 and P4.4 must be set to "1" before using this port. Operation of SIO1 Port: (SIO2 has the same function except their addresses of control registers) 2 - 17 - Publication Release Date: December 1999 Revision A1 Preliminary W78E378/W78C378/W78C374 a) Control Registers a-1) The Address Registers, S1ADR1, S1ADR2 The SIO1 is equipped with two address registers: S1ADR1 & S1ADR2. The CPU can read from and write to these two 8-bit, directly addressable SFRs. The content of these registers are irrelevant when SIO1 is in master modes. In the slave modes, the seven most significant bits must be loaded with the MCU's own address. The SIO1 hardware will react if either of the addresses is matched. 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 - |------------------------ Own Slave Address -----------------------| a-2) The Data Register, S1DAT This register contains a byte of serial data to be transmitted or a byte which has just been received. The CPU can read from or write to this 8-bit directly addressable SFR while it is not in the process of shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag (SI) is set. Data in S1DAT remains stable as long as SI is set. While data is being shifted out, data on the bus is simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in S1DAT. 7 SD7 6 SD6 5 SD5 4 SD4 3 SD3 2 SD2 1 SD1 0 SD0 |