W78C54

W78C54 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The W78C54 is a derivative of the W78C52 microcontroller family that provides extended internal ROM. The chip has 16K bytes of mask ROM and 256 bytes of RAM. This device provides an enhanced architecture that makes it more powerful and suitable for a variety of applications for general control systems. It provides on-chip 16KB mask ROM to accommodate large program codes, 256-bytes of non-volatile on-chip RAM, four 8-bit I/O ports, one 4-bit I/O port, three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator clock circuits. FEATURES • DC to 40 MHz extensive operating frequency • 256-byte on-chip scratch pad RAM • 16K-byte on-chip mask ROM • 64K-byte address space for external Program Memory • 64K-byte address space for external Data Memory • Three 16-bit timer/counters • Four 8-bit bit-addressable I/O ports • One extra 4-bit bit-addressable I/O port, additional INT2/ INT3 (Available on 44-pin PLCC/QFP package) • Eight-source, two priority-level interrupts • Low EMI emission mode • Built-in programmable power-saving modes - Idle mode & Power-down mode • Packages: − DIP 40: W78C54-16/24/40 − PLCC 44: W78C54P-16/24/40 − QFP 44: W78C54F-16/24/40 − TQFP 44: W78C54M-16/24/40 -1- Publication Release Date: December 1997 Revision A2 W78C54 PIN CONFIGURATIONS 40-Pin DIP (W78C54) T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 44-Pin PLCC (W78C54P) / I N T 3 , P 4V .C 2C 44-Pin QFP/TQFP (W78C54F/W78C54M) T 2 E X , PPPP 1111 .... 4321 / I N TT 23 ,, PP 14V ..C 02C T 2 E X , PPPP 1111 .... 4321 T 2 , P 1 . 0 A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 P1.5 P1.6 P1.7 RST RXD, P3. INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVP TS4 AS. L 0 1 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 44 43 42 41 40 39 38 37 36 35 34 1 33 32 2 31 3 30 4 29 5 28 6 27 7 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS.. L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 -2- W78C54 PIN DESCRIPTION SYMBOL EA TYPE I DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. The ROM address and data will not be present on the bus if the EA pin is high and the program counter is within the 16 KB area. Otherwise they will be present on the bus. PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ALE OH ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. An ALE pulse is omitted during external data memory accesses. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. PORT 0: Function is the same as that of the standard 8052. PORT 1: Function is the same as that of the standard 8052. PORT 2: Function is the same as that of the standard 8052. PORT 3: Function is the same as that of the standard 8052. PORT 4: A 4-bit bi-directional parallel port and bit-addressable with internal pull-ups. Pin P4.3 and P4.2 have alternative function as external interrupt (INT2/INT3) source input. External interrupt 2: An extra interrupt input source. It cascades to pin P4.3 internally. External interrupt 3: An extra interrupt input source. It cascades to pin P4.2 internally. PSEN OH RST XTAL1 XTAL2 VSS VDD P0.0−P0.7 P1.0−P1.7 P2.0−P2.7 P3.0−P3.7 P4.0−P4.3 IL I O I I I/O D I/O H I/O H I/O H I/O H INT2 (P4.3) INT3 (P4.2) IH IH * Note : TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain -3- Publication Release Date: December 1997 Revision A2 W78C54 BLOCK DIAGRAM P1.0 ~ P1.7 Port 1 Port 1 Latch ACC B Port 0 Latch Port 0 INT2 Interrupt INT3 T1 Timer 2 Timer 0 Timer 1 UART PSW ALU T2 P0.0 ~ P0.7 DPTR Stack Pointer Temp Reg. PC Incrementor Addr. Reg. P3.0 ~ P3.7 Port 3 Port 3 Latch Instruction Decoder & Sequencer SFR RAM Address 16KB ROM 256 bytes RAM & SFR Port 2 Bus & Clock Controller Port 2 Latch P2.0 ~ P2.7 P4.0 ~ P4.3 Port 4 Port 4 Latch Oscillator Reset Block Power control XTAL1 XTAL2 ALE PSEN RST VCC GND Figure 2. Architecture of the W78C54 -4- W78C54 FUNCTIONAL DESCRIPTION The W78C54 is pin-to-pin compatible with the W78C52, except that the internal 8K mask ROM has been replaced with 16K of internal mask ROM. The processor supports 111 different opcodes and references both 64K program address space and 64K data storage space. Clock The W78C54 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78C54 relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78C54 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal is connected across pins XTAL1 and XTAL2. In addition, a load capacitance of 30 pf (typically) must be connected from each pin to ground. Resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level greater than 3.5 volts. Power Management Idle Mode The idle mode is entered by setting the IDLE bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a reset. Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C54 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. New Defined Peripheral In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt INT2, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows: -5- Publication Release Date: December 1997 Revision A2 W78C54 1. INT2 / INT3 Two additional external interrupts, INT2 and INT3, whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. 2. PORT4 Another bit-address port P4 is also available except only 4 bits (P4) can be used. This port address is located at 0D8H with the same function as that of port P1,except the P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2/INT3). Example: P4 MOV MOV SETB CLR REG P4, #0AH A, P4 P4.0 P4.1 0D8H ; Output data "A" through P4.0−P4.3. ; Read P4 status to Accumulator. ; Set bit P4.0 ; Clear bit P4.1 Reduce EMI Emission Because of the large on-chip mask-ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space.. POF Flag The Power-Off-Reset flag is set by on-chip circuitry when the VCC level rises from 0 to 5V. The POF bit can be set/cleared by software allowing a user to determine if the reset is the result of a power-on or a warm up by external reset. To avoid effect of POF flag, the power voltage must remain above 3V. Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78C52C: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. -6- W78C54 DESCRIPTIONS OF THE SPECIAL FUNCTION REGISTERS (SFRS) SYM. B ACC P4* DEFINITION B register Accumulator Port 4 ADDR. MSB (F7) (E7) (F6) (E6) - BIT ADDRESS, SYMBOL (F5) (E5) (F4) (E4) (F3) (E3) (DB) INT2 (F2) (E2) (DA) INT3 (D2) OV (D1) (F1) (E1) (D9) LSB (F0) (E0) (D8) RESET 00000000B 00000000B xxxx0000B F0H E0H D8H PSW Program status word D0H (D7) CY (D6) AC (D5) F0 (D4) RS1 (D3) RS0 (D0) P 00000000B TH2 TL2 RCAP2H RCAP2L T2CON T2 reg. high T2 reg. low T2 capture high T2 capture low Timer 2 control CDH CCH CBH CAH C8H (CF) TF2 (CE) EXF2 (C6) EX3 (B6) WR (AE) (A6) A14 (9E) SM1 (96) (CD) RCLK (C5) IE3 PT2 (B5) T1 (AD) ET2 (A5) A13 (9D) SM2 (95) (CC) (CB) (CA) TR2 (C2) EX2 PX1 (B2) INT0 (AA) EX1 (A2) A10 (9A) RB8 (92) (C9) C/T2 (C1) IE2 PT0 (B1) TXD (A9) ET0 (A1) A9 (99) TI (91) T2EX (C8) CP/RL2 00000000B 00000000B 00000000B 00000000B 00000000B TCLK EXEN2 (C4) IT3 PS (B4) T0 (AC) ES (A4) A12 (9C) REN (94) (C3) PX2 PT1 (B3) INT1 (AB) ET1 (A3) A11 (9B) TB8 (93) - XICON* External interrupt control Interrupt priority Port 3 C0H (C7) PX3 (C0) IT2 PX0 (B0) RXD (A8) EX0 (A0) A8 00000000B IP P3 B8H B0H (B7) RD xx000000B 11111111B IE Interrupt enable A8H (AF) EA 00000000B P2 Port 2 A0H (A7) A15 11111111B SBUF SCON* P1* AUXR* TH1 TH0 TL1 TL0 TMOD TCON PCON* DPH DPL SP P0 Serial buffer Serial control Port 1 Auxiliary Timer high 1 Timer high 0 Timer low 1 Timer low 0 Timer mode Timer control Power control Data pointer high Data pointer low Stack pointer Port 0 99H 98H 90H 8EH 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H (87) (86) (85) (84) (83) (82) (81) (80) GATE (8F) TF1 C/T (8E) TR1 M1 (8D) TF0 M0 (8C) TR0 POF+ GATE (8B) IE1 GF1 C/T (8A) IT1 GF0 M1 (89) IE0 PD M0 (88) IT0 IDL (9F) SM0/FE xxxxxxxxB (98) RI (90) T2 AO xxxxxxx0B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00xxxx00B 00000000B 00000000B 00000111B 11111111B 11111111B 00000000B (97) - SMOD SMOD0 -7- Publication Release Date: December 1997 Revision A2 W78C54 Note: In column BIT_ADDRESS, SYMBOL, containing ( ) item means the bit address. * SFRs modified or added to the W78C52. + Reset value depends on reset condition. W78C54 SFRs address location map: F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 Notes: 1. + SFR is bit-addressable. 2. is additional defined function. + ACC +P4 + PSW +T2CON +XICON + IP + P3 + IE + P2 + SCON + P1 + TCON +P0 TMOD SP TL0 DPL TL1 DPH TH0 TH1 AUXR PCON SBUF RCAP2L RCAP2H TL2 TH2 +B FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 Power-off Flag ***PCON - Power Control (87H) SMOD SMOD: SMOD0: bit. POF: SMOD0 POF GF1 GF0 PD IDL Double baud rate bit. When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2, 3. Enable FE bit in SCON. This bit is an alternative switch of SM0 and FE (Frame Error) When set to a 1, SCON.7 means a FE bit, otherwise a SM0 bit. Power off flag. Bit is set by hardware when power on reset. It can be cleared by software to determine chip reset is a warm boot or cold boot. Power down mode bit. Set it to enter power down mode. Idle mode bit. Set it to enter idle mode. GF1, GF0: These two bits are general-purpose flag bits for the user. PD: IDL: The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software. -8- W78C54 * Interrupts ***IE - Interrupt Enable (A8H) EA ET2 ES ET1 EX1 ET0 EX0 EA: Lobal interrupt enable flag ET2: Timer 2 overflow interrupt enable ES: Serial port interrupt enable EX1: External interrupt 1 enable ET1: Timer 1 overflow interrupt enable EX0: External interrupt 0 enable ***IP - Interrupt Priority (B8H) PT2 PS PT1 PX1 PT0 PX0 PT2: Timer 2 interrupt priority high if set PS: Serial port priority high if set PT1: Timer 1 interrupt priority high if set PX1: External interrupt 1 priority high if set PT0: Timer 0 interrupt priority high if set PX0: External interrupt 0 priority high if set ***XICON - External Interrupt Control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2 PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software The W78C54 supports an eight-source and a four-priority-level interrupt architectures. Besides the SFRs of IP and IE to control the six-source of the standard 8052 interrupt functions. There is an another SFR (XICON) to control the extra two-source of the external interrrupt (INT2 and INT3). This priority scheme is formed by combining IPH with IP to determine the priority of each interrupt. Except the INT2 and INT3, they are not defined in IP SFR but in XICON. -9- Publication Release Date: December 1997 Revision A2 W78C54 Following tables show the interrupt informations and priority definitions. Eight-source interrupt informations: INTERRUPT SOURCE External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt 2 External Interrupt 3 VECTOR ADDRESS 03H 0BH 13H 1BH 23H 2BH 33H 3BH POLLING SEQUENCE WITHIN PRIORITY LEVEL 0 (highest) 1 2 3 4 5 6 7 (lowest) ENABLE REQUIRED SETTINGS IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.EX2 XICON.EX3 INTERRUPT TYPE EDGE/LEVEL TCON.IT0 TCON.IT1 XICON.IT2 XICON.IT3 *Timer/Counter ***TL0, TH0, TL1, TH1, TL2, TH2, RCAP2L, RCAP2H ***TMOD - Timer 0, 1 mode (89H) GATE C//T M1 M0 GATE C//T M1 M0 TIMER0 TIMER1 GATE: C//T: 0 0 Gating control. When set, Timer/counter x is enabled only while INTx pin is high and TRx control pin is set. When cleared, Timer x is enabled whenever the TRx conrol bit is set. Timer or Counter Selector. Cleared for timer operation. Set for counter operation. M1 M0: Operating Mode 0: 13-bit Timer/Counter. 1: 16-bit Timer/Counter. 8-bit auto-reload Timer/Counter. THx holds a value which is to be reloaded into TLx each time it overflows. Timer 0: TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits. Timer 1: Timer/counter 1 stopped. ***TCON - Timer 0, 1 Control (88H) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 1 0: 1 1: TF1: Timer 1 overflow flag. Set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. - 10 - W78C54 TR1: Timer 1 run control bit. Set/cleared by software to turn timer/counter on or off. TF0: Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. TR0: Timer 0 run control bit. Set/cleared by software to turn timer/counter on or off. IE1: Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT1: Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt. IE0: Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT0: Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt. ***T2CON - Timer 2 Control (C8H) TF2 TF2: EXF2 RCLK TCLK EXEN2 TR2 C//T CP//RL2 Timer 2 overflow flag. Set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when RCLK = 1 or TCLK = 1. EXF2: Timer2 external flag. Set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. RCLK: Receive clock flag. RCLK = 1 causes the serial port to use Timer 2 overflow pulses for its receive clock in mode 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. TCLK: Transmit clock flag. TCLK = 1 causes the serial port to use Timer 2 overflow pulses for its transmit clock in mode 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for the transmit clock. EXEN2: Timer 2 external enable flag. EXEN2 = 1 allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. TR2: TR2 = 1/0: turns on/off Timer 2. C//T: Timer or Counter select. Set 1/0 for external event counter(falling edge triggered)/inter timer. CP//RL2: Capture/reload flag. *Reduced EMI Mode The AO bit in the AUXR register, when set, disables the ALE output. ***AUXR - Auxiliary Register (8EH) AO AO: Turn off ALE output. Publication Release Date: December 1997 Revision A2 - 11 - W78C54 ABSOLUTE MAXIMUM RATINGS PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VCC−VSS VIN TA TST MIN. -0.3 VSS -0.3 0 -55 MAX. +7.0 VCC +0.3 70 +150 UNIT V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC CHARACTERISTICS (VDD−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current P0, EA Logic 1 to 0 Transition Current P1, P2, P3, P4 Input Low Voltage P0, P1, P2, P3, P4, EA Input Low Voltage RST Input Low Voltage XTAL1[*4] SYM. VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL [*4] SPECIFICATION MIN. 4.5 -50 -10 -10 -500 MAX. 5.5 20 6 50 +10 +300 +10 -200 UNIT V mA mA µA µA µA µA µA TEST CONDITIONS No load VDD = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0V < VIN < VDD VDD = 5.5V VIN = 2.0V VIL1 VIL2 VIL3 0 0 0 0.8 0.8 0.8 V V V VDD = 4.5V VDD = 4.5V VDD = 4.5V - 12 - W78C54 DC Characteristics, continued PARAMETER Input High Voltage P0, P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1 [*4] Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN [*3] Sink Current P1, P2, P3, P4 Sink Current P0, ALE, PSEN Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN [*3] Source Current P1, P2, P3, P4 Source Current P0, ALE, PSEN Notes: SYM. VIH1 VIH2 VIH3 VOL1 VOL2 ISK1 ISK2 VOH1 VOH2 ISR1 ISR2 SPECIFICATION MIN. 2.4 3.5 3.5 4 10 2.4 2.4 -120 -10 MAX. VDD +0.2 VDD +0.2 VDD +0.2 0.45 0.45 8 14 -180 -14 UNIT V V V V V mA mA V V µA mA TEST CONDITIONS VDD = 5.5V VDD = 5.5V VDD = 5.5V VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +4 mA VDD = 4.5V Vs = 0.45V VDD = 4.5V Vs = 0.45V VDD = 4.5V IOH = -100 µA VDD = 4.5V IOH = -400 µA VDD = 4.5V Vs = 2.4V VDD = 4.5V Vs = 2.4V *1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 KΩ. *3. P0, ALE and /PSEN are tested in the external access mode. *4. XTAL1 is a CMOS input. *5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN approximates to 2V. AC CHARACTERISTICS The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.8 micron CMOS process when using 2 and 4 mA output buffers. - 13 - Publication Release Date: December 1997 Revision A2 W78C54 Clock Input Waveform XTAL1 T CH FOP, TCP TCL Continued PARAMETER Operating Speed Clock Period Clock High Clock Low SYMBOL FOP TCP TCH TCL MIN. 0 25 10 10 TYP. - MAX. 40 - UNIT MHz nS nS nS NOTES 1 2 3 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. Program Fetch Cycle External Program Memory Fetch Cycle (see Figure 6) PARAMETER Address Valid to ALE Low Address Hold After ALE Low ALE Low to PSEN Low PSEN Low to Data Valid Data Hold After PSEN High Data Float After PSEN High ALE Pulse Width PSEN Pulse Width SYMBOL TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW MIN. 1TCP -∆ 1TCP -∆ 1TCP -∆ 0 0 2TCP -∆ 3TCP -∆ TYP. 1TCP 2TCP 3TCP MAX. 1TCP+∆ 2TCP 1TCP 1TCP 2TCP +∆ 3TCP +∆ UINT nS nS nS nS nS nS nS nS 4 4 2 3 1 NOTES Notes: 1. P00-P07, P20-P27 remain stable through entire memory cycle. 2. Memory access time is 3 Tcp. 3. Data has been latched internally prior to /PSEN going high. 4. ∆ is 20 ns (due to buffer driving delay and wire loading). - 14 - W78C54 Data Read Cycle External Data Memory Read Cycle (see Figure 7) PARAMETER ALE Low to RD Low RD Low to Data Valid SYMBOL TDAR TDDA TDDH TDDZ TDRD MIN. 3 Tcp-∆ 0 0 6 Tcp-∆ TYP. 3 Tcp 6 Tcp MAX. 3 Tcp+∆ 4 Tcp 2 Tcp 2 Tcp 6 Tcp+∆ UINT nS nS nS nS nS NOTES 1, 2 1 Data hold After RD High Data Float After RD High RD Pulse Width 2 Notes: 1. Data Memory access time is 5 Tcp. 2. ∆ is 20 ns (due to buffer driving delay and wire loading. Data Write Cycle External Data Memory Write Cycle (see Figure 8) PARAMETER ALE Low to WR Low Data Valid to WR Low Data hold After WR High WR Pulse Width SYMBOL TDAW TDAD TDWD TDWR MIN. 3 Tcp-∆ 1 Tcp-∆ 1 Tcp-∆ 6 Tcp-∆ TYP. 3 Tcp 6 Tcp MAX. 3 Tcp+∆ 6 Tcp+∆ UINT nS nS nS nS NOTE * * *Note: ∆ is 20 ns (due to buffer driving delay and wire loading) Port Access Cycle Port Access Cycle (see Figure 9) PARAMETER Port Input Setup to ALE Low Port Input Hold After ALE Low Port Output to ALE High SYMBOL TPDS TPDH TPDA MIN. 1Tcp 0 1Tcp-∆ TYP. MAX. UINT nS nS nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. - 15 - Publication Release Date: December 1997 Revision A2 W78C54 TIMING WAVEFORMS Program Fetch Cycle S1 XTAL1 Talw S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 ALE Tapl PSEN Taas Tpsw Tpdh,Tpdz Code PCL out Code PCL out Code PCL out Taah Tpda P0 P2 Code PCL out PCH out PCH out PCH out PCH out Figure 6. External Program Memory Fetch Cycle Data Read Cycle S4 XTAL1 ALE PSEN DPL or RI out S5 S6 S1 S2 S3 S4 S5 P0 P2 Data DPH or P2 SFR out Tdar Tdda Tddh,Tddz /RD Tdrd Figure7. External Data Memory Read Cycle - 16 - W78C54 Timing Waveforms, continued Data Write Cycle S4 XTAL1 ALE PSEN DPL or RI out S5 S6 S1 S2 S3 S4 S5 P0 P2 Data DPH or P2 SFR out Tdaw Tdad Tdwd WR Tdwr Figure 8. External Data Memory Write Cycle Port Access Cycle S5 XTAL1 ALE Tpds Tpdh Tpda Data Out S6 S1 PORT Input Sample Output Clock Data In Figure 9. Port Access Cycle - 17 - Publication Release Date: December 1997 Revision A2 W78C54 APPLICATION CIRCUIT Expanded External Program Memory and Crystal VCC VCC 35 21 10u R CRYSTAL EA X1 X2 RESET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78C54 20 10 8.2K C1 C2 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 19 18 32 33 13 11 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 OC G Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 GND 1 11 14 15 16 17 2 3 4 5 6 7 8 9 74LS373 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 GND 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 1 20 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE 27512 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Figure A Table 1 Shows the typical values of off-chip components to configure the on-chip oscillator. Table 1. Off-chip components list CRYSTAL FREQ. 12 MHz 16 MHz 20 MHz 24 MHz 33 MHz 40MHz Notes: 1. Refer to Figure 10 for C1, C2 and R. 2. It is recommended that an oscillator be used as external clock source when operating freq. is above 35MHz. Apply the external clock signal to XTAL1, and leave XTAL2 float, as shown in Figure 10. C1 30 pF 30 pF 15 pF 15 pF 10 pF 5 pF C2 30 pF 30 pF 15 pF 15 pF 10 pF 5 pF R 6.8 KΩ 4.3 KΩ - 18 - W78C54 Application Circuit, continued Expanded External Data Memory and Oscillator VCC VCC OSCILLATOR 35 21 20 EA X1 X2 RESET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78C54 10u 8.2K 10 14 15 16 17 2 3 4 5 6 7 8 9 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 19 18 32 33 13 11 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND 3 4 7 8 13 14 17 18 1 11 D0 D1 D2 D3 D4 D5 D6 D7 OC G Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 74LS373 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 20 22 27 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WR 20256 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Figure B - 19 - Publication Release Date: December 1997 Revision A2 W78C54 PACKAGE DIMENSIONS 40-pin DIP Symbol Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15 0.670 0.090 14.986 13.72 2.286 3.048 0 16.00 16.51 0.254 3.81 0.406 1.219 0.203 3.937 0.457 1.27 0.254 52.20 15.24 13.84 2.54 3.302 4.064 0.559 1.372 0.356 52.58 15.494 13.97 2.794 3.556 15 17.01 2.286 5.334 D 40 21 E1 A A1 A2 B B1 c D E E1 e1 L a 1 20 E c eA S Notes: S A A2 A1 Base Plane Seating Plane L B B1 e1 a eA 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 44-pin PLCC HD D 6 1 44 40 Symbol 7 39 Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.185 0.020 0.145 0.026 0.016 0.008 0.648 0.648 0.150 0.028 0.018 0.010 0.653 0.653 0.155 0.032 0.022 0.014 0.658 0.658 0.508 3.683 0.66 0.406 0.203 16.46 16.46 3.81 0.711 0.457 0.254 16.59 16.59 3.937 0.813 0.559 0.356 16.71 16.71 4.699 E HE GE 17 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Notes: 0.050 0.590 0.590 0.680 0.680 0.090 BSC 0.630 0.630 0.700 0.700 0.110 0.004 1.27 14.99 14.99 17.27 17.27 2.296 BSC 16.00 16.00 17.78 17.78 2.794 0.10 0.610 0.610 0.690 0.690 0.100 15.49 15.49 17.53 17.53 2.54 L A2 A θ e Seating Plane GD b b1 A1 y 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. - 20 - W78C54 Package Dimensions, continued 44-pin QFP HD D Dimension in inch Dimension in mm Symbol 44 34 Min. Nom. Max. --0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7 Min. Nom. --0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6 Max. --0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08 1 33 E HE 11 12 e b 22 A A1 A2 b c D E e HD HE L L1 y θ Notes: c 0 7 A2 A A1 θ L L1 Detail F Seating Plane See Detail F y 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. 44-pin TQFP HD D Dimension in inch Dimension in mm Symbol 44 34 Min. --0.002 0.037 0.0039 0.004 0.390 0.390 0.025 0.468 0.468 0.018 --- Nom. --0.004 0.039 0.013 --0.394 0.394 0.031 0.472 0.472 0.024 0.039 Max. 0.047 0.006 0.041 0.015 0.008 0.398 0.398 0.036 0.476 0.476 0.030 --0.003 Min. --0.05 0.95 0.22 0.090 9.9 9.9 0.635 11.90 11.90 0.45 --- Nom. --0.10 1.00 0.32 --10.00 10.00 0.80 12.00 12.00 0.60 1.00 Max. 1.20 0.15 1.05 0.38 0.200 10.1 10.1 0.952 12.10 12.10 0.75 --0.08 1 33 E HE 11 12 e b 22 A A1 A2 b c D E e HD HE L L1 y θ Notes: c 0 7 0 7 A2 A A1 θ L L 1 Seating Plane See Detail F y 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. Detail F - 21 - Publication Release Date: December 1997 Revision A2 W78C54 Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792697 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 408-9436666 Voice & Fax-on-demand: 886-2-27197006 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 22 -