W78E354P

W78E354 MONITOR MICROCONTROLLER GENERAL DESCRIPTION The W78E354 is a stand-alone high-performance microcontroller ASIC specially designed for use in monitor control applications. Using the Winbond 0.8µ DPDM process, the W78E354 integrates an embedded 8031 microcontroller core, 16K bytes of Flash cell, 512 bytes of RAM and a number of dedicated hardware functions. These hardware functions include a 6-bit A/D converter, two/fourteen 12/8-bit PWM static DACs, one/three 12/8-bit PWM dynamic DACs, a sync processor, one DDC port, a watchdog timer and other custom glue logic. Additional special function registers are incorporated to control the on-chip peripheral hardware. The chip is used to control the interface signals of other devices in the monitor and to process the video sync signals. Because of high integration and the incorporation of Flash cell for program memory, the device offers the user the competitive advantages of low cost and reduced development time. FEATURES • 80C31 MCU core included • 16K bytes Flash OTP memory for program storage • Total 512 bytes of on-chip data RAM: 256 bytes accessed as in the 80C32, 256 bytes accessed as external data memory via "MOVX @Ri". • One SPI/RS232 port (a serial port of 8051 standard) • One external interrupt input • Two timers/counters • PWM DACs: − Two 12-bit PWM/BRM Static DACs − Fourteen 8-bit PWM Static DACs − One 12-bit PWM/BRM Dynamic DAC − Three 8-bit PWM Dynamic DACs • One 6-bit ADC with 4 multiplexed analog inputs • Sync Processor: − Horizontal & Vertical Polarity Detector − Sync Separator for composite sync − Horizontal & Vertical Frequency Counter − Programmable dummy frequency generator − Programmable H-clamp pulse output − SOA output (hardware H frequency change detection) • One DDC port (master/slave mode I C with two slave address reg., support DC1/DDC2B/DDC2B+) • One 8-bit Auto-reload timer for software time base 2 -1- Publication Release Date: April 1997 Revision A1 W78E354 • Watchdog Timer • Two 15 mA output pins for driving LEDs • Power down reset • Clock: DC to 20 MHz • Packaged in 68-pin PLCC, 48-pin DIP and 40-pin DIP PIN CONFIGURATIONS P 2 . 5 / S D A C 1 1 P 2 . 4 / S DS AD CA 1C 09 S D A C 8 SS DD AA CC 76 S D A C 5 P 4 . 6 S P PD 4V3A .D. C 5D7 4 S D A C 3 P 4 . 4 S D A C 2 S D A C 1 P 3 . 3 SDAC10 SDAC11 P2.6/SDAC12 P2.7/SDAC13 OSCOUT OSCIN VSS P2.0 P2.1 SDAC12 SDAC13 P2.2 P2.3/STP P3.4/T0 P3.5/T1 HIN VIN 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 66666666 987654 32 187654321 W78E354P (PLCC-68) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 SDAC0 BDDAC DDAC2 DDAC1 DDAC0 P4.3 VPP P4.2 VDD P1.5/SOA P1.4/HCLAMP P1.3/DSDA P1.2/DSCL P1.1 P1.0 P4.1 P4.0 22233333333334444 78901234567890123 H O U T V O U T B S D A C 0 B S D A C 1 P 3 . 0 / R X D P 3 . 1 / T X D RVVAAVAAT ESSDDADDe SSSCCACCs E A01 23t T / /C PL P1K 1. .7 6 P 3 . 2 / I N T 0 P 3 . 6 -2- W78E354 Pin Cinfigurations, continued SDAC5 SDAC6 SDAC7 P2.4/SDAC10 P2.5/SDAC11 P2.6/SDAC12 P2.7/SDAC13 OSCOUT OSCIN VSS P2.0 P2.1 P2.2 P2.3/STP P3.4/T0 P3.5/T1 HIN VIN HOUT VOUT BSDAC0 P3.0/RXD P3.1/TXD RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 V DD SDAC4 SDAC3 SDAC2 SDAC1 P3.3 SDAC0 BDDAC DDAC2 DDAC1 DDAC0 VPP P1.5/SOA P1.4/HCLAMP P1.3/DSDA P1.2/DSCL P1.1 P1.0 P3.6 P3.2/INT0 TestCLK VAA ADC0 VSSA SDAC5 SDAC6 SDAC7 P2.4/SDAC10 P2.5/SDAC11 P2.6/SDAC12 P2.7/SDAC13 OSCOUT OSCIN V SS P2.0 P2.1 P2.2 P2.3/STP HIN VIN HOUT VOUT BSDAC0 P3.0/RXD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD SDAC4 SDAC3 SDAC2 SDAC1 SDAC0 BDDAC DDAC0 VPP P1.5/SOA P1.4/HCLAMP P1.3/DSDA P1.2/DSCL P1.1 P1.0 P3.2/INT0 TestCLK ADC0 RESET P3.1/TXD W78E354E (DIP-48) W78E354 (DIP-40) PIN DESCRIPTION PIN NO. 68P 64P 48P 40P PIN NAME SDAC0 SDAC1 SDAC2 SDAC3 SDAC4 SDAC5 SDAC6 SDAC7 I/O TYPE I/O TEST NAME A0 A1 A2 A3 A4 A5 A6 A7 FUNCTIONAL DESCRIPTION 8-bit PWM static DAC output. Sink/Source current 4 mA/-4 mA. With slew rate control and output delay: 1. Delay about 5 nS: SDAC2, 5, 8, 11. 2. Delay about 10 nS: SDAC0, 3, 6, 9, 12. 3. Without delay: the others. --------------------------------------------------------- 60 62 63 65 66 3 4 5 57 59 60 61 62 1 2 3 42 44 45 46 47 1 2 3 35 36 37 38 39 1 2 3 6 7 10 11 19 20 4 5 8 9 17 18 - - SDAC8 SDAC9 SDAC10 SDAC11 SDAC12 SDAC13 O/P - * In the Flash/RAM-test mode (when the chip is in reset state): SDAC0−7: A0−A7 inputs. * In the functional test mode (CPU executes out of ext. program memory): SDAC0−7: A0−A7 outputs. -3- Publication Release Date: April 1997 Revision A1 W78E354 Pin Description, continued PIN NO. 68P 64P 48P 40P PIN NAME BSDAC0 BSDAC1 I/O TYPE I/O O/P TEST NAME A8 - FUNCTIONAL DESCRIPTION 12-bit PWM/BRM static DAC output. Sink/Source current 8 mA/-8 mA. With slew rate control and output delay: 1. Delay about 5ns: BSDAC1 2. Without delay: BSDAC0. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): BSDAC0: A8 input. * In the functional test mode (CPU executes out of ext. program memory): BSDAC0: A8 output. 29 30 27 28 21 - 19 - 56 53 38 33 DDAC0 I/O A9 8-bit PWM dynamic DAC output. Sink/Source current 8 mA/-8 mA. With slew rate control and output delay: 1. Delay about 5 nS: DDAC1. 2. Delay about 10 nS: DDAC2. 3. Without delay: DDAC0. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): DDAC0: A9 input. * In the functional test mode (CPU executes out of ext. program memory): DDAC0: A9 output. 57 58 54 55 39 40 - DDAC1 DDAC2 O/P - 59 56 41 34 BDDAC I/O A10 12-bit PWM/BRM dynamic DAC output. Sink/Source current 8mA/-8mA. With slew rate control. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): BDDAC: A10 input. * In the functional test mode (CPU executes out of ext. program memory): BDDAC: A10 output. -4- W78E354 Pin Description, continued PIN NO. 68P 64P 48P 40P PIN NAME ADC0 ADC1 ADC2 (P1.6) ADC3 (P1.7) I/O TYPE I/P TEST NAME - FUNCTIONAL DESCRIPTION Analog signal input channel to ADC. Alternate function: ADC2: P1.6 input (input only). ADC3: P1.7 input (input only). 36 37 39 40 34 35 37 38 26 - 23 - 46 47 44 45 31 32 26 27 P1.0 P1.1 I/O A13 A14 General purpose I/O. Open-drain, Sink current 2mA. Schmitt trigger I/P. No PMOS ESD cell. VIH = 3.0V (min), VIL = 1.5V (max) --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): P1.0 and P1.1: A13 and A14 inputs. * In the functional test mode (CPU executes out of ext. program memory): P1.0 and P1.1: do not output A13 and A14, but function in their normal operational state. 48 49 46 47 33 34 28 29 P1.2 (DSCL) P1.3 (DSDA) I/O A13CTRL A14CTRL General purpose I/O. Open-drain, Sink current 6mA. Schmitt trigger I/P. No PMOS ESD cell. VIH = 3.0V (min), VIL = 1.5V (max) Alternate function: P1.2: DDC port serial clock DSCL. P1.3: DDC port serial data DSDA. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): P1.2: A13CTRL input. P1.3: A14CTRL input. -5- Publication Release Date: April 1997 Revision A1 W78E354 Pin Description, continued PIN NO. 68P 64P 48P 40P PIN NAME P1.4 (HCLAMP) I/O TYPE I/O TEST NAME A9CTRL FUNCTIONAL DESCRIPTION General purpose I/O. Sink/Source current 4 mA/-100 µ A. Alternate function: P1.4: HCLAMP (H-clamp pulse) output. While outputing special function, P1.4's Sink/Source current is 4 mA/-4 mA. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): P1.4: A9CTRL input. 50 48 35 30 51 49 36 31 P1.5 (SOA) I/O A11 General purpose O/P. Sink/Source current 4 mA/-4 mA. Alternate function: P1.5: SOA (Safe Operation Area) outpout. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): P1.5: A11 input. * In the functional test mode (CPU executes out of ext. program memory): P1.5: doesn't output A11, but functions as its normal operation. 17 18 15 16 11 12 11 12 P2.0 P2.1 I/O D0 D1 General purpose I/O. Sink/Source current 15mA/-100µ A. With slew rate control . --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): P2.0−P2.1: D0−D1 data inputs/outputs. * In the functional test mode (CPU executes out of ext. program memory): P2.0−P2.1: D0−D1 program inputs. -6- W78E354 Pin Description, continued PIN NO. 68P 64P 48P 40P PIN NAME P2.2 P2.3 (STP) P2.4 (SDAC10) P2.5 (SDAC11) P2.6 (SDAC12) P2.7 (SDAC13) I/O TYPE I/O TEST NAME D2 D3 D4 D5 D6 D7 FUNCTIONAL DESCRIPTION General purpose I/O. Sink/Source current 4 mA/-100 µ A. Alternate function: P2.3: STP (Self-Test Pattern) output. P2.4−P2.7: SDAC10−13 outputs. While outputing special function, P2.3−P2.7's Sink/Source current is 4mA/-4mA. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): P2.2−P2.7: D2−D7 data inputs/outputs. * In the functional test mode (CPU executes out of ext. program memory): P2.2−P2.7: D2−D7 program inputs. 21 22 8 9 12 13 19 20 6 7 10 11 13 14 4 5 6 7 13 14 4 5 6 7 31 32 42 29 30 40 22 23 29 20 21 25 P3.0 (RXD) P3.1 (TXD) P3.2 (INT0) I/O A12 (PSEN) - General purpose I/O. Sink/Source current 2 mA/-100 µ A. Alternate function: P3.0: 8051 serial input port. P3.1: 8051 serial output port. P3.2: External interrupt input. P3.4 and P3.5: Timer/counter 0 and 1 external inputs. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): P3.2: A12 input. * In the functional test mode (CPU executes out of ext. program memory): P3.2: PSEN output (the read strobe to external program memory) instead of A12. 61 23 24 43 67 58 21 22 41 63 43 15 16 30 - - P3.3 P3.4 (T0) P3.5 (T1) P3.6 P3.7 - -7- Publication Release Date: April 1997 Revision A1 W78E354 Pin Description, continued PIN NO. 68P 64P 48P 40P PIN NAME P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 HIN VIN I/O TYPE O/P TEST NAME - FUNCTIONAL DESCRIPTION Output port (Latch output). Sink/Source current 2 mA/-2 mA. 44 45 53 55 64 1 2 25 26 42 43 51 23 24 17 18 15 16 I/P OE CE HIN: Hsync/Composite sync input. VIN: Vsync input. Schmitt trigger I/P. With Internal high value pull-down (about 200 KΩ). No PMOS ESD diode. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): HIN: OE input. VIN: CE input. 27 28 25 26 19 20 17 18 HOUT VOUT I/O OECTRL PROG HOUT: Hsync output. VOUT: Vsync output with internal weak pull-up (above 200 KΩ). Sink/Source current 4 mA/-4 mA. --------------------------------------------------------* In the Flash/RAM-test mode (when the chip is in reset state): HOUT: OECTRL input. VOUT: PROG input. 33 31 24 22 RESET I/P - Reset the controller (active low). Schmitt trigger I/P. With internal pull-up (about 30 KΩ). 41 39 28 24 TestCLK I/P EA Clock input while in internal (glue logic's) function test. With internal pull-up (about 30 KΩ). --------------------------------------------------------* If the EA (TestCLK) pin is pulled low when the chip is being reset, and remains low for at least 24 clock periods after the reset, the CPU will execute from the external program memory regardless of the PC value. i.e., the CPU is forced to enter the functional test mode. -8- W78E354 Pin Description, continued PIN NO. 68P 64P 48P 40P PIN NAME OSCOUT OSCIN I/O TYPE O/P I/P TEST NAME - FUNCTIONAL DESCRIPTION Output from the inverting oscillator amplifier. Input to the inverting oscillator amplifier. Freq.: 16 MHz to 24 MHz. 14 15 12 13 8 9 8 9 54 68 16 52 52 64 14 50 37 48 10 - 32 40 10 - VPP VDD VSS VDD - VPP - In the Test/Flash mode, this pin is the power supply input for the Flash cell. Positive digital power supply, +5V. Digital ground. Positive digital power supply, +5V. Internally connected to the other power source. 34 32 - - VSS - - Digital ground. Internally connected to the other power source. 38 35 36 33 27 25 - VAA VSSA - - Positive analog power supply, +5V. Analog ground. -9- Publication Release Date: April 1997 Revision A1 W78E354 BLOCK DIAGRAM W78E354 V DD VSS Power Source Supervisor 8031 MCU core with 256B Scratchpad RAM 16KB Flash ROM Vpp RESET Reset Circuit WDT OSCIN OSC/Timing Generator OSCOUT 256B Data Memory Interrupt Processor INT0 (P3.2) SDAC HIN, VIN HOUT, VOUT HCLAMP (P1.4) SOA (P1.5) RXD (P3.0) TXD (P3.1) DDAC Sync Processor ADC SDAC0~13 BSDAC0~1 DDAC0~2 BDDAC ADC0~3 V AA, VSSA Srial Port T0 (P3.4) T1 (P3.5) Timer 0 Timer1 Autoload Timer DDC DSCL (P1.2) DSDA (P1.3) Port 1, 2, 3 (except P1.5) P1.5, Port 4 I/O Port - 10 - W78E354 FUNCTIONAL DESCRIPTION A. 80C31 Core The W78E354's 80C31 (CMOS MCU) core architecture consists of a CPU surrounded by various Special Function Registers or SFRs. Some of these SFRs are standard 80C31 registers while others are new additions, cf. Table 1. The device includes three general purpose I/O ports (P1, P2 and P3), one output-only port (P4), 256 bytes of scratchpad RAM, two timer/counters (Timer0 and Timer1) and one 8051 standard serial port. The processor supports 109 different instructions (without "MOVX A,@DPTR" and "MOVX @DPTR,A") all of which are compatible with those of the MCS-51 family. One distinguishing feature of the device architecture is the SFR address space into which all the registers, peripherals and scratchpad RAM are mapped. Many of the instructions operate on an SFR address rather than a specific register, greatly increasing the power of the instruction set. The core controller has been designed around a state machine rather than utilizing a microcode approach, a design methodology which offers several advantages. The first of these is that faster circuits can be produced due to the fact that flip-flops are inherently faster than ROMs. Secondly, a ROM-free approach allows the design to be directly utilized in ASIC gate array implementations, an important factor for cost reductions. Finally, an entire digital logic approach provides better supply noise immunity in most applications. Table 1. W78E354's Special Function Registers (SFRs) F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 + IP + P3 + IE + P2 + SCON + P1 + TCON + CONTREG1 SBRM0 ADC SDAC7 SDAC0 SBUF AUTOLOAD TMOD SP SBRM1 INTVECT SDAC8 SDAC1 BSDAC0 DHREG TL0 DPL PORT4 STATUS SDAC9 SDAC2 BSDAC1 DVREG TL1 DPH SOAREG HFCOUNTL SDAC10 SDAC3 WDTCLR DDC1 TH0 CONTREG5 SOACLR HFCOUNTH SDAC11 SDAC4 DDAC0 INTMSK TH1 CONTREG2 VFCOUNTL SDAC12 SDAC5 DDAC1 BDDAC PARAL CONTREG3 VFCOUNTH SDAC13 SDAC6 DDAC2 DBRM PARAH PCON + ACC + S1CON + PSW + CONTREG4 S1STA S1DAT S1ADR +B FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 Notes: 1. The SFRs with a "+" are both byte- and bit-addressable. 2. The registers in the shaded region are new additions to the 80C31 SFRs. A.1 Address Space (cf. Figure 1) The W78E354 CPU operates out of three separate address spaces: - 11 - Publication Release Date: April 1997 Revision A1 W78E354 1. The first of these is the internal program space (internal Flash memory) with 16K byte size (0000H− 3FFFH). The program space can be accessed by both opcode fetches and the "MOVC" instructions. 2. The second is referred to as the data memory space and has a size of 256 bytes (0000H−00FFH). The data memory is integrated within the chip rather than being outside as in the case of the standard 8031. The "inside" data memory space is accessed by the "MOVX @Ri" instruction. 3. The third address space has 256 locations while it is used by 384 bytes (256 bytes of RAM and 128 bytes of SFRs). • The lower 128 locations of this address space (00H−7FH) are for the lower 128 bytes of scratchpad RAM. Any of these 128 bytes may be used by a programmer but some of them have special uses. The lowest 32 bytes are organized to four 8-byte register banks. The bank select bits (RS0 and RS1 in the PSW register) selects one of these four banks which is to be used currently as an operand in the instruction set. Registers 0 to 7 in the bank are referenced by the register direct opcodes. Registers 0 and 1 may also contain an address that is referenced by the register indirect opcodes. • The higher 128 locations of this address space (80H−FFH) are shared by the higher 128 bytes of scratchpad RAM and the Special Function Registers (SFRs). The SFRs are accessed only by "direct" addressing while the higher 128 bytes of scrachpad RAM are accessed only by "indirect" addressing. The higher 128 bytes of scratchpad data RAM are also available for stack space. Address spaces 20H to 2FH are bit-addressable and can be used by the Boolean Variable Manipulation instructions. For example, bit 0 of address 20H has a Boolean address 00H, and bit 7 of address 2FH has a Boolean address 7FH. The higher Boolean addresses (80H−FFH) are mapped into the SFR address space. To determine a Boolean address in some bit-addressable SFR, the higher 5 bits of the SFR's address can be combined with the 3 lower bits that specify the desired bit in the SFR. On-Chip Program Memory 3FFFH On-Chip Data Memory FFH FFH SFR Scratchpad RAM (Direct Addressing) (Indirect Addressing) (MOVX @Ri) 80H 7FH Scratchpad RAM (Direct/Indirect Addressing) 0000H 00H 00H Figure1. Addres Space - 12 - W78E354 A.2 The Modified 80C31 SFRs 1. Timer/Counter Control Register: TCON BIT TCON.7 NAME TF1 Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when the processor vectors to the interrupt routine. TCON.6 TCON.5 TR1 TF0 Timer 1 run control bit. Set/cleared by software to turn the timer/counter on or off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when the processor vectors to the interrupt routine. TCON.4 TCON.3 TCON.2 TCON.1 TR0 IE0 Timer 0 run control bit. Set/cleared by software to turn the timer/counter on or off. (Reserved, not used by users.) (Reserved) Interrupt 0 edge flag. Set by hardware when an external interrupt edge is detected. Cleared when the interrupt is processed. TCON.0 IT0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt. 2. Power Control Register: PCON BIT 7 6 5 4 NAME SMOD Double baud rate bit. (Reserved) (Reserved, not used by users.) (Reserved for testing, not used by users. Normally 0. If set, P2.4−P2.7 will output SDAC8-11 after reset (not poweron reset).) 3 2 1 0 GF1 GF0 PD IDL General-purpose flag bit. General-purpose flag bit. Power-down mode bit. Idle mode bit. FUNCTION FUNCTION - 13 - Publication Release Date: April 1997 Revision A1 W78E354 3. Interrupt Enable Register: IE BIT IE.7 NAME EA FUNCTION If EA = 0, no interrupt will be acknowledged (disable all interrupts). If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 Notes: *1: No name for ASSEMBLER, must be used via "IE.x". *2 = (DSCLINT + ADCINT + TIMEOUT + SOAINT + VEVENT + PARAINT + DDC1INT). *1 ES ET1 *1 ET0 EX0 (Reserved) Set/clear to enable/disable the DDC port's I2C interrupt. Set/clear to enable/disable the serial port 0 interrupt. Set/clear to enable/disable the Timer 1 overflow interrupt. Set/clear to enable/disable the *2 interrupt. Set/clear to enable/disable the Timer 0 overflow interrupt. Set/clear to enable/disable the external interrupt 0. 4. Interrupt Priority Register: IP BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 Notes: *1: No name for ASSEMBLER, must be used via "IP.x". *2 = (DSCLINT + ADCINT + TIMEOUT + SOAINT + VEVENT + PARAINT + DDC1INT). NAME *1 PS PT1 *1 PT0 PX0 (Reserved) (Reserved) FUNCTION Define the DDC port's I2C interrupt priority level. If IP.5 = 1, the priority level is higher. Define the serial port interrupt priority level. If PS = 1, the priority level is higher. Define the Timer 1 interrupt priority level. If PT1 = 1, the priority level is higher. Define the *2 priority level. If IP.2 = 1, the priority level is higher. Define the Timer 0 interrupt priority level. If PT0 = 1, the priority level is higher. Define the external interrupt 0 priority level. If PX0 = 1, the priority level is higher. - 14 - W78E354 A.3 New Register Description In addition to the 80C31 standard SFRs, the W78E354 has some newly added Special Function Registers in the SFR address space as listed in Table 2. Table 2. Newly Added Special Function Registers (SFRs) REGISTER ADDRESS LENGTH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CONTREG1 CONTREG2 CONTREG3 CONTREG4 CONTREG5 SDAC0 SDAC1 SDAC2 SDAC3 SDAC4 SDAC5 SDAC6 SDAC7 SDAC8 SDAC9 SDAC10 SDAC11 SDAC12 SDAC13 BSDAC0 SBRM0 BSDAC1 SBRM1 DDAC0 DDAC1 DDAC2 BDDAC DBRM HFCOUNTL HFCOUNTH 80H 85H 86H C8H 84H A1H A2H A3H A4H A5H A6H A7H A9H AAH ABH ACH ADH AEH AFH 9AH B9H 9BH BAH 9DH 9EH 9FH 96H 97H B4H B5H 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 4 8 4 8 8 8 8 4 8 8 R/W TYPE R/W W W R/W R/W W W W W W W W W W W W W W W W W W W W W W W W R R RESET CONTENT 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 REGISTER VFCOUNTL VFCOUNTH DHREG DVREG PARAL PARAH AUTOLOAD WDTCLR SOAREG SOACLR INTMSK INTVECT STATUS ADC PORT4 DDC1 S1CON S1STA S1DAT S1ADR ADDRESS LENGTH B6H B7H 92H 93H 8EH 8FH 91H 9CH BCH BDH 95H B2H B3H B1H BBH 94H D8H D9H DAH DBH 8 8 4 8 8 8 8 8 8 8 4 8 7 8 8 8 8 8 R/W TYPE R R W W W W W W W W W R/W R R W W R/W R R/W R/W RESET CONTENT 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 80H 00H 00H 00H F8H 00H 00H Note: '-' means the SFR has no real hardware but an address. - 15 - Publication Release Date: April 1997 Revision A1 W78E354 * CONTREG1: Control register1, bit-addressable. BIT 0 1 2 3 4 5 6 7 NAME ADCS0 ADCS1 ENDDC1 HCES HCWS0 HCWS1 DUMMYEN ADCSTRT FUNCTION ADC channel Select bit 0 ADC channel Select bit 1 Enable DDC1 H-Clamp Edge Select H-Clamp Width Select bit 0 H-Clamp Width Select bit 1 Dummy signal Enable Start ADC conversion 0: Stop, 1: Start NOTE See Section E.10. See Section E.10. See below. See Section E.12.f. See Section E.12.f. See Section E.12.f. See Section E.12. 'Sync Processor Block Diagram' & E.12.e. See Section E.10. DDC Port I 2C IN SCL OUT P1.2/DSCL IN SDA OUT P1.3/DSDA 0 Support DDC2B/2B+ 1 DDC1 SDA SCL Support DDC1 OUT from Vsync ENDDC1 - 16 - W78E354 * CONTREG2: Control register2. BIT 0 1 2 3 4 NAME ENVS HSPS VSPS OSCSEL EINTES FUNCTION ENable Vsync Separator HSync Polarity Select 0: Positive, 1: Negative VSync Polarity Select 0: Positive, 1: Negative OSC or OSC/2 SELect External INT Edge Select 0: High-level/rising-edge triggered 1: Low-level/falling-edge triggered 5 6 7 ENM0 ENM1 VDISHC ENable SDAC0 Moire cancel function 0: Disable, 1:Enable ENable SDAC1 Moire cancel function 0: Disable, 1:Enable Vsync DISable H-Clamp pulse 0: Enable, 1:Disable See Section E.12. 'Sync Processor Block Diagram'. NOTE See Section E.12. 'Sync Processor Block Diagram' & E.12.e. See Section E.12. 'Sync Processor Block Diagram'. See Section E.12. 'Sync Processor Block Diagram'. See below. See below. OSCSEL OSCOUT OSCIN Divided by 2 To CPU core 0 To Sync processor 1 EINTES INT0 (P3.2) 1 0 0 1 IT0 IE0 - 17 - Publication Release Date: April 1997 Revision A1 W78E354 *CONTREG3: Control register3. BIT 0 1 2 3 4 5 6 NAME P4SF TSTMOD1 TSTMOD2 TSTMOD3 TVSEP FUNCTION Port 4 Special Function Function test mode1 Function test mode2 Function test mode3 Test VSEP signal (Reserved for internal use.) (Reserved for internal use.) (Reserved for internal use.) NOTE 7 *CONTREG4: Control register4, bit-addressable. BIT 0 1 2 3 4 5 6 7 NAME P24SF P25SF P26SF P27SF P14SF P15SF P23SF INVSTP FUNCTION Port 2.4 Special Function* (SDAC10) Port 2.5 Special Function* (SDAC11) Port 2.6 Special Function* (SDAC12) Port 2.7 Special Function* (SDAC13) Port 1.4 Special Function* Port 1.5 Special Function* Port 2.3 Special Function* Invert Self-Test Pattern NOTE See below. See below. See below. See below. See below. See below. See below. *Note:In addition to setting PxySF, the port latch Pxy must have been cleared previously to enable the Pxy output special functions. P14SF P1.4 latch H-Clamp pulse P15SF 0 P1.5 latch 0 P1.4/HCLAMP 1 SOA output P1.5/SOA 1 - 18 - W78E354 P2mSF P2.m latch SDACn P23SF 0 P2.m/SDACn mn 4 5 6 7 10 11 12 13 1 P2.3 latch STP output 0 P2.3/STP 1 *CONTREG5: Control register5. BIT 0 1 2 3 4 5 6 7 HDSEL DPARAINT HCLAMP Source SELect Enable parabola with dummy Sync. NAME FUNCTION NOTE * STATUS: Status register. BIT 0 1 2 3 NAME HP VP NOH NOV FUNCTION Hsync polarity. 0: Positive, 1: Negative. Vsync polarity. 0: Positive, 1: Negative. Set by hardware if no Hsync. Set by hardware if no Vsync. - 19 - Publication Release Date: April 1997 Revision A1 W78E354 * INTMSK: Interrupt mask register. BIT 0 1 2 3 4 5 6 7 Note: A '1' in any bit of the INTMSK register enables the corresponding interrupt flag in INTVECT to be set by hardware when the interrupt source generates an interrupt. NAME DSCLINTmsk ADCINTmsk TIMEOUTmsk SOAINTmsk VEVENTmsk PARAINTmsk DDC1INTmsk FUNCTION Set/clear to enable/disable DSCLINT interrupt. Set/clear to enable/disable ADCINT interrupt. Set/clear to enable/disable TIMEOUT interrupt. Set/clear to enable/disable SOAINT interrupt. Set/clear to enable/disable VEVENT interrupt. Set/clear to enable/disable PARAINT interrupt. Set/clear to enable/disable DDC1INT interrupt. * INTVECT: Interrupt vector register. BIT 0 1 2 3 4 5 6 7 Note: To clear the interrupt flag, write a '1' (not '0') to the corresponding bit in INTVECT register. NAME FUNCTION NOTE See Section E.6. See Section E.10. See Section E.8. See Section E.12.g. VSEP NOV VEVENT DSCLINT Set by hardware when DSCL is toggled from High to Low and kept Low for at least 12/Fosc sec. ADCINT Set by hardware when ADC conversion is completed. TIMEOUT Set by hardware when Autoload timer timeout. SOAINT VEVENT Set by hardware when SOA is High. Set by hardware when Vsync or Vertical frequency counter timeout. PARAINT For parabola interrupt generator (set by hardware). DDC1INT For DDC1 of DDC port (set by hardware). See Section E.9. See Section E.6. * PARAL: Parabola interrupt generator register, low byte. * PARAH: Parabola interrupt generator register, high byte. * AUTOLOAD: 8-bit Auto-reload timer register. (See Section H.) * DHREG: Dummy Hsync frequency generator register. (See Section L.e.) * DVREG: Dummy Vsync frequency generator register. (See Section L.e.) * DDC1: DDC port's DDC1 data buffer. * DDAC0−DDAC2: 8-bit PWM dynamic DAC register. (See Section K.) * BDDAC (8 bits)+DBRM (4 bits): 12-bit PWM/BRM dynamic DAC register. (See Section K.) * SDAC0−SDAC13: 8 bits, 8-bit PWM static DAC register. (See Section K.) * BSDAC0 (8 bits)+SBRM0 (4 bits): 12-bit PWM/BRM static DAC register. (See Section K.) - 20 - W78E354 * BSDAC1 (8 bits)+SBRM1 (4 bits): 12-bit PWM/BRM static DAC register. (See Section K.) * WDTCLR: Watchdog-timer-clear register, no specific hardware but an address. Writing any value to WDTCLR will clear the watchdog timer. * ADC: Result of the A-to-D conversion. * HFCOUNTL: Horizontal frequency counter register, low byte. (See Section L.d.) * HFCOUNTH: Horizontal frequency counter register, high byte. (See Section L.d.) * VFCOUNTL: Vertical frequency counter register, low byte. (See Section L.d.) * VFCOUNTH: Vertical frequency counter register, high byte. (See Section L.d.) * PORT4: Latch outputs (output only). * SOAREG: Safe-Operation-Area register. (See Section L.g.) * SOACLR: Safe-Operation-Area Clear register, no specific hardware but an address. Writing anyvalue to SOACLR will clear the SOA output (P1.5). * S1CON: Serial Port 1 Control Register. * S1STA: Serial Port 1 Status Register. * S1DAT: Serial Port 1 Data Register. * S1ADR: Serial Port 1 Address Register. B. 16K Bytes Flash Memory Programming the Flash memory will be described in section F. C. 256 Bytes of On-Chip Data Memory This data memory is mapped to external locations 00H to FFH and can only be accessed by the "MOVX @Ri" instruction. Since no external data can be accessed by this chip, there is no need for the external memory read/write control signals ( RD , WR ) as the "MOVX @Ri" instruction can only be executed internally. D. SPI (Synchronous Peripheral Interface) and RS232 Port: Serial Port 0 P3.0(RXD) and P3.1(TXD) can be used as a SPI port (serial port mode 0 of standard 80C51) or a RS232 port (mode 1, 2 or 3). • The SPI port can be used to communicate to OSD chip, DAC ... • An RS232 port can be used to talk to auto-alignment system, by using an 18.432 MHz crystal, aximun baud rate is 19200 bpS. E. DDC Port (support DDC1/2B/2B+, with two slave address registers) • One DDC1 port to support DDC1 • One I2C port support DDC2B/2B+: Serial Port 1 An Interrupt is generated when DSCL has a transition from high to low and then remains low for 12 clock periods. Publication Release Date: April 1997 Revision A1 - 21 - W78E354 16 MHz DSCL Low 750 nS 18.432 MHz 651 nS 20 MHz 600 nS 24 MHz 499 nS F. I2C Port: Serial Port 2 (S/W emulation). G. Interrupts The W78E354 has 6 interrupt sources. Five of them, with the exception of INT1 (at vector address 0013H) are identical to those of the 8051 series. The remaining one (at vector address 002BH) is a new addition. All the interrupt sources and the corresponding interrupt vector addresses for the W78E354 are given in the following table: SOURCE 1 2 3 4 5 6 Notes: *1 = DSCLINT + ADCINT + TIMEOUT + SOAINT + VEVENT + PARAINT + DDC1INT. *2 is the interrupt generated by the I2C in the DDC port. VECTOR DDRESS 0003H 000BH 0013H 001BH 0023H 002BH DESCRIPTION Same as the 8051. Same as the 8051. Replaces INT1 of the 8051. Same as the 8051. Same as the 8051. New addition. (like TF2 + EXF2 in the 8052) PRIORITY WITHIN A LEVEL Highest IE0 TF0 *1 TF1 RI+TI *2 Lowest The interrupt at vector address 0013H is driven by another seven different sources. These are 1) a High-to-low transition of the DSCL-pin, 2) the A/D converter, 3) the Auto-reload Timer, 4) the SOA output, 5) Vsync, 6) the Parabola interrupt generator, and 7) DDC1 in the DDC port. The programmer must read the INTVECT register to identify the interrupt request source. These seven sources can be masked individually by setting the corresponding bit within the INTMSK register (Bit0..6). The newly added interrupt at vector address 002BH is driven by the I2C circuit in the DDC port. The interrupt enable control bits for the two interrupts at 0013H and 002BH are the bits IE.2 and IE.5 in the IE register, respectively. They can be disabled by clearing IE.7 (disable all interrupts). The interrupt priority control bits are IP.2 and IP.5 in the IP register, respectively. The following diagram illustrates the above description. - 22 - W78E354 Vector Address IE 0003H IE.0 IP IP.0 IP.1 INTMSK INTVECT DSCLINT source ADCINT source TIMEOUT source SOAINT source VEVENT source PARAINT source DDC1INT source Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 IE0 TF0 High Priority Low Priority 000BH IE.1 DSCLINT ADCINT TIMEOUT SOAINT VEVENT PARAINT DDC1INT Interrupt Polling Sequence OR 0013H IE.2 IP.2 I2C in DDC port TF1 RI+TI 001BH IE.3 IP.3 IP.4 IP.5 IE.7 0023H IE.4 002BH IE.5 H. 8-bit Auto-reload Timer for Software Time Base This is an 8-bit auto-reload timer, which generates a periodic interrupt to the CPU. The time interval is programmable: The minimun interval (unit) = 1/ (Fclock ÷ 1024), the programmable interval = the minimun interval × (AUTOLOAD Reg. value +1), the maximum interval = the minimun interval × 255. 16 MHz Minimum Interval Maximum Interval 64 µS 16.3 mS 18.432 MHz 55 µS 14.2 mS 20 MHz 51.2 µS 13.1 mS 24 MHz 42.6 µS 10.9 mS I. Parabola interrupt generator This is an 16-bit auto-reload timer, which generates a periodic interrupt to the CPU. The interrupt period is programmable: the time base = 1/Fclock, the programmable interrupt period = the time base × ([PARAH, PARAL] 16-bit Reg. value+1), the maximum period = the time base × 65535. J. 6-bit ADC One 6-bit Analog-to-Digital Converter. SPEC.: • ±1 LSB - 23 - Publication Release Date: April 1997 Revision A1 W78E354 • Conversion time: > TPWM b. 2 channels of 12-bit Static DAC The two channel, 12-bit PWM outputs are composed of an 8-bit PWM and a 4-bit BRM (Bit Rate Multiplier). The 4-bit BRM Reg. value decides which one is to be added one clock preiod in every 16 PWM outputs. BRM Reg. 4-bit data One clock period is incremented in the n-th output in every 16 PWM outputs. 0000 0001 0010 0100 1000 None n=8 n = 4, 12 n = 2, 6, 10, 14 n = 1, 3, 5, 7, 9, 11, 13, 15 Note: See the positions marked with an "*" in the following figure. BRM Reg. value 0 0001 0010 0100 1000 1 * 2 * 3 * 4 * 5 * * - BRM Cycle 6 7 * 8 * 9 * 10 * 11 * 12 * 13 * 14 * 15 * Example: 0000 0011 1111 * * * * * * * * * * * * * * * * * * The 12-bit PWM frequency is the same as that of the 8-bit PWM output. - 25 - Publication Release Date: April 1997 Revision A1 W78E354 c. 1 channel of 12-bit & 3 channels of 8-bit Dynamic DAC The Dynamic DACs are used to generate a parabola waveform for geometric compensation. DDAC application circuit: D1616 2.5V 8/12 bit resolution DDAC Balanced/Unbalanced Parabola Geometry compensation parabola waveform: DDAC0 can be used to compensate H size distortion: 1. PinCushion Correction (amplitude) (PCC amplitude) 2. Trapezoid (Keystone) 25% 3. CBOW (S-comp) 25% 4. PinCushion correction (corner) (PCC corner) The PCC amplitude can be compensated against V size adjustment automatically. The Trapezoid can be compensated against V center adjustment automatically. DDAC1 is used to compensate H center distortion: 1. Pin balance (Bow) 2. Key balance (Tilt) Note: The unused dynamic DACs can be used as static DACs. - 26 - W78E354 L. Sync Processor Sync Processor Block Diagram VSPS HSPS DUMMYEN ENVS 0 VIN H IN Digital Filter Polarity Detect & Restoration VREST HREST Vsync Separator VSEP 1 0 1 0 V OUT 1 AD[7:0 ] H/V Frequency Counter VDUMMY H/V Dummy Sync Generator 0 HDUMMY 1 0 H OUT 1 H-Clamp SOA VDISHC H-Clamp Generator SOA Generator a. H/V Sync Digital Filter Both Hsync and Vsync inputs have an internal digital filter to improve noise immunity. Any pulse that is shorter than an internal clock period will be regarded as a glitch and will be ignored. Ex: Tclock = 62 nS @16 MHz, any sync with pulse width less than 62 nS will be regarded as a glitch. b. Polarity Detector The H/V polarity is detected automatically and can be read from the STATUS register, the H/V input signals are then polarity restored (become HREST/VREST) for internal processing and output to HOUT/VOUT to drive the deflection circuit. The maximun sync width to HIN pin is: (1/Fclock ) × 16384 The maximun sync width to VIN pin is: (1/Fclock ) × 16384 FCLOCK Max. sync width for HIN Max. sync width for VIN 16 MHz 1024 µS 1024 µS 18.432 MHz 888 µS 888 µS 20 MHz 819 µS 819 µS 24 MHz 681 µS 681 µS - 27 - Publication Release Date: April 1997 Revision A1 W78E354 c. Sync Separator Hsync/ Composite Sync H IN H OUT To deflection circuit Vsync V IN V OUT Vsync Separator Output (VOUT = VSEP when DUMMYEN = 0, ENVS = 1): H IN V IN Tdelay Wvmin V OUT H IN (H+V) V IN V OUT The Vsync is separated from the composite sync automatically, without any software effort. The limitation for the Vsync signal is: the VIN pulse width must be larger than Wvmin = (1/Fclock) × 128.5, +/- 1/Fclock ÷ 2 VOUT is also delayed from the VIN signal by Tdelay = (1/Fclock) × 128.5, +/- 1/Fclock ÷ 2 (if ENVS bit is set to 1) FCLOCK 1/Fclock Min. Vsync Width (Wvmin) VOUT Delay from VIN (Tdelay) 16 MHz 62.5 nS 18.432 MHz 54 nS 20 MHz 50 nS 24 MHz 41 nS 5268 +/- 20 nS 5268 +/- 20 nS 8031 +/- 31 nS 6939 +/- 27 nS 6425 +/- 25 nS 8031 +/- 31 nS 6939 +/- 27 nS 6425 +/- 25 nS d. Horizontal & Vertical Frequency Counter There are two 16-bit counters which can count H and V frequency automatically. When a VEVENT (V frequency counter timeout) interrupt occurs, the MCU may read the count value (Hcount and Vcount) from the counter registers (HFCOUNTH, HFCOUNTL, VFCOUNTH and VFCOUNTL) to calculate the H and V frequency by the formulas listed below. - 28 - W78E354 V frequency: The resolution of V frequency counter: Vresol = (1/Fclock ) × 16. The V frequency: Vfreq = 1/(Vcount × Vresol ). The lowest V frequency can be detected: Fclock ÷ 1048576. H frequency: The resolution of H frequency counter: Hresol = (1/Fclock ) ÷ 8. The H frequency: Hfreq = 1/(Hcount × Hresol ). The lowest H frequency can be detected: Fclock ÷ 8192. Vresol The Lowest Vfreq Hresol The Lowest Hfreq 16 MHz 1 µs 15 Hz 7.8 nS 1.9 KHz 18.432 MHz 868 nS 17.6 Hz 6.8 nS 2.3 KHz 20 MHz 800 nS 19 Hz 6.3 nS 2.4 KHz 24 MHz 666 nS 23 Hz 5.2 nS 2.9 KHz e. Dummy Frequency Generator The Dummy H and V frequencies are generated for 1) factory burn-in and 2) displaying warning messages if there is no input frequency. There are two registers in the dummy sync generator: DHREG: 4-bit register, determines the Dummy Hsync output frequency DVREG: 8-bit register, determines the Dummy Vsync output frequency Dummy Hsync frequency FdH = Fclock ÷ 32 ÷ (DHREG+1) Dummy Vsync frequency FdV = FdH ÷ 8 ÷ (DVREG+1) DUMMYEN 0 1 HOUT HREST HDUMMY VOUT VREST (if ENVS = 0), VSEP (if ENVS = 1) VDUMMY Ex. If System clock = 16 MHz DHREG 15 12 10 9 7 6 5 4 FdH 31.25K 38.5K 45.5K 50K 62.5K 71K 82K 100K DVREG 48 59 70 77 96 109 127 155 FdV 79.7 Hz 80.2 Hz 80.1 Hz 80.1 Hz 80.5 Hz 80.7 Hz 80.1 Hz 80.1 Hz - 29 - Publication Release Date: April 1997 Revision A1 W78E354 f. H-clamp Pulse Generator If P14SF = 0, P1.4 is a general purpose I/O port. If P14SF = 1, P1.4 is the H-clamp pulse output. 1. Leading edge / Trailing edge selectable HCES = 0: select leading edge HCES = 1: select trailing edge Hsync Hrest Leading Edge Trailing Edge 2. Pulse width selectable Hsync H-clamp ouput The pulse width is programmable: (1/Fclock) × Option, +/- 1/Fclock ÷ 2 (HCWS1, HCWS0) OPTION 4.5 8.5 16.5 32.5 16 MHz 281 +/- 31 nS 531 +/- 31 nS 1031 +/- 31 nS 18.432 MHz 244 +/- 27 nS 461 +/- 27 nS 896 +/- 27 nS 20 MHz 225 +/- 25 nS 425 +/- 25 nS 825 +/- 25 nS 24 MHz 187 +/- 20 nS 353 +/- 20 nS 686 +/- 20 nS 1352 +/- 20 nS (0, 0) (0, 1) (1, 0) (1, 1) g. SOA output 2031 +/- 31 nS 1764 +/- 27 nS 1625 +/- 25 nS If P15SF = 0, P1.5 is a general purpose I/O port. If P15SF = 1, P1.5 is the SOA output. - 30 - W78E354 Purpose: To protect the HOT (Horizontal Oscillating Transistor) and other critical circuitry by making a quick response when the Hsync frequency drops below the preset boundary frequency. Operation: When the Hsync frequency is lower than the boundary frequency for three consecutive cycles or stopped for a certain period, the SOA pin (P1.5) will change to a "high" state (for the extenal protection circuit to function). Writing any value to the SOACLR register will release the SOA pin. To set the boundary frequency, one can write some formula:value to the SOAREG register according to the SOAREG value = 2M ÷ boundary frequency Ex: If 50 KHz is considered the boundary frequency, then SOAREG = 2M ÷ 50K = 40. No Hsync response time = 2048 × (1/Fclock ). 16 MHz No H response time 128 µS 18.432 MHz 110 µS 20 MHz 102 µS 24 MHz 85 µS M. Power Supervisor, Watchdog Timer and Reset Circuitry The reset signals come from the following three sources: 1. External reset input (active low) 2. Power low detect 3. Hardware Watchdog Timer The power-low detection circuit generates a reset signal once the VCC voltage falls below 3.8V. This reset signal is released a short time after VCC has increased above 4.3V. This function can be enabled or disabled by a code option. The purpose of a watchdog timer is to reset the CPU if it enters erroneous processor states (possibly caused by electrical noise or RFI) within a reasonable period of time. The watchdog timer clock source comes from the internal system clock and can be enabled or disabled by a code option. When enabled, the watchdog circuitry will generate a system reset if the user program fails to reload the watchdog timer (by writing any value to the WDTCLR register) within a specified length of time known as the "watchdog interval". The watchdog interval has four code options: 219/fosc, 221/fosc, 223/fosc and 224/fosc sec. The block diagram of the reset circuitry is shown as follows: External Reset Watchdog Timer EN CPU XRESET POR Reset the other function blocks EnWDT_Bit Power-low Detect Circuit EN Reset all DACs EnSVS_Bit - 31 - Publication Release Date: April 1997 Revision A1 W78E354 FLASH CELL DESCRIPTION A. Flash ROM Interface The following diagram shows the Flash cell block control interface. A are the address bus inputs and Dout are the data bus outputs of the Flash ROM. VSS VPP VDD OSCEN (normally "0") /CE (PAD) 0 /CE 1 0 s /OE Flash ROM (16KB) /OE (PAD) 1 s 8 MUX 8 0 8 8 Din Dout 1 s 8 15 D (PAD) 15 PC 15 0 1 s A 8 A (PAD) OPTION 0 A9HV A9CTRL (PAD) ROM-MAP 8 1 0 s A13HV A13CTRL (PAD) 1 0 s A14HV A14CTRL (PAD) 1 0 s OECTRL OECTRL (PAD) 1 s Select signal will be decided by /RESET, /PROG, A9CTRL, A13CTRL, A14CTRL and OECTRL. * A14 = 0 at normal operation all the time. Flash ROM Block Diagram - 32 - W78E354 VPP is the high voltage input while in Flash Mode. A is the address bus of the Flash cell while in Flash Mode. Dout is the data bus output of the Flash cell and Din is the data bus input while the chip is in Flash mode. The A9CTRL, A13CTRL, A14CTRL and OECTRL signals are used to select the Flash Mode. The OE and CE signals are the control strobe signals for Flash Mode operation. These signals are operational only in Flash Mode and appear as inputs/outputs via the external pins with a "Test Name" as listed in the Pin Description in Sec. D. During normal operation, the critical timing parameter is the Flash data access time. When operating at 24 MHz, the Flash cell requires 150 nS after an address out until the data is valid, as shown below. Timing for Flash ROM Data Access ROM Address A ROM Data Dout Sample Clock 0000 0001 0002 #AAH Max. 150 nS for 24 MHz B. Option Setting Bits The Option setting bits are used to set user-selectable options. These bits are programmed in the same way as the 16K byte Flash ROM except for the address A which is 7FFFH. MSB B4 B3 B2 B1 Note: Default value is 1 for each bit. LSB • B1: EnWDT_Bit. (1: Disable, 0:Enable) This bit is used to enable/disable the Watchdog Timer operation. • (B3, B2): WatchDog Timer period set. These two bits are used to set the time period of the Watchdog timer. (0, 0): 219/fosc sec. (0, 1): 221/fosc sec. (1, 0): 223/fosc sec. (1, 1): 224/fosc sec. Where fosc is the crystal frequency. • B4: EnSVS_Bit. (1: Disable, 0:Enable) This bit is used to enable/disable the Power-low-detection function. - 33 - Publication Release Date: April 1997 Revision A1 W78E354 C. ROM-MAP Bits In order to increase the functionality of the 16K byte Flash ROM, the Flash ROM is divided into 4 blocks. If some blocks contain bad Flash cells but the other blocks are good, the 16KB Flash can be treated as either 8KB or 4KB, and the W78E354 downgraded to either the W78E352 or the W78E351. Four ROM-MAP bits are used to indicate the availability of the 16K bytes of Flash ROM after testing. MSB ROM-MAP B3 B2 B1 LSB B0 Set B0 = 1 if block 0 is available. Set B1 = 1 if block 1 is available. Set B2 = 1 if block 2 is available. Set B3 = 1 if block 3 is available. 16K bytes Flash ROM Block 0, 4K bytes Block 1, 4K bytes Block 2, 4K bytes Block 3, 4K bytes Note: Only one/two/four of the four bits can be set to indicate whether 4K/8K/16K are usable. FLASH/TEST MODE A. Flash Modes 1. Read This mode is supported for customer code verification. The data will be invalid if the Lock bit is set low. 2. Output Disable When the OE is set high, no data outputs appear on D7..D0. 3. Standby This condition disables the DC path from the Flash cell to reduce power consumption. 4. Program This mode is used to program the Flash cell and option bits. It is the only way to change data from "1" to "0". 5. Program Verify All the programming data must be checked after program or mass program operations. This operation should be performed after each byte is programmed to ensure a substantial program margin. 6. Erase An erase operation is the only way to change data from "0" to "1". 7. Erase Verify After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase margin. This operation will be implemented after the erase operation if VPP = VEP (14.5V), CE is high and OE is low. - 34 - W78E354 8. Proram/Erase Inhibit This operation allows parallel erasing or programming of multiple chips with different data. 9. Mass Program In order to increase the throughput of testing, this operation programs 256 bytes with the same data simultaneously. Note that 256 program verify operations must follow each mass program operation. All the timings for this operation are the same as those of the byte program operation except that the /CE program pulse width is 125µS. In addition, this operation is also used for cell reliability analysis by stressing the source line. 10. Read Company ID and Device ID These two modes are especially useful in EPROM WRITERs, which can read the silicon identification to set the appropriate erase or program algorithm to match the device being erased or programmed. 11. VT This operation is used for cell performance analysis. By connecting 2V to the D7..D0 pins, the cell currents can be measured for each location within the chip by specifying its appropriate address. 12. Read ROM-map Bits This operation is used to verify the ROM-MAP bits which were programmed previously. Its action is the same as an EEPROM read operation. 13. Fuse ROM-map Bits The ROM-MAP bits can be fused by this operation only. Its action is the same as an EEPROM program operation. 14. Erase ROM-map Bits The ROM-MAP bits can be erased by this operation only. Its action is the same as an EEPROM erase operation. 15. CKBD & /CKBD Mass Program These two operations are used to mass program the Flash cells in such a way that the state of any bit is different from those of its neighboring bits. 16. Read Disturb B. Test Mode *RAM-test Mode This mode is used to verify the function of the internal 512 bytes of RAM by a write-in and then readout operation. *Functional Test Mode If the EA (TestCLK) pin is pulled low when the chip is being reset and remains low for at least 24 clock periods after the reset, the CPU will execute from the external program memory (maximum program size is 2K bytes). This feature may be used to test the chip's functions via an external program. It should be noted that this mode is like the normal operation except that the CPU executes from external program memory and that some different pins are used in place of A10−A0, D7−D0 and PSEN instead of their original functions. - 35 - Publication Release Date: April 1997 Revision A1 W78E354 Flash/RAM-test Mode Configuration Table. CONFIGURATION Flash Modes Read Output Disable Standby Program Program Verify Erase [*3] Erase Verify Program/Erase Inhibit Mass Program Read Company ID Read Device ID VT Read ROM-MAP Fuse ROM-MAP Erase ROM-MAP CKBD & /CKBD Mass Program Read Disturb 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 VCP VEP VCP 1 A9CTRL A13CTRL A14CTRL 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 OECTRL 0 0 0 0 0 0 0 0 0 /CE /OE 0 0 1 0 1 0 1 1 0 0 1 X 1 0 1 0 1 1 VPP 1 1 1 VCP VCP VEP VEP VCP/VEP VCP A14..A0 Address X X Address Address A0 = 0, others: X Address X X A0 = 0, others: X A0 = 1, others: X Address 7FFFh 7FFFh X A6, A0 [*4] D7..D0 Data Out High-Z High-Z Data In Data Out Data In (FFh) Data Out X Data In Data Out (DAh) Data Out (64h) Cell Current Data Out Data In Data In (FFh) Data In (00h) Data Out Address CONFIGURATION RAM-test Modes 8032's 256 bytes of RAM-write 8032's 256 bytes of RAM-read Data Memory by MOVX-write Data Memory by MOVX-read Notes: 1: RESET and PROG must be kept low for all the above modes. 2: "X" means "Don't care" but not floating. VCP = 12.5V, VEP = 14.5V, "1" stands for VDD and "0" for VSS. *3: The Erase operation erases all the 16K bytes of Flash cell but not the ROM-MAP cell. *4: A0/A6 decides whether the bit-line/word-line is even or odd. A9CTRL A13CTRL A14CTRL 0 0 0 0 1 1 1 1 1 1 1 1 OECTRL X X X X /CE /OE 0 1 0 1 1 0 1 0 VPP X X X X A14..A9 A8 X X X X 0 0 1 1 A7..A0 Address Address Address Address D7..D0 Data In Data Out Data In Data Out - 36 - W78E354 For CKBD, (A6, A0) = (0, 0) and then (1, 1); for /CKBD, (A6, A0) = (1, 0) and then (0, 1). G.3 Flash Mode Timing Waveforms *Read Operation (including EEPROM, Company ID, Device ID, Option bits and ROM-MAP bits Read) PARAMETER Address Access Time Chip Enable Access Time Output Enable Access Time Output Data Hold Time Output Data Float Time Read Waveform SYMBOL TACC TCE TOE TODH TODF MIN. 0 TYP. MAX. 150 150 150 100 UNIT nS nS nS nS nS (A14..A0) VIH VIL VIH VIL VIH TODH/ODF Valid Address OE TOE CE VIL TCE VIH D7..D0 VIL TACC Data Note: Please pay attention to the relation between /CE's and /OE's waveforms. - 37 - Publication Release Date: April 1997 Revision A1 W78E354 *Erase Operation (including EEPROM&Option bits and ROM-MAP bits Erase) PARAMETER Vpp Setup Time Address Setup Time Address Hold Time Erase Pulse Width Output Data Valid after OE Low Address Hold Time Output Data Hold Time Output Data Float Time Erase Waveform SYMBOL TVPS TAS TAH1 TEPW TODV TAH2 TODH TODF MIN. 2.0 2.0 2.0 0 0 TYP. 1 MAX. 5 150 100 UNIT µS µS µS mS nS µS nS nS Erase VIH A14..A0 VIL VIH VIL TEPW OE VIH VIL VIH VIL Vep VIH TVPS TAS A0 = 0 TAH1 TAS Erase Verify Address Stable CE TAH2 TODH/ODF TODV DOUT D7..D0 VPP - 38 - W78E354 *Program & Mass Program Operation (including EEPROM, Option bits and ROM-MAP bits Program, and Mass Program) PARAMETER Vpp Setup Time Address Setup Time Input Data Setup Time Input Data Hold Time Program Pulse Width Mass Program Pulse Width Output Data Valid after OE Low Address Hold Time Output Data Hold Time Output Data Float Time Program Waveform Program Verify SYMBOL TVPS TAS TIDS TIDH TPPW TMPPW TODV TAH TODH TODF MIN. 2.0 2.0 2.0 2.0 0 0 - TYP. 100 500 - MAX. 200 1000 150 100 UNIT µS µS µS µS µS mS nS µS nS nS Program A14..A0 VIH VIL VIH VIL OE VIH VIL VIH VIL Vcp VIH TVPS Data In TIDH TIDS TAS TPPW Address Stable CE TAH TODH/ODF TODV Data Out D7..D0 VPP - 39 - Publication Release Date: April 1997 Revision A1 W78E354 D.1 Smart Erase Algorithm Start Vpp = 14.5V Enter ERASE Mode N=0 Increment N Erase one 1 mS pulse NO Erase Verify (Verify all bytes, must be FFh) PASS FAIL N = 10 ? YES Vpp = 5.0V Enter READ Mode Read Verify (Blank check) PASS FAIL Erase Fail ! Erase Pass ! - 40 - W78E354 D.2 Smart Program Algorithm Start Vpp = 12.5V Enter PROGRAM Mode Address = First Location N=0 Increment N Program One 100 uS Pulse NO Program Verify (Verify one byte) PASS FAIL N = 10 ? YES Increment Address NO Last Address ? YES Vpp = 5.0V Enter Rdad Mode Read Verify (Verify all bytes) PASS FAIL Program Fail ! Program Pass ! - 41 - Publication Release Date: April 1997 Revision A1 W78E354 ABSOLUTE MAXIMUM RATINGS PARAMETER DC Power Supply Input Voltage Input Current Operating Temperature Storage Temperature SYMBOL VDD VIN II TA TST MIN. -0.3 VSS -0.3 -100 0 -55 MAX. +7.0 VDD +0.3 +100 70 150 UNIT V V mA °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. ELECTRICAL CHARACTERISTICS Normal Operation D.C. Characteristics (VDD & VAA)−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified. PARAMETER Operating Voltage Operating Current Idle Current Power-down Current Logic 0 Input Current P1, P2, P3 (except P1.0−P1.3, P1.5) Input Current RESET , TestCLK (*1) SYM. VDD IDD IIDLE IPD IIN1 SPECIFICATION Min. 4.5 Typ. 5 Max. 5.5 65 30 10 -10 UNIT V mA mA µA µA TEST CONDITIONS No load, VDD = 5.5V No load, VDD = 5.5V No load, VDD = 5.5V VDD = 5.5V VIN = 0V VDD = 5.5V VIN = 0V VDD = 5.5V VIN = VDD VDD = 5.5V 0V < VIN < VDD VDD = 5.5V VIN = 2.0V Inputs -75 - IIN2 -250 - - µA µA µA µA Input Current HIN, VIN (*2) Input Leakage Current P1.0−P1.3, ADC0−ADC3 Logical 1-to-0 Transition Current P1, P2, P3 (*3) (except P1.0−P1.3, P1.5) IIN3 ILK ITL -10 -650 - +30 +10 - - 42 - W78E354 Normal Operation D.C. Characteristics, continued PARAMETER Input Low Voltage (*4) SYM. VIL1 SPECIFICATION Min. 0 Typ. Max. 0.8 UNIT V TEST CONDITIONS VDD = 4.5V P1, P2, P3 (except P1.0−P1.3, P1.5) RESET Input Low Voltage (*4) HIN, VIN Input Low Voltage (*4) P1.0−P1.3 Input High Voltage P1, P2, P3 (except P1.0−P1.3, P1.5) Input High Voltage (*4) RESET , OSCIN VIL2 VIL3 VIH1 0 0 2.4 - 0.8 1.5 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 V V V VDD = 4.5V VDD = 4.5V VDD = 5.5V VIH2 3.5 - V VDD = 5.5V Input High Voltage (*4) HIN, VIN Input High Voltage (*4) P1.0−P1.3 Output Low Voltage P1.0, P1.1 Output Low Voltage P1.2, P1.3 Output Low Voltage P1.4, P1.5, P2.2−P2.7 SDAC0−13, HOUT, VOUT Output Low Voltage P2.0, P2.1 Output Low Voltage P3, P4 Output Low Voltage BSDAC0−1, DDAC0−2, BDDAC VIH3 VIH4 2.4 3.0 - V V VDD = 5.5V VDD = 5.5V VOL1 VOL2 VOL3 Outputs - 0.4 0.4 0.45 V V V VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +6 mA VDD = 4.5V IOL = +4 mA VOL4 VOL5 VOL6 - - 0.5 0.45 0.45 V V V VDD = 4.5V IOL = +15 mA VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +8 mA - 43 - Publication Release Date: April 1997 Revision A1 W78E354 Normal Operation D.C. Characteristics, continued PARAMETER Output High Voltage P1.4, P2, P3 Output High Voltage P4 Output High Voltage P1.5, SDAC0−13, HOUT, VOUT S.F. of P1.4 and P2.3−P2.7(*5) Output High Voltage BSDAC0−1, DDAC0−2, BDDAC Notes: SYM. VOH1 VOH2 VOH3 SPECIFICATION Min. 2.4 2.4 2.4 Typ. Max. - UNIT V V V TEST CONDITIONS VDD = 4.5V IOL = -100 µA VDD = 4.5V IOH = -2 mA VDD =4.5V IOH = -4 mA VOH4 2.4 - - V VDD = 4.5V IOH = -8 mA *1. RESET and TestCLK have an internal pull-up resistor of about 30 KΩ. *2. HIN and VIN have an internal pull-down resistor of about 200 KΩ. *3. P1, P2 and P3 (except P1.0−P1.3 and P1.5) can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. *4. P1.0−P1.3, RESET , HIN and VIN are Schmitt trigger inputs, and OSCIN is a CMOS input. *5. While outputing a special function, the source current of P1.4 and P2.3−P2.7 is -4 mA. Flash Operation D.C. Characteristics (VDD & VAA)−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified. PARAMETER SYM. SPECIFICATION MIN. TYP. MAX. UNIT TEST CONDITIONS Input Current A0−A14, D0−D7, A9CTRL, A13CTRL, A14CTRL, OECTRL, OE , CE VPP Erase Current (VPP = VEP) VPP Program Current (VPP = VCP) Input Low Voltage A0−A14, D0−D7, A9CTRL, A13CTRL, A14CTRL, OECTRL, OE , CE IIN -75 - +10 µA VDD = 5.5V VIN = 0V or VDD IEP ICP VIL 0 - +200 +200 0.8 µA µA V VDD = 5.5V CE = VIL, CE = VIH VDD = 5.5V CE = VIL, CE = VIH VDD = 4.5V - 44 - W78E354 Flash Operation D.C. Characteristics, continued PARAMETER SYM. SPECIFICATION MIN. TYP. MAX. UNIT TEST CONDITIONS Input High Voltage A0−A14, D0−D7, A9CTRL, A13CTRL, A14CTRL, OECTRL, OE , CE Output Low Voltage D0−D7 Output High Voltage D0−D7 VPP Erase Voltage VPP Program Voltage VIH 2.4 - VDD +0.2 V VDD = 5.5V VOL VOH VEP VCP 2.4 14.25 12.25 14.5 12.5 0.45 14.75 12.75 V V V V VDD = 4.5V IOL = +2 mA VDD = 4.5V IOH = -100 µA TYPICAL APPLICATION Please note: While the chip is being powered on and the RESET pin is low, if P1.5 and P3.2 are kept low at the same time, then the POR (Power-on Reset) will last until P1.5 or P3.2 is pulled High, whichever occurs first. Headquarters Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792697 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 408-9436666 Voice & Fax-on-demand: 886-2-27197006 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 45 - Publication Release Date: April 1997 Revision A1