W78E516B_06

W78E516B Data Sheet 8-BIT MICROCONTROLLER Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 PIN DESCRIPTION..................................................................................................................... 5 FUNCTIONAL DESCRIPTION ................................................................................................... 6 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 6. RAM ................................................................................................................................ 6 Timers 0, 1 and 2 ............................................................................................................ 6 Clock ............................................................................................................................... 7 Crystal Oscillator............................................................................................................. 7 External Clock................................................................................................................. 7 Power Management........................................................................................................ 7 Reduce EMI Emission .................................................................................................... 7 Reset............................................................................................................................... 7 Port 4 .............................................................................................................................. 9 INT2 / INT3 ...................................................................................................................... 9 Port 4 Base Address Registers .................................................................................... 12 In-System Programming (ISP) Mode............................................................................ 14 In-System Programming Control Register (CHPCON)................................................. 16 SECURITY ................................................................................................................................ 20 6.1 6.2 6.3 6.4 Lock Bit ......................................................................................................................... 20 MOVC Inhibit................................................................................................................. 20 Encryption ..................................................................................................................... 21 Oscillator Control .......................................................................................................... 21 7. ELECTRICAL CHARACTERISTICS......................................................................................... 22 7.1 7.2 7.3 Absolute Maximum Ratings .......................................................................................... 22 D.C. Characteristics...................................................................................................... 22 A.C. Characteristics ...................................................................................................... 24 8. TIMING WAVEFORMS ............................................................................................................. 26 8.1 8.2 8.3 Program Fetch Cycle .................................................................................................... 26 Data Read Cycle........................................................................................................... 26 Data Write Cycle ........................................................................................................... 27 -1- Publication Release Date: December 4, 2006 Revision A11 W78E516B 8.4 9. Port Access Cycle......................................................................................................... 27 TYPICAL APPLICATION CIRCUITS ........................................................................................ 28 9.1 9.2 External Program Memory and Crystal ........................................................................ 28 Expanded External Data Memory and Oscillator ......................................................... 29 10. PACKAGE DIMENSIONS ......................................................................................................... 30 10.1 10.2 10.3 40-pin DIP ..................................................................................................................... 30 44-pin PLCC ................................................................................................................. 30 44-pin PQFP ................................................................................................................. 31 11. APPLICATION NOTE ............................................................................................................... 32 11.1 In-system Programming Software Examples ............................................................... 32 12. REVISION HISTORY ................................................................................................................ 37 -2- W78E516B 1. GENERAL DESCRIPTION The W78E516B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E516B is fully compatible with the standard 8052. The W78E516B contains a 64K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash EPROM which allows the contents of the 64KB main Flash EPROM to be updated by the loader program located at the 4KB auxiliary Flash EPROM ROM; 512 bytes of on-chip RAM; four 8-bit bidirectional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the W78E516B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E516B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. 2. FEATURES • • • • • • • • • • • • • Fully static design 8-bit CMOS microcontroller up to 40 MHz. 64K bytes of in-system programmable Flash EPROM for Application Program (APROM). 4K bytes of auxiliary Flash EPROM for Loader Program (LDROM). 512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable) 64K bytes program memory address space and 64K bytes data memory address space. Four 8-bit bi-directional ports. One 4-bit multipurpose programmable port. Three 16-bit timer/counters One full duplex serial port Six-sources, two-level interrupt capability Built-in power management Code protection Packaged in − Lead Free (ROHS) DIP 40: W78E516B40DL − Lead Free (ROHS) PLCC 44: W78E516B40PL − Lead Free (ROHS) PQFP 44: W78E516B40FL -3- Publication Release Date: December 4, 2006 Revision A11 W78E516B 3. PIN CONFIGURATIONS 40-Pin DIP T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 44-Pin PLCC / I N T 3 , P 4V .D 2D 44-Pin QFP T 2 E X , P 1 . 1 / I N T 3 , P 4V .D 2D P 1 . 4 P 1 . 3 P 1 . 2 T 2 E X , P 1 . 1 T 2 , P 1 . 0 A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 1 2 P 1 . 4 P 1 . 3 P 1 . 2 T 2 , P 1 . 0 A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X T A L 1 V S S P 4 . 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XV TS AS L 1 P 4 . 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 -4- W78E516B 4. PIN DESCRIPTION SYMBOL TYPE DESCRIPTIONS EA I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus if the EA pin is high. PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. PSEN OH ALE RST XTAL1 XTAL2 VSS VDD P0.0 − P0.7 P1.0 − P1.7 P2.0 − P2.7 P3.0 − P3.7 P4.0 − P4.3 OH IL I O I I I/O D PORT 0: Function is the same as that of standard 8052. I/O H PORT 1: Function is the same as that of standard 8052. I/O H PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. I/O H PORT 3: Function is the same as that of the standard 8052. I/O H PORT 4: A bi-directional I/O. See details below. * Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4) can be used. This port address is located at 0D8H with the same function as that of port P1. Example: P4 MOV MOV ORL ANL REG A, P4 P4, #00000001B P4, #11111110B 0D8H ; Output data "A" through P4.0 − P4.3. ; Read P4 status to Accumulator. P4, #0AH -5- Publication Release Date: December 4, 2006 Revision A11 W78E516B 5. FUNCTIONAL DESCRIPTION The W78E516B architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three timer/counters, a serial port and an internal 74373 latch and 74244 buffer which can be switched to port2. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. 5.1 RAM The internal data RAM in the W78E516B is 512 bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways. • RAM 0H − 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers are R0 and R1 of the selected register bank. • RAM 80H − FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0, R1 of the selected registers bank. • AUX-RAM 0H − FFH is addressed indirectly as the same way to access external data memory with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than FFH will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD . Example, CHPENR CHPCON MOV MOV ORL MOV MOV MOV MOVX REG F6H REG BFH CHPENR, #87H CHPENR, #59H CHPCON, #00010000B CHPENR, #00H R0, #12H A, #34H @R0, A ; enable AUX-RAM ; Write 34h data to 12h address. 5.2 Timers 0, 1 and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. -6- W78E516B 5.3 Clock The W78E516B is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78E516B relatively insensitive to duty cycle variations in the clock. 5.4 Crystal Oscillator The W78E516B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. 5.5 External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts. 5.6 Power Management Idle Mode Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered. 5.7 Reduce EMI Emission The W78E516B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 24 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. 5.8 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E516B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. -7- Publication Release Date: December 4, 2006 Revision A11 W78E516B W78E516B Special Function Registers (SFRs) and Reset Values F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 Notes: 1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable. 2. The text of SFR with bold type characters are extension function registers. +ACC 00000000 +P4 xxxx1111 +PSW 00000000 +T2CON 00000000 XICON 00000000 +IP 00000000 +P3 00000000 +IE 00000000 +P2 11111111 +SCON 00000000 +P1 11111111 +TCON 00000000 +P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 SBUF xxxxxxxx P41AL 00000000 TH0 00000000 P40AL 00000000 P41AH 00000000 TH1 00000000 P40AH 00000000 PCON 00110000 P2EAL 00000000 P2EAH 00000000 +B 00000000 CHPENR 00000000 FF F7 EF E7 DF D7 RCAP2L 00000000 P4CONA 00000000 RCAP2H 00000000 P4CONB 00000000 TL2 00000000 SFRAL 00000000 TH2 00000000 SFRAH 00000000 CF SFRFD 00000000 SFRCN 00000000 CHPCON 0xx00000 C7 BF B7 P2ECON 0000XX00 AF A7 9F 97 8F 87 P43AL 00000000 P42AL 00000000 P43AH 00000000 P42AH 00000000 -8- W78E516B 5.9 Port 4 Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation modes. Mode 0: P4.0 − P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as external interrupt INT3 and INT2 if enabled. Mode 1: P4.0 − P4.3 are read strobe signals that are synchronized with RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 2: P4.0 − P4.3 are write strobe signals that are synchronized with WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 3: P4.0 − P4.3 are read/write strobe signals that are synchronized with RD or WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode. 5.10 INT2 / INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. -9- Publication Release Date: December 4, 2006 Revision A11 W78E516B XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2 PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt information INTERRUPT SOURCE VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt 2 External Interrupt 3 03H 0BH 13H 1BH 23H 2BH 33H 3BH 0 (highest) 1 2 3 4 5 6 7 (lowest) IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.2 XICON.6 TCON.0 TCON.2 XICON.0 XICON.3 - 10 - W78E516B P4CONB (C3H) BIT NAME FUNCTION 00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1. 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 7, 6 P43FUN1 P43FUN0 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1, and P43CMP0. Chip-select signals address comparison: 00: Compare the full address (16 bits length) with the base address register P43AH, P43AL. 5, 4 P43CMP1 01: Compare the 15 high bits (A15 − A1) of address bus with the base address register P43AH, P43AL. P43CMP0 10: Compare the 14 high bits (A15 − A2) of address bus with the base address register P43AH, P43AL. 11: Compare the 8 high bits (A15 − A8) of address bus with the base address register P43AH, P43AL. 3, 2 1, 0 P42FUN1 P42FUN0 The P4.2 function control bits which are the similar definition as P43FUN1, P43FUN0. P42CMP1 The P4.2 address comparator length control bits which are the similar P42CMP0 definition as P43CMP1, P43CMP0. P4CONA (C2H) BIT NAME FUNCTION 7, 6 5, 4 3, 2 1, 0 P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1, P41FUN0 P43FUN0. P41CMP1 The P4.1 address comparator length control bits which are the similar P41CMP0 definition as P43CMP1, P43CMP0. P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1, P40FUN0 P43FUN0. P40CMP1 The P4.0 address comparator length control bits which are the similar P40CMP0 definition as P43CMP1, P43CMP0. - 11 - Publication Release Date: December 4, 2006 Revision A11 W78E516B P2ECON (AEH) BIT NAME FUNCTION 7 The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe signal. = 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe P43CSINV signal. = 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal. P42CSINV The similarity definition as P43SINV. P41CSINV The similarity definition as P43SINV. P41CSINV The similarity definition as P43SINV. P40CSINV The similarity definition as P43SINV. Reserve Reserve 0 0 6 5 5 4 3 2 1 0 5.11 Port 4 Base Address Registers P40AH, P40AL: The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address. P41AH, P41AL: The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address. P42AH, P42AL: The Base address register for comparator of P4.2. P42AH contains the high-order byte of address, P42AL contains the low-order byte of address. P43AH, P43AL: The Base address register for comparator of P4.3. P43AH contains the high-order byte of address, P43AL contains the low-order byte of address. - 12 - W78E516B P4 (D8H) BIT NAME FUNCTION 7 6 5 4 3 2 1 0 P43 P42 P41 P40 Reserve Reserve Reserve Reserve Port 4 Data bit which outputs to pin P4.3 at mode 0. Port 4 Data bit which outputs to pin P4.2 at mode 0. Port 4 Data bit which outputs to pin P4.1at mode 0. Port 4 Data bit which outputs to pin P4.0 at mode 0. Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H − 1237H and positive polarity, and P4.1 − P4.3 are used as general I/O ports. MOV P40AH, #12H MOV P40AL, #34H MOV P4CONA, #00001010B MOV P4CONB, #00H MOV P2ECON, #10H ; Base I/O address 1234H for P4.0 ; P4.0 a write strobe signal and address line A0 and A1 are masked. ; P4.1 − P4.3 as general I/O port which are the same as PORT1 ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity ; default is negative. Then any instruction MOVX @DPTR, A (with DPTR = 1234H − 1237H) will generate the positive polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of data #XX to pin P4.3 − P4.1. - 13 - Publication Release Date: December 4, 2006 Revision A11 W78E516B P4xCSINV P4 REGISTER P4.x DATA I/O RD_CS MUX 4->1 WR_CS READ WRITE RD/WR_CS PIN P4.x ADDRESS BUS EQUAL REGISTER P4xAL P4xAH P4xFUN0 P4xFUN1 Bit Length Selectable comparator REGISTER P4xCMP0 P4xCMP1 P4.x INPUT DATA BUS 5.12 In-System Programming (ISP) Mode The W78E516B equips one 64K byte of main Flash EPROM bank for application program (called APROM) and one 4K byte of auxiliary Flash EPROM bank for loader program (called LDROM). In the normal operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the W78E516B allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON register write attribute. The W78E516B achieves all in-system programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode, software may use timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for revising contents of APROM, software located at APROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in LDROM. Because the device will clear the program counter while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The device offers a software reset for switching back to APROM while the content of APROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset to reset the CPU. The software reset serves as a external reset. This insystem programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible to easily update the system firmware without opening the chassis. - 14 - W78E516B SFRAH, SFRAL: The objective address of on-chip Flash EPROM in the in-system programming mode. SFRFAH contains the high-order byte of address, SFRFAL contains the low-order byte of address. SFRFD: The programming data for on-chip Flash EPROM in programming mode. SFRCN: The control byte of on-chip Flash EPROM programming mode. SFRCN (C7) BIT NAME FUNCTION 7 - Reserve. On-chip Flash EPROM bank select for in-system programming. = 0: 64K bytes Flash EPROM bank is selected as destination for reprogramming. = 1: 4K bytes Flash EPROM bank is selected as destination for reprogramming. 6 WFWIN 5 4 3, 2, 1, 0 OEN CEN CTRL[3:0] Flash EPROM output enable. Flash EPROM chip enable. The flash control signals MODE WFWIN CTRL OEN CEN SFRAH, SFRAL SFRFD Erase 64KB APROM Program 64KB APROM Read 64KB APROM Erase 4KB LDROM Program 4KB LDROM Read 4KB LDROM 0 0 0 1 1 1 0010 0001 0000 0010 0001 0000 1 1 0 1 1 0 0 0 0 0 0 0 X Address in Address in X Address in Address in X Data in Data out X Data in Data out - 15 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 5.13 In-System Programming Control Register (CHPCON) CHPCON (BFH) BIT NAME FUNCTION 7 6 5 4 3 2 When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It SWRESET will enforce microcontroller reset to initial condition just like power on reset. (F04KMODE) This action will re-boot the microcontroller and start to normal operation. To read this bit in logic-1 can determine that the F04KBOOT mode is running. ENAUXRAM Reserve. Reserve. 1: Enable on-chip AUX-RAM. 0: Disable the on-chip AUX-RAM Must set to 0. Must set to 0. The Program Location Select. 0: The Loader Program locates at the 64 KB APROM. 4KB LDROM is destination for re-programming. 1: The Loader Program locates at the 4 KB memory bank. 64KB APROM is destination for re-programming. FLASH EPROM Programming Enable. 0 0 1 FBOOTSL 0 = 1: enable. The microcontroller enter the in-system programming mode after entering the idle mode and wake-up from interrupt. During in-system FPROGEN programming mode, the operation of erase, program and read are achieve when device enters idle mode. = 0: disable. The on-chip flash memory is read-only. In-system programmability is disabled. F04KBOOT Mode (Boot from LDROM) By default, the W78E516B boots from APROM program after a power on reset. On some occasions, user can force the W78E516B to boot from the LDROM program via following settings. The possible situation that you need to enter F04KBOOT mode when the APROM program can not run properly and device can not jump back to LDROM to execute in-system programming function. Then you can use this F04KBOOT mode to force the W78E516B jumps to LDROM and executes in-system programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel. When the APROM program fails to execute the normal application program. User can press both two buttons at the same time and then turn on the power of the personal computer to force the W78E516B to enter the F04KBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or F04KBOOT mode. - 16 - W78E516B F04KBOOT MODE P4.3 P2.7 P2.6 MODE X L L X L X FO4KBOOT FO4KBOOT The Reset Timing For Entering F04KBOOT Mode P2.7 Hi-Z P2.6 Hi-Z RST 30 mS 10 mS - 17 - Publication Release Date: December 4, 2006 Revision A11 W78E516B The Algorithm of In-System Programming Part 1:64KB APROM START procedure of entering In-System Programming Mode Enter In-System Programming Mode ? (conditions depend on user's application) Yes No Setting control registers MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Execute the normal application program Setting Timer (about 1.5 us) and enable timer interrupt END Start Timer and enter idle Mode. (CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode) CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program. Go - 18 - W78E516B Part 2: 4KB LDROM Go Procedure of Updating the 64KB APROM Timer Interrupt Service Routine: Stop Timer & disable interrupt PGM Yes Is F04KBOOT Mode? (CHPCON.7=1) No Reset the CHPCON Register: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Setting Timer and enable Timer interrupt for wake-up . (50us for program operation) End of Programming ? Yes No Is currently in the F04KBOOT Mode ? No Software reset CPU and re-boot from the 64KB APROM. MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#83H Yes Get the parameters of new code Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) (Address and data bytes) through I/O ports, UART or other interfaces. Setting erase operation mode: MOV SFRCN,#22H (Erase 64KB APROM) Setting control registers for programming: MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H Start Timer and enter IDLE Mode. (Erasing...) Hardware Reset to re-boot from new 64 KB APROM. (S/W reset is invalid in F04KBOOT Mode) End of erase operation. CPU will be wakened by Timer interrupt. END Executing new code from address 00H in the 64KB APROM. PGM - 19 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 6. SECURITY During the on-chip Flash EPROM programming mode, the Flash EPROM can be programmed and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash EPROM and those operations on it are described below. The W78E516B has a Special Setting Register, the Security Register, which can not be accessed in programming mode. Those bits of the Security Register can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the LDROM space. D7 D6 D5 D4 D3 D2 D1 D0 B7 Reserved B2 B1 B0 4KB Flash EPROM 0000h Security Bits Program Memory LDROM B0: Lock bit, logic 0: active B1: MOVC inhibit, logic 0: the MOVC instruction in external memory cannot access the code in internal memory. logic 1: no restriction. B2: Encryption logic 0: the encryption logic enable logic 1: the encryption logic disable B07: Osillator Control logic 0: 1/2 gain logic 1: Full gain Default 1 for all security bits. Reserved bits must be kept in logic 1. Security Register 0FFFh 64KB Flash EPROM Program Memory APROM Reserved Reserved FFFFh Special Setting Register 6.1 Lock Bit This bit is used to protect the customer's program code in the W78E516B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the Flash EPROM data and Special Setting Registers can not be accessed again. 6.2 MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. - 20 - W78E516B 6.3 Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. 6.4 Oscillator Control W78E516B/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. - 21 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER SYMBOL MIN. MAX. UNIT DC Power Supply Input Voltage Operating Temperature Storage Temperature VDD − VSS VIN TA TST -0.3 VSS -0.3 0 -55 +6.0 VDD +0.3 70 +150 V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 7.2 D.C. Characteristics (VDD − VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER SYM. SPECIFICATION MIN. MAX. UNIT TEST CONDITIONS Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current P0, EA Logic 1 to 0 Transition Current P1, P2, P3, P4 Input Low Voltage P0, P1, P2, P3, P4, EA Input Low Voltage RST Input Low Voltage XTAL1[*4] VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL[*4] VIL1 VIL2 VIL3 4.5 -50 -10 -10 -500 0 0 0 5.5 20 6 50 +10 +300 +10 0.8 0.8 0.8 V mA mA μA μA μA μA μA V V V RST = 1, P0 = VDD No load VDD = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0< VIN