W78E54P-24

W78E54 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The W78E54 is an 8-bit microcontroller that is functionally compatible with the W78C54, except that the mask ROM is replaced by a flash EEPROM with a size of 16 KB. To facilitate programming and verification, the flash EEPROM inside the W78E54 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E54 microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the market. It is functionally compatible with the industry-standard 80C52 microcontroller series, except that one extra 4-bit bit-addressable I/O port (Port 4) and two additional external interrupts ( INT2 , INT3 ). The W78E54 contains four 8-bit bidirectional and bit-addressable I/O ports, three 16-bit timer/counters, and a serial port. These peripherals are supported by a eight-source, two-level interrupt capability. There are 256 bytes of RAM and an 16 KB flash EEPROM for application programs. The W78E54 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. FEATURES • • • • • • • • • 8-bit CMOS microcontroller Fully static design Low standby current at full supply voltage DC-40 MHz operation 256 bytes of on-chip scratchpad RAM 16 KB electrically erasable/programmable EPROM 64 KB program memory address space 64 KB data memory address space Four 8-bit bidirectional ports (available on 44-pin PLCC/QFP package) Three 16-bit timer/counters One full duplex serial port Boolean processor Eight-source, two-level interrupt capability Built-in power management Code protection mechanism Packages: − DIP 40: W78E54-16/24/40 − PLCC 44: W78E54P-16/24/40 − QFP 44: W78E54F-16/24/40 − TQFP 44: W78E54M-16/24/40 Publication Release Date: November 1997 Revision A2 • One extra 4-bit bit-addressable I/O port, additional INT2 / INT3 • • • • • • • -1- W78E54 PIN CONFIGURATIONS 40-Pin DIP (W78E54) T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 44-Pin PLCC (W78E54P) / I N T 3 , P 4V .C 2C 44-Pin QFP/TQFP (W78E54F/W78E54M)) T 2 E X , PPPP 1111 .... 4321 / I N TT 23 ,, PP 14V ..C 02C T 2 E X , PPPP 1111 .... 4321 T 2 , P 1 . 0 A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVP TS4 AS. L 0 1 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 1 2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS. . L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 -2- W78E54 PIN DESCRIPTION The W78E54 has two operating modes, normal and flash. In normal mode, the W78E54 corresponds to the W78C54. In flash mode, the user (the maker of the flash EEPROM writer) can access the flash EEPROM. P0.7− P0.0 Port 0, Bits 7− 0 MODE Normal Flash DESCRIPTION Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. This port provides the data bus during access to the flash EEPROM. P1.7− P1.0 Port 1, Bits 7− 0 MODE Normal DESCRIPTION Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively. This port provides the low-order address bus during access to the flash EEPROM. Flash P2.7− P2.0 Port 2, Bits 7− 0 MODE Normal Flash DESCRIPTION Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory.. This port provides the high-order address bus during access to the flash EEPROM. P3.7− P3.0 Port 3, Bits 7− 0 MODE Normal Flash DESCRIPTION Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate functions. P3.3−P3.0 and P3.7−P3.6 are the flash mode configuration pins, Input. P3.3−P3.0 and P3.7−P3.6 are configured to select or execute the flash operations. For details, see Flash Operations. P4.3− P4.0 Port 4, Bits 3− 0 (available on 44-pin PLCC/QFP package) MODE Normal DESCRIPTION Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 / INT3 ). -3- Publication Release Date: November 1997 Revision A2 W78E54 Flash No function in this mode. EA/VPP MODE Normal DESCRIPTION EA , External Access, Input, active low. This pin forces the processor to execute a program from the external ROM. When the internal flash EEPROM is accessed as in the W78C54, this pin should be kept high. Flash VPP, Program Power supply pin, Input. This pin accepts the high voltage (12V) needed for programming the flash EEPROM. RST MODE Normal RST, Reset, Input, active high. This pin resets the processor. It must be kept high for at least two machine cycles in order to be recognized by the processor. Flash Flash mode configuration pin, Input, active high. RST is used to configure the flash operations. For details, see Flash Operations. DESCRIPTION ALE MODE Normal DESCRIPTION ALE, Address Latch Enable, Output, active high. ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped during external data memory accesses. ALE goes to a high impedance state with a weak pull-up during reset state. Flash mode configuration pin, Input, active low. ALE is used to configure the flash operations. For details, see Flash Operations. Flash PSEN MODE Normal DESCRIPTION PSEN , Program Store Enable, Output, active low. This pin enables the external ROM onto the Port 0 address/data bus during fetch and MOVC operations. PSEN goes to a high impedance state with a weak pull-up during reset state Flash Flash mode configuration pin, Input, active high. PSEN is used to configure the flash operations. For details, see Flash Operations. XTAL1 MODE DESCRIPTION -4- W78E54 Normal Flash Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock. Connect to VSS. XTAL2 MODE Normal Flash No function in this mode. DESCRIPTION Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1. VSS, VCC Power Supplies. These are the chip ground and positive supplies. BLOCK DIAGRAM -5- Publication Release Date: November 1997 Revision A2 W78E54 P1.0 ~ P1.7 Port 1 Port 1 Latch ACC INT2 B Port 0 Latch T1 T2 Port 0 Interrupt INT3 P0.0 ~ P0.7 Timer 2 Timer 0 Timer 1 UART PSW ALU Stack Pointer DPTR Temp Reg. PC Incrementor Addr. Reg. P3.0 ~ P3.7 Port 3 Port 3 Latch Instruction Decoder & Sequencer SFR RAM Address 256 bytes RAM & SFR Port 2 Bus & Clock Controller Port 2 Latch P2.0 ~ P2.7 P4.0 ~ P4.3 Port 4 Port 4 Latch Oscillator Reset Block Power control XTAL1 XTAL2 ALE PSEN RST Vcc Vss -6- W78E54 FUNCTIONAL DESCRIPTION The W78E54 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78E54: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. Clock The W78E54 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78E54 relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78E54 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts. Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode -7- Publication Release Date: November 1997 Revision A2 W78E54 When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a reset. -8- W78E54 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E54 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. Option Setting Users write programs into the W78E54 by using the Winbond proprietary writer. The writer programs the data into an internal 16 KB region and reads the data back for verification. After confirming that the program is correct, the user can lock the data so that they can no longer be read. Lock Bit This bit is used to protect the customer data in the W78E54. It may be turned on after the programmer finishes the programming and verify sequence. Once this bit is set to logic 0, no flash data can be accessed again. MOVC Execute This bit is used to restrict the region accessible to the MOVC instruction. It can prevent the program from being downloaded using this instruction if the program needs to jump outside to get data. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code in the external memory, but it will not be able to access code in the internal memory. A MOVC instruction in internal program memory space will always be able to access code in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. New Defined Peripheral In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows: 1. INT2/ INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. ***XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2 -9- Publication Release Date: November 1997 Revision A2 W78E54 PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt informations: INTERRUPT SOURCE External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt 2 External Interrupt 3 2. PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 , INT3 ). Example: P4 MOV MOV SETB CLR REG A, P4 P4.0 P4.1 0D8H ; Output data "A" through P4.0−P4.3. ; Read P4 status to Accumulator. ; Set bit P4.0 ; Clear bit P4.1 P4, #0AH VECTOR ADDRESS 03H 0BH 13H 1BH 23H 2BH 33H 3BH POLLING SEQUENCE WITHIN PRIORITY LEVEL 0 (highest) 1 2 3 4 5 6 7 (lowest) ENABLE REQUIRED SETTINGS IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.2 XICON.6 INTERRUPT TYPE EDGE/LEVEL TCON.0 TCON.2 XICON.0 XICON.3 3. Reduce EMI Emission Because of the large on-chip flash EEPROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the - 10 - W78E54 AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space.. The AO bit in the AUXR register, when set, disables the ALE output. ***AUXR - Auxiliary register (8EH) AO AO: Turn off ALE output. 4. Power-off Flag ***PCON - Power control (87H) SMOD SMOD: POF: GF1, GF0: PD: IDL: POF GF1 GF0 PD IDL Double baud rate bit. When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2, 3. Power off flag. Bit is set by hardware when power on reset. It can be cleared by software to determine chip reset is a warm boot or cold boot. These two bits are general-purpose flag bits for the user. Power down mode bit. Set it to enter power down mode. Idle mode bit. Set it to enter idle mode. The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software. Flash Operations In normal operation, the W78E54 is functionally compatible with the W78C54. In the flash operating mode, the flash EEPROM can be programmed and verified repeatedly. Once the code inside the flash EEPROM is confirmed, the code can be protected. The flash EEPROM and the operations on it are described below. All of the operations are configured by the pins RST, ALE, PSEN , A9CTRL (P3.0), A13CTRL (P3.1), A14CTRL (P3.2), OECTRL (P3.3), CE (P3.6), OE (P3.7), A0 (P1.0) and VPP ( EA ). In these operations, A15 to A0 (P2.7 to P2.0, P1.7 to P1.0) and D7 to D0 (P0.7 to P0.0) serve as the address and data bus, respectively. Read Operation This operation enables customers to read their codes and the option bits. The data will not be valid if the lock bit is programmed to low. - 11 - Publication Release Date: November 1997 Revision A2 W78E54 Program Operation This operation is used to program data to the flash EEPROM and the option bits. Programming is initiated when VPP reaches VCP (12.5V) level, CE is set to low, and OE is set to high. Program Verify Operation All data must be checked after programming. This operation should be performed after each byte is programmed, and it will ensure a substantial program margin. OPERATION P3.0 (A9 CTRL) Read Program Program Verify Notes: 1. During all of these operations, RST = VIH, ALE = VIL, and PSEN = VIH. 2. VCP = 12V, VIH = VDD, VIL = Vss. 3. The program verify operation should follow the programming operaion. VIL VIL VIL P3.1 (A13 CTRL) VIL VIL VIL P3.2 (A14 CTRL) VIL VIL VIL P3.3 (OE CTRL) VIL VIL VIL P3.6 ( CE ) VIL VIL VIH P3.7 ( OE ) VIL VIH VIL EA (VPP) VIH VCP VCP P2, P1 (A15 TO A0) Address Address Address P0 (D7 TO D0) Data Out Data In Data Out 1, 2 1, 2 3 NOTES ABSOLUTE MAXIMUM RATINGS PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VDD−VSS VIN TA TST MIN. -0.3 VSS -0.3 0 -55 MAX. +7.0 VDD +0.3 70 +150 UNIT V V °C °C of Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability the device. +5V +5V V DD A0 to A7 V IL V IL V IL V IL V IL V IH P1 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 X'tal2 Vss ALE RST PSEN V IL V IH V IH P0 EA/Vpp PGM DATA A0 to A7 V IL V IL V IL V IL V IH V IL P1 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 X'tal2 Vss V DD P0 EA/Vpp ALE RST PSEN PGM DATA V CP V CP V IL V IH V IH P2 A8 to A15 P2 A8 to A15 Programming Configuration Programming Verification - 12 - W78E54 DC CHARACTERISTICS (VDD-VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current P0, /EA Logic 1 to 0 Transition Current P1, P2, P3, P4 Input Low Voltage P0, P1, P2, P3, P4, EA Input Low Voltage RST Input Low Voltage XTAL1[*4] Input High Voltage P0, P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1 [*4] Output Low Voltage P1, P2, P3, P4 SYM. VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL [*4] SPECIFICATION MIN. 4.5 -50 -10 -10 -500 MAX. 5.5 20 6 50 +10 +300 +10 -200 UNIT V mA mA µA µA µA µA µA TEST CONDITIONS No load VDD = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0V