W78LE365

W78LE365/W78L365A Data Sheet 8-BIT MICROCONTROLLER Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 PIN DESCRIPTION..................................................................................................................... 5 FUNCTIONAL DESCRIPTION ................................................................................................... 6 5.1 5.2 5.3 RAM ................................................................................................................................ 6 Timers 0, 1 and 2............................................................................................................ 7 5.2.1 5.3.1 5.3.2 Timer 2 Output .................................................................................................................7 Crystal Oscillator ..............................................................................................................7 External Clock ..................................................................................................................7 Idle Mode..........................................................................................................................8 Power-down Mode............................................................................................................8 Reduce EMI Emission ......................................................................................................8 W78L365A Special Function Registers (SFRs) and Reset Values...................................9 Port Options Register .....................................................................................................10 Clock ............................................................................................................................... 7 5.4 Power Management........................................................................................................ 8 5.4.1 5.4.2 5.4.3 5.5 5.6 Reset............................................................................................................................... 9 5.5.1 5.6.1 5.6.2 5.6.3 Port 4 ............................................................................................................................ 10 INT2 / INT3 ..................................................................................................................10 Port 4 Base Address Registers ......................................................................................13 5.7 5.8 5.9 5.10 5.11 6. 6.1 6.2 6.3 6.4 7. Pulse Width Modulated Outputs (PWM)....................................................................... 14 Watchdog Timer ........................................................................................................... 17 In-System Programming (ISP) Mode............................................................................ 19 5.9.1 In-System Programming Control Register (CHPCON) ...................................................20 Software Reset ............................................................................................................. 21 H/W Reboot Mode (Boot from LDROM) ....................................................................... 21 Lock Bit ......................................................................................................................... 24 MOVC Inhibit................................................................................................................. 24 Encryption ..................................................................................................................... 25 Oscillator Control .......................................................................................................... 25 SECURITY ................................................................................................................................ 24 ELECTRICAL CHARACTERISTICS......................................................................................... 26 Publication Release Date: January 10, 2007 Revision A7 -1- W78LE365/W78L365A 7.1 7.2 7.3 8. 8.1 8.2 8.3 8.4 9. 9.1 9.2 10. 10.1 10.2 10.3 10.4 11. 12. 11.1 Absolute Maximum Ratings .......................................................................................... 26 D.C. Characteristics...................................................................................................... 26 A.C. Characteristics ...................................................................................................... 28 Program Fetch Cycle .................................................................................................... 29 Data Read Cycle........................................................................................................... 30 Data Write Cycle........................................................................................................... 31 Port Access Cycle......................................................................................................... 32 External Program Memory and Crystal ........................................................................ 33 Expanded External Data Memory and Oscillator ......................................................... 34 40-pin DIP ..................................................................................................................... 35 44-pin PLCC ................................................................................................................. 35 44-pin PQFP ................................................................................................................. 36 48-pin LQFP.................................................................................................................. 36 In-system Programming Software Examples ............................................................... 37 TIMING WAVEFORMS ............................................................................................................. 29 TYPICAL APPLICATION CIRCUIT........................................................................................... 33 PACKAGE DIMENSIONS ......................................................................................................... 35 APPLICATION NOTE ............................................................................................................... 37 REVISION HISTORY ................................................................................................................ 42 -2- W78LE365/W78L365A 1. GENERAL DESCRIPTION The W78L365A is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78L365A is fully compatible with the standard 8052. The W78L365A contains a 64K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the contents of the 64KB main ROM to be updated by the loader program located at the 4KB auxiliary ROM; 256+1K bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the W78L365A allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78L365A microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. 2. • • • • • • • • • • • • • • • • FEATURES Fully static design 8-bit CMOS microcontroller 64K bytes of in-system programmable Flash EPROM for Application Program (APROM) 4K bytes of auxiliary ROM for Loader Program (LDROM) 256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable) Four 8-bit bi-directional ports One 4-bit multipurpose programmable port (I/O, interrupt, Chip select function) Three 16-bit timer/counters One full duplex serial port Watchdog timer Software Reset P1.0 T2 programmable clock out Eight-sources, two-level interrupt capability Up to 20 MHz Built-in power management Code protection Packaged in − Lead Free (RoHS) DIP 40: − Lead Free (RoHS) QFP 44: W78L365A24DL W78L365A24FL − Lead Free (RoHS) PLCC 44: W78L365A24PL − Lead Free (RoHS) LQFP 48: W78L365A24LL -3- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 3. PIN CONFIGURATIONS 44-pin PLCC 40-pin DIP T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 T 2 E X , PPPP 1111 .... 4321 / I N TT 23 ,, PP 1 4V ..D 0 2D A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPPP TS422 AS. . . L 001 1 ,, AA 89 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 44-pin PQFP T 2 E X , PPPP 1111 .... 4321 T 2 , P 1 . 0 / I A N D T 0 3 , , P P 4V0 .D. 2D0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 P1.5 P1.6 P1.7 RST P3.0 P4.3 P3.1 P3.2 P3.3 P3.4 P3.5 NC 1 2 3 4 5 6 7 8 9 10 11 12 48-pin LQFP P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 44 43 42 41 40 39 38 37 36 35 34 1 33 32 2 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 XVPP TS42 AS. . L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 36 35 34 33 32 31 30 29 28 27 26 25 NC P0.4 P0.5 P0.6 P0.7 EA P4.1 ALE PSEN P2.7 P2.6 P2.5 -4- W78LE365/W78L365A 4. PIN DESCRIPTION SYMBOL TYPE DESCRIPTIONS EA I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus if the EA pin is high. PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: ground potential. POWER SUPPLY: Supply voltage for operation. PSEN OH ALE RST XTAL1 XTAL2 VSS VDD P0.0−P0.7 P1.0−P1.7 P2.0−P2.7 P3.0−P3.7 P4.0−P4.7 OH IL I O I I I/O D PORT 0: Function is the same as that of standard 8052. I/O H PORT 1: Function is the same as that of standard 8052. PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. The P2.6 and P2.7 also provide the alternate function REBOOT which is H/W reboot from LD flash. PORT 4: A bi-directional I/O. The P4.3 also provide the alternate function REBOOT which is H/W reboot from LD flash. I/O H I/O H PORT 3: Function is the same as that of the standard 8052. I/O H * Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain -5- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 5. FUNCTIONAL DESCRIPTION The W78L365A architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. 5.1 RAM The internal data RAM in the W78L365A is 256+1K bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways. • • • RAM 0H−7FH can be addressed directly and indirectly as the same as in 8051. Address pointers are R0 and R1 of the selected register bank. RAM 80H−FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0, R1 of the selected registers bank. AUX-RAM 0H−3FFH is addressed indirectly as the same way to access external data memory with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than 3FFH will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is enable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When executing from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD . REG REG REG F6H BFH A1H Example: CHPENR CHPCON XRAMAH MOV MOV ORL MOV MOV MOV MOV MOVX MOV MOV MOVX MOV MOV MOVX MOV MOVX CHPENR, #87H CHPENR, #59H CHPCON, #00010000B CHPENR, #00H XRAMAH, #01H R0, #23H A, #55H @R0, A XRAMAH, #02H R1, #FFH A, @R1 DPTR, #0134H A, #78H @DPTR,A DPTR, #7FFFH A, @DPRT ; enable AUX-RAM ; internal high address ; Write 55h data to 0123h AUX-RAM address. ; Read data from 02FFh AUX-RAM address. ; Write 78h data to 0134h AUX-RAM address. ; Read data from the external 7FFFh address SRAM -6- W78LE365/W78L365A 5.2 Timers 0, 1 and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. 5.2.1 Timer 2 Output If set T2OE (T2MOD.1) bit and clear C/T2 (T2CON.1) bit at auto-reload mode, P1.0 will be toggled once overflow. TIMER 2 Mode Bit: 7 6 5 4 3 2 1 T2OE 0 Mnemonic: T2MOD Address: C9H T2OE: Enable this bit to toggle P1.0 pin while Timer2 has been overflowed. 5.3 Clock The W78L365A is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78L365A relatively insensitive to duty cycle variations in the clock. 5.3.1 Crystal Oscillator The W78L365A incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. 5.3.2 External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. -7- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 5.4 Power Management 5.4.1 Idle Mode Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. 5.4.2 Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered. 5.4.3 Reduce EMI Emission The W78L365A allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency. The value of C1 and C2 may need some adjustment while running at lower gain. ALE OFF Function Auxiliary Register Bit: 7 6 5 4 3 2 1 0 ALEOFF Mnemonic: AUXR ALEOFF : Set this bit to disable ALE output. Address: 8EH -8- W78LE365/W78L365A 5.5 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L365A is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. 5.5.1 F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 Notes: W78L365A Special Function Registers (SFRs) and Reset Values +B 00000000 CHPENR 00000000 +ACC 00000000 +P4 11111111 +PSW 00000000 +T2CON 00000000 +XICON 00000000 +IP 00000000 +P3 00000000 +IE 00000000 +P2 11111111 +SCON 00000000 +P1 11111111 +TCON 00000000 +P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DPL 00000000 TL1 00000000 DPH 00000000 XRAMAH 00000000 SBUF xxxxxxxx P41AL 00000000 TH0 00000000 P40AL 00000000 P41AH 00000000 TH1 00000000 P40AH 00000000 AUXR 00000000 POR 00000000 WDTC 00000000 PCON 00110000 P43AL 00000000 P42AL 00000000 P43AH 00000000 P42AH 00000000 P4CSIN 00000000 T2MOD 00000000 RCAP2L 00000000 P4CONA 00000000 RCAP2H 00000000 P4CONB 00000000 TL2 00000000 SFRAL 00000000 TH2 00000000 SFRAH 00000000 PWMCON2 00000000 SFRFD 00000000 PWM4 00000000 SFRCN 00000000 CHPCON 0xx00000 PWMP 00000000 PWM0 00000000 PWM1 00000000 PWMCON1 00000000 PWM2 00000000 PWM3 00000000 1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable. 2. The text of SFR with bold type characters are extension function registers. -9- Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 5.6 Port 4 Port 4, address D8H, is a 8-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation modes. Mode 0: P4.0−P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as external interrupt PSEN and INT2 if enabled. Mode 1: P4.0−P4.3 are read strobe signals that are synchronized with RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 2: P4.0−P4.3 are write strobe signals that are synchronized with WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 3: P4.0−P4.3 are read/write strobe signals that are synchronized with RD or WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode. The high nibble of port4(P4.4 to P4.7) can be selected to serve to the direct LED display drive outputs by setting the HDx bit is set, the corresponding pin p4.x can sink about 20 mA current for driving LED display directly. 5.6.1 Port Options Register Bit: 7 6 5 4 HD47 3 HD46 2 HD45 1 HD44 0 P0UP Mnemonic: POR Address: 86H HD47-44: Enable pins P4.4 to P4.7 individually with high drive outputs. P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or standart port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with internal pull-up that is structurally the same Port2. 5.6.2 INT2 / INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. - 10 - W78LE365/W78L365A XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2 PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt information: INTERRUPT SOURCE VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL External Interrupt 0 Timer/Counter 0 External Interrupt 1 Timer/Counter 1 Serial Port Timer/Counter 2 External Interrupt 2 External Interrupt 3 P4CONB (C3H) BIT NAME 03H 0BH 13H 1BH 23H 2BH 33H 3BH 0 (highest) 1 2 3 4 5 6 7 (lowest) IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 XICON.2 XICON.6 TCON.0 TCON.2 XICON.0 XICON.3 FUNCTION 00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1. 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 7, 6 P43FUN1 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. P43FUN0 11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1, and P43CMP0. - 11 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A P4CONB (C3H), continued BIT NAME FUNCTION Chip-select signals address comparison: 00: Compare the full address (16 bits length) with the base address register P43AH, P43AL. 5, 4 P43CMP1 01: Compare the 15 high bits (A15−A1) of address bus with the base address register P43AH, P43AL. P43CMP0 10: Compare the 14 high bits (A15−A2) of address bus with the base address register P43AH, P43AL. 11: Compare the 8 high bits (A15−A8) of address bus with the base address register P43AH, P43AL. 3, 2 1, 0 P42FUN1 The P4.2 function control bits which are the similar definition as P43FUN1, P42FUN0 P43FUN0. P42CMP1 The P4.2 address comparator length control bits which are the similar definition P42CMP0 as P43CMP1, P43CMP0. P4CONA (C2H) BIT NAME FUNCTION 7, 6 5, 4 3, 2 1, 0 P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1, P41FUN0 P43FUN0. P41CMP1 The P4.1 address comparator length control bits which are the similar definition P41CMP0 as P43CMP1, P43CMP0. P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1, P40FUN0 P43FUN0. P40CMP1 The P4.0 address comparator length control bits which are the similar definition P40CMP0 as P43CMP1, P43CMP0. P4CSIN (AEH) BIT 7 6 5 4 3 2 1 0 NAME P43CSINV P42CSINV P41CSINV P40CSINV FUNCTION The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe signal. = 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe signal. = 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal. The similarity definition as P43SINV. The similarity definition as P43SINV. The similarity definition as P43SINV. Reserve Reserve 0 0 - 12 - W78LE365/W78L365A 5.6.3 Port 4 Base Address Registers P40AH, P40AL: The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address. P41AH, P41AL: The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address. P42AH, P42AL: The Base address register for comparator of P4.2. P42AH contains the high-order byte of address, P42AL contains the low-order byte of address. P43AH, P43AL: The Base address register for comparator of P4.3. P43AH contains the high-order byte of address, P43AL contains the low-order byte of address. P4 (D8H) BIT NAME FUNCTION 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 I/O pin I/O pin. I/O pin. I/O pin. Port 4 Data bit which outputs to pin P4.3 at mode 0. Port 4 Data bit. which outputs to pin P4.2 at mode 0. Port 4 Data bit. which outputs to pin P4.1at mode 0. Port 4 Data bit which outputs to pin P4.0 at mode 0. Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H−1237H and positive polarity, and P4.1−P4.3 are used as general I/O ports. P4.4−P4.7 is only available for 48 pin package. MOV P40AH, #12H MOV P40AL, #34H MOV P4CONA, #00001010B MOV P4CONB, #00H MOV P2ECON, #10H ; Base I/O address 1234H for P4.0 ; P4.0 a write strobe signal and address line A0 and A1 are masked. ; P4.1−P4.3 as general I/O port which are the same as PORT1 ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity ; default is negative. Then any instruction MOVX @DPTR, A (with DPTR = 1234H−1237H) will generate the positive polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of data #XX to pin P4.3−P4.1. - 13 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A P4 REGISTER P4.x P4xCSINV DATA I/O RD_CS MUX 4->1 WR_CS READ WRITE RD/WR_CS PIN P4.x ADDRESS BUS EQUAL REGISTER P4xAL P4xAH P4xFUN0 P4xFUN1 Bit Length Selectable comparator REGISTER P4xCMP0 P4xCMP1 P4.x INPUT DATA BUS 5.7 Pulse Width Modulated Outputs (PWM) There are five pulse width modulated output channels to generate pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts modular 255 (0−254). The value of the 8-bit counter compared to the contents of five registers: PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either these registers is greater than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3 or PWM4 output is set HIGH. If the contents of these registers are equal to, or less than the counter value, the output will be LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2, PWM3 and PWM4. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of 1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3 and ENPWM4 bit will enable or disable PWM output. Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to the contents of PWM0/1/2/3/4. The repetition frequency fpwm , at the PWM0/1/2/3/4 output is given by: fpwm = fosc 2 × (1 + PWMP) × 255 (PWMn) 255 - (PWMn) Prescaler division factor = PWM + 1 PWMn high/low ratio of PWMn = - 14 - W78LE365/W78L365A This gives a repetition frequency range of 123 Hz to 31.4 KHz ( fosc = 16 MHz). By loading the PWM registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the PWM registers when they are loaded with FFH. When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4) is loaded with a new value, the associated output updated immediately. It does not have to wait until the end of the current counter period. There is weakly pulled high on PWM output. ENPWM0/1/2/3/4 PWM0 f osc 1/2 Prescaler PWMP PWM1 8bit counter comparator PWM0OE PWM0 (P1.3) PWM1OE PWM1 (P1.4) comparator comparator PWM2 8bit counter PWM3OE PWM3 comparator 8bit counter PWM4OE PWM4 comparator PWM4 (P1.7) PWM3 (P1.6) PWM2OE PWM2 (P1.5) FIGURE 1 PWM DIAGRAM Please refer as below code. mov mov mov jb mov jb mov pwmcon1, #00110011b pwmcon2, #00000101b pwmp, #40h p1.3, $ pwm0, #14h p1.4, $ pwm1, #18h Publication Release Date: January 10, 2007 Revision A7 ; duty cycle high/low = pwm0/(255-pmw0) ; enable pwm3, 2, 1, 0 ; enable pwm4 ; Fpwm = XT/(2*(1+pwmp)*255) - 15 - W78LE365/W78L365A jb mov jb mov jb mov mov p1.5, $ pwm2, #20h p1.6, $ pwm3, #b0h p1.7, $ pwm4, #40h pwmcon1, #11111111b ;output enable pwm3, 2, 1, 0 PWM3 Register Bit: 7 6 5 4 3 2 1 0 Mnemonic: PWM3 PWM2 Register Bit: 7 6 5 4 Address: DEH 3 2 1 0 Mnemonic: PWM2 PWM Control 1 Register Bit: 7 PWM3OE Address: DDH 6 PWM2OE 5 ENPWM3 4 ENPWM2 3 PWM1OE 2 PWM0OE 1 ENPWM1 0 ENWPM0 Mnemonic: PWMCON1 PWM3OE: Output enable for PWM3 PWM2OE: Output enable for PWM2 ENPWM3: Enable PWM3 ENPWM2: Enable PWM2 PWM1OE: Output enable for PWM1 PWM0OE: Output enable for PWM0 ENPWM1: Enable PWM1 ENPWM0: Enable PWM0 PWM1 Register Bit: 7 6 5 4 Address: DCH 3 2 1 0 Mnemonic: PWM1 Address: DBH - 16 - W78LE365/W78L365A PWM0 Register Bit: 7 6 5 4 3 2 1 0 Mnemonic: PWM0 PWMP Register Bit: 7 6 5 4 Address: DAH 3 2 1 0 Mnemonic: PWMP PWM4 Register Bit: 7 6 5 4 Address: D9H 3 2 1 0 Mnemonic: PWM4 PWM Control 2 Register Bit: 7 6 5 4 - Address: CFH 3 2 PWM4OE 1 - 0 ENWPM4 Mnemonic: PWMCON2 PWM4OE: Output enable for PWM4 ENPWM: Enable for PWM4 Address: CEH 5.8 Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electromagnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 ENW 6 CLRW 5 WIDL 4 3 2 PS2 1 PS1 0 PS0 Mnemonic: WDTC Address: 8FH ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared. Publication Release Date: January 10, 2007 Revision A7 - 17 - W78LE365/W78L365A PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2−0 as follows: PS2 PS1 PS0 PRESCALER SELECT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 4 8 16 32 64 128 256 The time-out period is obtained using the following equation: 1 × 214 × PRESCALER × 1000 × 12 mS OSC Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset. ENW EXTERNAL RESET PRESCALER 14-BIT TIMER CLEAR WIDL IDLE OSC 1/12 INTERNAL RESET Watchdog Timer Block Diagram CLRW Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 19.66 mS 39.32 mS 78.64 mS 157.28 mS 314.57 mS 629.14 mS 1.25 S 2.50 S - 18 - W78LE365/W78L365A 5.9 In-System Programming (ISP) Mode The W78L365A equips one 64K byte of main ROM bank for application program (called APROM) and one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the W78L365A allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON register write attribute. The W78L365A achieves all in-system programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode, software may use timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for revising contents of APROM, software located at APROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in LDROM. Because the device will clear the program counter while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The device offers a software reset for switching back to APROM while the content of APROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset to reset the CPU. The software reset serves as a external reset. This in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible to easily update the system firmware without opening the chassis. SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode. SFRAH contains the high-order byte of address, SFRAL contains the low-order byte of address. SFRFD: The programming data for on-chip ROM in programming mode. SFRCN: The control byte of on-chip ROM programming mode. SFRCN (C7) BIT NAME FUNCTION 7 6 5 4 3, 2, 1, 0 WFWIN OEN CEN CTRL[3:0] Reserve. On-chip ROM bank select for in-system programming. = 0: 64K bytes ROM bank is selected as destination for re-programming. = 1: 4K bytes ROM bank is selected as destination for re-programming. ROM output enable. ROM chip enable. The flash control signals - 19 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A MODE WFWIN CTRL OEN CEN SFRAH, SFRAL SFRFD Erase 64KB APROM Program 64KB APROM Read 64KB APROM Erase 4KB LDROM Program 4KB LDROM Read 4KB LDROM 0 0 0 1 1 1 0010 0001 0000 0010 0001 0000 1 1 0 1 1 0 0 0 0 0 0 0 X Address in Address in X Address in Address in X Data in Data out X Data in Data out 5.9.1 In-System Programming Control Register (CHPCON) CHPCON (BFH) BIT NAME FUNCTION 7 6 5 4 3 2 1 0 SWRESET LD/AP ENAUXRAM 1 FBOOTSL FPROGEN When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. Reserve. This bit is read only. 1: CPU is running LDROM program. 0: CPU is running APROM program. 1: Enable on-chip AUX-RAM. 0: Disable the on-chip AUX-RAM Must be 1 Reserve. When this bit is set to 1, and both SWRESET and FPROGEN are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. When this bit is set to 1, and both SWRESET and FBOOTSL are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. This register is protected by CHPENR register. Please write as below procedures while you would like to write CHPCON register. Mov CHPENR, #87h Mov CHPENR, #59h Anl CHPCON, #EFh ;Disable AUX-RAM Mov CHPENR, #0h - 20 - W78LE365/W78L365A 5.10 Software Reset Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFLASH after time out. 5.11 H/W Reboot Mode (Boot from LDROM) By default, the W78L365A boots from APROM program after a power on reset. On some occasions, user can force the W78L365A to boot from the LDROM program via following settings. The possible situation that you need to enter H/W REBOOT mode when the APROM program can not run properly and device can not jump back to LDROM to execute in-system programming function. Then you can use this H/W REBOOT mode to force the W78L365A jumps to LDROM and executes in-system programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel. When the APROM program fails to execute the normal application program. User can press both two buttons at the same time and then turn on the power of the personal computer to force the W78L365A to enter the H/W REBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or H/W REBOOT mode. It is necessary to add 10K resistor on these P2.6, P2.7 and P4.3 pins. H/W Reboot MODE P4.3 P2.7 P2.6 MODE X L L X L X REBOOT REBOOT The Reset Timing For Entering F04KBOOT Mode P2.7 Hi-Z P2.6 Hi-Z RST 30 mS 10 mS - 21 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A The Algorithm of In-System Programming Part 1:32KB APROM START procedure of entering In-System Programming Mode Enter In-System Programming Mode ? (conditions depend on user's application) Yes No Setting control registers MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Execute the normal application program Setting Timer (about 1.5 us) and enable timer interrupt END Start Timer and enter idle Mode. (CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode) CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program. Go - 22 - W78LE365/W78L365A Part 2: 4KB LDROM Go Procedure of Updating the 32KB APROM Timer Interrupt Service Routine: Stop Timer & disable interrupt PGM Is F04KBOOT Mode? (CHPCON.7=1) No Yes End of Programming ? Yes No Reset the CHPCON Register: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Setting Timer and enable Timer interrupt for wake-up . (50us for program operation) Is currently in the F04KBOOT Mode ? No Software reset CPU and re-boot from the 32KB APROM. MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#83H Yes Get the parameters of new code Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) (Address and data bytes) through I/O ports, UART or other interfaces. Setting erase operation mode: MOV SFRCN,#22H (Erase 32KB APROM) Setting control registers for programming: MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H Start Timer and enter IDLE Mode. (Erasing...) Hardware Reset to re-boot from new 32 KB APROM. (S/W reset is invalid in F04KBOOT Mode) End of erase operation. CPU will be wakened by Timer interrupt. END Executing new code from address 00H in the 32KB APROM. PGM - 23 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 6. SECURITY During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly. Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM and those operations on it are described below. The W78L365A has a Security Register that can be accessed in programming mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the LDROM space. B7 Reserved B2 B1 B0 Security Bits 4KB On-chip ROM Program Memory LDROM 0000h 32KB On-chip ROM Program Memory 0FFFh APROM B0: Lock bit, logic 0: active B1: MOVC inhibit, logic 0: the MOVC instruction in external memory cannot access the code in internal memory. logic 1: no restriction. B2: Encryption logic 0: the encryption logic enable logic 1: the encryption logic disable B07: Osillator Control logic 0: 1/2 gain logic 1: Full gain Default 1 for all security bits. Reserved bits must be kept in logic 1. Reserved Reserved 7FFFh Security Register FFFFh Special Setting Register 6.1 Lock Bit This bit is used to protect the customer's program code in the W78L365A. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the ROM data and Security Register can not be accessed again. 6.2 MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. - 24 - W78LE365/W78L365A 6.3 Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. 6.4 Oscillator Control W78L365A/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 20 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. - 25 - Publication Release Date: January 10, 2007 Revision A7 W78LE365/W78L365A 7. 7.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings PARAMETER SYMBOL MIN. MAX. UNIT DC Power Supply Input Voltage Operating Temperature Storage Temperature VDD−VSS VIN TA TST -0.3 VSS -0.3 0 -55 +6.0 VDD +0.3 70 +150 V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 7.2 D.C. Characteristics SPECIFICATION MIN. MAX. UNIT (VSS = 0v, TA = 25°C, unless otherwise specified.) SYMBOL PARAMETER TEST CONDITIONS VDD IDD IIDLE IPWDN IIN1 IIN2 ILK ITL[*4] Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current P0, EA Logic 1 to 0 Transition Current P1, P2, P3, P4 2.4 2.7 -50 -10 -10 -10 -500 -50 5.5 5.5 20 2.5 6 1 10 10 +10 +150 50 +10 -200 -30 V V mA mA mA mA µA µA µA µA µA µA µA µA Without ISP With ISP No load VDD = 5.5V No load VDD = 2.4V VDD = 5.5V, Fosc = 20 MHz VDD = 2.4V, Fosc = 12 MHz VDD = 5.5V, Fosc = 20 MHz VDD = 2.4V, Fosc = 12 MHz VDD = 5.5V or 2.4V, VIN = 0V or VDD VDD = 5.5V, 0