W78LE812_06

W78LE812/W78L812A 8-BIT MICROCONTROLLER Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 PIN DESCRIPTION..................................................................................................................... 6 FUNCTIONAL DESCRIPTION ................................................................................................... 7 5.1 5.2 5.3 5.4 5.5 Timers 0, 1, and 2 ........................................................................................................... 7 Timer 2 Mode Control ..................................................................................................... 7 I/O Port Options .............................................................................................................. 8 5.3.1 5.4.1 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 Port Options Register ....................................................................................................8 Port 4.............................................................................................................................8 Interrupt Enable Register 0............................................................................................9 Interrupt Enable Register 1............................................................................................9 Interrupt Priority Register 0..........................................................................................10 Interrupt Priority Register 1..........................................................................................10 Interrupt Polarity Register ............................................................................................10 Interrupt Request Flag Register...................................................................................11 Watchdog Timer Control Register ...............................................................................12 Port 4 .............................................................................................................................. 8 Interrupt System ............................................................................................................. 9 5.6 5.7 5.8 Watchdog Timer ........................................................................................................... 12 5.6.1 Clock ............................................................................................................................. 13 Power Management...................................................................................................... 13 5.8.1 5.8.2 Idle Mode.....................................................................................................................13 Power-down Mode.......................................................................................................14 5.9 5.10 5.11 6. 6.1 6.2 6.3 6.4 6.5 AUXR - Auxiliary Register............................................................................................. 14 Reduce EMI Emission .................................................................................................. 14 Reset............................................................................................................................. 14 Read Operation ............................................................................................................ 15 Output Disable Condition.............................................................................................. 15 Program Operation ....................................................................................................... 15 Program Verify Operation ............................................................................................. 15 Erase Operation............................................................................................................ 15 ON-CHIP ROM CHARACTERISTICS ...................................................................................... 15 -1- Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 6.6 6.7 6.8 Erase Verify Operation ................................................................................................. 15 Program/Erase Inhibit Operation .................................................................................. 15 Security Bits .................................................................................................................. 16 6.8.1 6.8.2 6.8.3 Lock Bit........................................................................................................................17 MOVC Inhibit ...............................................................................................................17 Encryption....................................................................................................................18 7. 8. 9. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 18 DC CHARACTERISTICS.......................................................................................................... 19 AC CHARACTERISTICS .......................................................................................................... 21 9.1 9.2 9.3 9.4 9.5 9.6 Clock Input Waveform .................................................................................................. 21 Program Fetch Cycle .................................................................................................... 22 Data Read Cycle........................................................................................................... 22 Data Write Cycle ........................................................................................................... 22 Port Access Cycle......................................................................................................... 23 Program Operation ....................................................................................................... 23 Program Fetch Cycle .................................................................................................... 24 Data Read Cycle........................................................................................................... 24 Data Write Cycle ........................................................................................................... 25 Port Access Cycle......................................................................................................... 25 Program Operation ....................................................................................................... 26 Expanded External Program Memory and Crystal ....................................................... 27 Expanded External Data Memory and Oscillator ......................................................... 28 40-pin DIP ..................................................................................................................... 29 44-pin PLCC ................................................................................................................. 29 44-pin PQFP ................................................................................................................. 30 48-pin LQFP.................................................................................................................. 30 10. TIMING WAVEFORMS ............................................................................................................. 24 10.1 10.2 10.3 10.4 10.5 11. TYPICAL APPLICATION CIRCUITS ........................................................................................ 27 11.1 11.2 12. PACKAGE DIMENSIONS ......................................................................................................... 29 12.1 12.2 12.3 12.4 13. REVISION HISTORY ................................................................................................................ 31 -2- W78LE812/W78L812A 1. GENERAL DESCRIPTION The W78L812 is an 8-bit microcontroller which can accommodate a wide range of supply voltages with low power consumption. The instruction set for the W78L812 is fully compatible with the standard 8051. The W78L812 contains an 8K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 5-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by a fourteen sources two-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the W78L812 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78L812 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. 2. FEATURES Fully static design 8-bit CMOS microcontroller Wide supply voltage of 2.4V to 5.5V 256 bytes of on-chip scratchpad RAM 8 KB electrically erasable/programmable Flash EPROM 64 KB program memory address space 64 KB data memory address space Four 8-bit bi-directional ports Three 16-bit timer/counters Timer 2 Clock-out One full duplex serial port (UART) Watchdog Timer Direct LED drive outputs Fourteen sources, two-level interrupt capability Wake-up via external interrupts at Port 1 EMI reduction mode Built-in power management Code protection mechanism Packages: − Lead Free (RoHS) DIP 40: W78L812A24DL − Lead Free (RoHS) PLCC 44: W78L812A24PL − Lead Free (RoHS) PQFP 44: W78L812A24FL − Lead Free (RoHS) LQFP 48: W78L812A24LL -3- Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 3. PIN CONFIGURATIONS 40-Pin DIP INT2,,T2, P1.0 INT3,T2EX, P1.1 INT4,P1.2 INT5,P1.3 INT6,P1.4 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 A13CTR,LTXD, P3.1 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5 CE,WR, P3.6 OE,RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA,VPP ALE PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 44-Pin PLCC I N T 3 , T 2 E X , P 1 . 1 I N T 2 , T 2 , P 1 . 0 44-Pin PQFP I N T 3 , T 2 E X , P 1 . 1 I N T 2 , T 2 , P 1 . 0 I N T 6 , P 1 . 4 I N T 5 , P 1 . 3 I N T 4 , P 1 . 2 A D 0 , P P 4V0 .D. 2D0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 I N T 6 , P 1 . 4 I N T 5 , P 1 . 3 I N T 4 , P 1 . 2 A D 0 , P P 4V0 .D. 2D0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 P4.3 A13CTRL,TXD, P3.1 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5 6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R , / C E P 3 . 7 , / R D , / O E X T A L 2 XVPP TS42 AS. . L 00 1 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA,VPP P4.1 ALE PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 P4.3 A13CTRL,TXD, P3.1 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5 1 2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R , / C E P 3 . 7 , / R D , / O E X T A L 2 XVPPP TS422 AS. . . L 001 1 ,, AA 89 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA,VPP P4.1 ALE PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 -4- W78LE812/W78L812A -5- Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 4. PIN DESCRIPTION SYMBOL DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be present on the bus if EA pin is high and the program counter is within on-chip ROM area. Otherwise they will be present on the bus. EA PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/data bus during fetch and MOVC operations. When internal ROM access is PSEN performed, no PSEN strobe signal outputs from this pin. This pin also serves the alternative function P4.6. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the ALE address from the data on Port 0. RESET: A high on this pin for two machine cycles while the oscillator is running resets the RST device. XTAL1 CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. VSS GROUND: Ground potential VDD POWER SUPPLY: Supply voltage for operation. PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order P0.0 − P0.7 address/data bus during accesses to external memory. The pins of Port 0 can be individually configured to open-drain or standard port with internal pull-ups. PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below: P1.0 − P1.7 T2(P1.0): Timer/Counter 2 external count input T2EX(P1.1): Timer/Counter 2 Reload/Capture control INT2 − INT9 (P1.0 − P1.7): External interrupt 2 to 9 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the P2.0 − P2.7 upper address bits for accesses to external memory. PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7 can be configured with high sink current which can drive LED displays directly. All bits have alternate functions, which are described below: RXD(P3.0): Serial Port receiver input TXD(P3.1): Serial Port transmitter output P3.0 − P3.7 INT0 (P3.2): External Interrupt 0 INT1(P3.3): External Interrupt 1 T0(P3.4): Timer 0 External Input T1(P3.5): Timer 1 External Input WR (P3.6): External Data Memory Write Strobe RD (P3.7): External Data Memory Read Strobe PORT 4: A 5-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are P4.0 − P4.6 available on 44-pin PLCC/QFP package. P4.6 is the alternative function corresponding to PSEN . -6- W78LE812/W78L812A 5. FUNCTIONAL DESCRIPTION The W78L812 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. 5.1 Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78L812: it is a 16-bit up/down counter that is configured and controlled by the T2CON and T2MOD registers. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. In the auto-reload mode, Timer 2 performs a up counter which is similar with standard 8052. When counting up, an overflow in Timer 2 will cause a reload from RCAP2H and RCAP2L registers. The Timer 2 also provides a programmable clock-out mode as a clock generator. To enable this mode, timer 2 has to be configured with a 16-bit auto-reload timer (C/T2 = 0, CP/RL2 = 0) and bit T2OE (T2MOD.1) must be set to 1. This mode produces a 50% duty cycle clock output and timer 2 roll-overs will not generate an interrupt. The clock-out frequency depends on the oscillator frequency and the reload value of registers RCAP2H and RCAP2L. The clock-out frequency is determined by following equation: Clock-out Frequency = Oscillator Frequency / [4 × (65536-RCAP2H, RCAP2L)] OSC 1/2 TL2 TH2 1/2 T2 (P1.0) TR2 (T2CON.2) T2EX (P1.1) RCAP2L RCAP2H EXF2 EXEN2 (T2CON.3) Timer 2 Interrupt Timer 2 Clock-Out Mode T2CON.6 5.2 Timer 2 Mode Control Bit: 7 6 5 4 3 2 1 T2OE 0 - Mnemonic: T2MOD Address: C9h T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function. -7- Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 5.3 I/O Port Options The Port 0 and Port 3 of W78L812 may be configured with different types by setting the bits of the Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When the PUP bit in the POR register is set, the pins of Port 0 will perform a quasi-bidirectional I/O port with internal pull-up that is structurally the same as Port 2. The high nibble of Port 3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by setting the HDx bit in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink about 20mA current for driving LED display directly. After reset, the POR register is cleared and the pins of Ports 0 and 3 are the same as those of the standard 80C31. The POR register is shown below. 5.3.1 Port Options Register Bit: 7 EP6 6 5 4 HD7 3 HD6 2 HD5 1 HD4 0 PUP Mnemonic: POR PUP : Enable Port 0 weak pull-up. Address: 86H HD4 − 7: Enable pins P3.4 to P3.7 individually with High Drive outputs. EP6 : Enable P4.6. To set this bit shifts PSEN pin to the alternate function P4.6 5.4 Port 4 The W78L812 has one additional bit-addressable I/O port P4 in which the port address is D8H. The Port 4 contains seven bits; P4.0 to P4.3 are only available on 44-pin PLCC/QFP package; P4.6 is the alternate function corresponding to pin PSEN . When program is running in the internal memory without any access to external memory, PSEN may be individually configured to the alternate functions P4.6 that serve as general purpose I/O pins. To enable I/O port P4.6, the bit EP6 in the POR register must be set. During reset, the, PSEN perform as in the standard 80C32. The alternate functions P4.6 must be enabled by software. Care must be taken with the ALE pins when configured as the alternate functions. 5.4.1 Port 4 Bit: 7 6 P4.6 5 4 3 P4.3 2 P4.2 1 P4.1 0 P4.0 Mnemonic: P4 Address: D8H -8- W78LE812/W78L812A 5.5 Interrupt System The W78L812 has fourteen interrupt sources: INT 0 and INT1; Timer 0,1 and 2; Serial Port; INT2 to INT9. Each interrupt vectors to a specific location in program memory for its interrupt service routine. Each of these sources can be individually enabled or disabled by setting or clearing the corresponding bit in Special Function Register IE0 and IE1. The individual interrupt priority level depends on the Interrupt Priority Register IP0 and IP1. Additional external interrupts INT2 to INT9 are level sensitive and may be used to awake the device from power down mode. The Port 1 interrupts can be initialized to either active HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ register contains the flags of Port 1 interrupts. Each flag in IRQ register will be set when a interrupt request is recognized but must be cleared by software. Note that the interrupt flags have to be cleared before the interrupt service routine is completed, or else another interrupt will be generated. 5.5.1 Interrupt Enable Register 0 Bit: 7 EA 6 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Mnemonic: IE EA : Global enable. Enable/disable all interrupts. ET2: Enable Timer 2 interrupt. ES : Enable Serial Port interrupt. ET1: Enable Timer 1 interrupt EX1: Enable external interrupt 1 ET0: Enable Timer 0 interrupt EX0: Enable external interrupt 0 Address: A8H 5.5.2 Interrupt Enable Register 1 Bit: 7 EX9 6 EX8 5 EX7 4 EX6 3 EX5 2 EX4 1 EX3 0 EX2 Mnemonic: IE1 Address: E8H EX9: Enable external interrupt 9 Note: 0 = interrupt disabled, 1 = interrupt enabled. EX8: Enable external interrupt 8 EX7: Enable external interrupt 7 EX6: Enable external interrupt 6 EX5: Enable external interrupt 5 EX4: Enable external interrupt 4 EX3: Enable external interrupt 3 EX2: Enable external interrupt 2 -9- Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 5.5.3 Interrupt Priority Register 0 Bit: 7 6 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Mnemonic: IP0 IP.7: Unused. IP.6: Unused. PT2: This bit defines the Timer 2 interrupt priority. PS: This bit defines the Serial port 0 interrupt priority. PT1: This bit defines the Timer 1 interrupt priority. PX1: This bit defines the External interrupt 1 priority. PT0: This bit defines the Timer 0 interrupt priority. PX0: This bit defines the External interrupt 0 priority. Address: B8h PT2 = 1 sets it to higher priority level. PS = 1 sets it to higher priority level. PT1 = 1 sets it to higher priority level. PX1 = 1 sets it to higher priority level. PT0 = 1 sets it to higher priority level. PX0 = 1 sets it to higher priority level. 5.5.4 Interrupt Priority Register 1 Bit: 7 PX9 6 PX8 5 PX7 4 PX6 3 PX5 2 PX4 1 PX3 0 PX2 Mnemonic: IP1 PX9: PX8: PX7: PX6: PX5: PX4: PX3: PX2: This bit defines the External interrupt 9 priority. This bit defines the External interrupt 8 priority. This bit defines the External interrupt 7 priority. This bit defines the External interrupt 6 priority. This bit defines the External interrupt 5 priority. This bit defines the External interrupt 4 priority. This bit defines the External interrupt 3 priority. This bit defines the External interrupt 2 priority. Address: F8h PX9 = 1 sets it to higher priority level. PX8 = 1 sets it to higher priority level. PX7 = 1 sets it to higher priority level. PX6 = 1 sets it to higher priority level. PX5 = 1 sets it to higher priority level. PX4 = 1 sets it to higher priority level. PX3 = 1 sets it to higher priority level. PX2 = 1 sets it to higher priority level. 5.5.5 Interrupt Polarity Register Bit: 7 IL9 6 IL8 5 IL7 4 IL6 3 IL5 2 IL4 1 IL3 0 IL2 Mnemonic: IX IL9: External interrupt 9 polarity level. IL8: External interrupt 8 polarity level. IL7: External interrupt 7 polarity level. IL6: External interrupt 6 polarity level. IL5: External interrupt 5 polarity level. IL4: External interrupt 4 polarity level. IL3: External interrupt 3 polarity level. IL2: External interrupt 2 polarity level. Note: 0 = active LOW, 1 = active HIGH. Address: E9H - 10 - W78LE812/W78L812A 5.5.6 Interrupt Request Flag Register Bit: 7 IQ9 IQ9: IQ8: IQ7: IQ6: IQ5: IQ4: IQ3: IQ2: 6 IQ8 5 IQ7 4 IQ6 3 IQ5 2 IQ4 1 IQ3 0 IQ2 Mnemonic: IRQ External interrupt 9 request flag. External interrupt 8 request flag. External interrupt 7 request flag. External interrupt 6 request flag. External interrupt 5 request flag. External interrupt 4 request flag. External interrupt 3 request flag. External interrupt 2 request flag. Address: C0H Table.1 Priority level for simultaneous requests of the same priority interrupt sources SOURCE FLAG PRIORITY LEVEL VECTOR ADDRESS External Interrupt 0 Serial Port External Interrupt 5 Timer 0 Overflow External Interrupt 6 External Interrupt 1 External Interrupt 2 External Interrupt 7 Timer 1 Overflow Timer 2 Overflow External Interrupt 3 External Interrupt 8 External Interrupt 4 External Interrupt 9 IE0 RI + TI IQ5 TF0 IQ6 IE1 IQ2 IQ7 TF1 TF2 + EXF2 IQ3 IQ8 IQ4 IQ9 (Highest) 0003H 0023H 0053H 000BH 005BH 0013H 003BH 0063H 001BH 002BH 0043H 006BH 004BH (Lowest) 0073H - 11 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 5.6 Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electromagnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. 5.6.1 Watchdog Timer Control Register Bit: 7 ENW 6 CLRW 5 WIDL 4 3 2 PS2 1 PS1 0 PS0 Mnemonic: WDTC ENW : Enable watch-dog if set. Address: 8FH CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared. PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2 − 0 as follows: PS2 PS1 PS0 PRESCALER SELECT 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 2 4 8 16 32 64 128 256 The time-out period is obtained using the following equation: 1 × 214 × PRESCALER × 1000 × 12 mS OSC Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset. - 12 - W78LE812/W78L812A WIDL IDLE ENW EXTERNAL RESET 14-BIT TIMER CLEAR OSC 1/12 PRESCALER INTERNAL RESET Watchdog Timer Block Diagram CLRW Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 19.66 mS 39.32 mS 78.64 mS 157.28 mS 314.57 mS 629.14 mS 1.25 S 2.50 S 5.7 Clock The W78L812 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78L812 relatively insensitive to duty cycle variations in the clock. The W78L812 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. 5.8 5.8.1 Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. - 13 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 5.8.2 Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. 5.9 AUXR - Auxiliary Register Bit: 7 6 5 4 3 2 1 0 AO Mnemonic: AUXR AO: Turn off ALE signal. Address: 8Eh 5.10 Reduce EMI Emission Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space. 5.11 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L812 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. - 14 - W78LE812/W78L812A 6. ON-CHIP ROM CHARACTERISTICS The W78L812 has several modes to program the on-chip ROM. All these operations are configured by the pins RST, ALE, PSEN , A9CTRL (P3.0), A13CTRL (P3.1), A14CTRL (P3.2), OECTRL (P3.3), CE (P3.6), OE (P3.7), A0 (P1.0) and VPP ( EA ). Moreover, the A15 − A0 (P2.7 − P2.0, P1.7 − P1.0) and the D7 − D0 (P0.7 − P0.0) serve as the address and data bus respectively for these operations. 6.1 Read Operation This operation is supported for customer to read their code and the Security bits. The data will not be valid if the Lock bit is programmed to low. 6.2 Output Disable Condition When the OE is set to high, no data output appears on the D7… D0. 6.3 Program Operation This operation is used to program the data to Flash EPROM and the security bits. Program operation is done when the VPP is reach to VCP (12.5V) level, CE set to low, and OE set to high. 6.4 Program Verify Operation All the programming data must be checked after program operations. This operation should be performed after each byte is programmed; it will ensure a substantial program margin. 6.5 Erase Operation An erase operation is the only way to change data from 0 to 1. This operation will erase all the Flash EPROM cells and the security bits from 0 to 1. This erase operation is done when the VPP is reach to VEP level, CE set to low, and OE set to high. 6.6 Erase Verify Operation After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase margin. This operation will be done after the erase operation if VPP = VEP (14.5V), CE is high and OE is low. 6.7 Program/Erase Inhibit Operation This operation allows parallel erasing or programming of multiple chips with different data. When P3.6 ( CE ) = VIH, P3.7 ( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So, except for the P3.6 and P3.7 pins, the individual chips may have common inputs. - 15 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A P3.0 OPERATIONS (A9 P3.1 (A13 P3.2 (A14 P3.3 (OE P3.6 ( CE ) P3.7 ( OE ) EA P2, P1 P0 CTRL) CTRL) CTRL) CTRL) (VPP) (A15… A0) (D7… D0) NOTES Read Output Disable Program Program Verify Erase Erase Verify Program/ Erase Inhibit Notes: 0 0 0 0 1 1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 0 1 1 1 VCP VCP VEP VEP VCP/ VEP Address X Address Address A0:0, others: X Address X Data Out Hi-Z Data In Data Out Data In 0FFH Data Out X @3 @4 @5 1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH. 2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = VSS. 3. The program verify operation follows behind the program operation. 4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits. 5. The erase verify operation follows behind the erase operation. 6.8 Security Bits During the programmer operation mode, the Flash EPROM can be programmed and verified repeatedly. Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM and those operations on it are described below. The W78L812 has a Special Setting Register, the Security Register, which can not be accessed in normal mode. The register can only be accessed from the on-chip ROM operation mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The Security Register is addressed in the Flash EPROM operation mode by address #0FFFFh. - 16 - W78LE812/W78L812A D7 D6 D5 D4 D3 D2 D1 D0 Reserved B2 B1 B 0 Security Bits 8KB Flash EPROM Program M emory 0000h B0 : Lock bit, logic 0 : active B1 : M OVC inhibit, logic 0 : the M OVC instruction in external memory cannot access the code in internal m em ory. logic 1 : no restriction. B2 : Encryption logic 0 : the encryption logic enable logic 1 : the encryption logic disable 1FFFh Reserved Default 1 for all security bits. Reserved bits m ust be kept in logic 1. Security Register 0FFFFh Special Setting Register 6.8.1 Lock Bit This bit is used to protect the customer's program code in the W78L812. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the on-chip ROM data and Special Setting Registers can not be accessed again. 6.8.2 MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. - 17 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 6.8.3 Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. +5V +5V V DD A0 to A7 V IL V IL V IL V IL V IL V IH P1 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 X'tal2 Vss P0 EA/Vpp ALE RST PSEN PGM DATA A0 to A7 V IL V IL V IL V IL V IH V IL P1 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 X'tal2 Vss V DD P0 EA/Vpp ALE RST PSEN PGM DATA V CP V IL V IH V IH V CP V IL V IH V IH P2 A8 to A15 P2 A8 to A15 Programming Configuration Programming Verification 7. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN. MAX. UNIT DC Power Supply Input Voltage Operating Temperature Storage Temperature VDD − VSS VIN Ta TST -0.3 VSS -0.3 0 -55 +7.0 VDD +0.3 70 +150 V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. - 18 - W78LE812/W78L812A 8. DC CHARACTERISTICS VSS = 0V, TA = 25° C, unless otherwise specified. PARAMETER SYM. MIN. SPECIFICATION MAX. UNIT TEST CONDITIONS Operating Voltage VDD 2.4 - 5.5 20 3 7 1.5 50 30 V mA mA mA mA μA μA μA μA μA μA μA V V V V V V V V V V V VDD = 5.5V, 20 MHz, no load, RST = 1 VDD = 2.4V, 12 MHz, no load, RST = 1 VDD = 5.5V, 20 MHz, no load VDD = 2.4V, 12 MHz, no load VDD = 5.5V, no load VDD = 2.4V, no load VDD = 5.5V VIN = 0V or VDD VDD = 5.5V VSS < VIN < VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0V < VIN < VDD VDD = 5.5V VIN = 2V VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V Operating Current IDD - Idle Current IIDLE - Power Down Current Input Input Current P1, P2, P3, P4 Input Leakage Current P0, EA Input Current RST Input Leakage Current P0, EA Logic 1-to-0 Transition Current P1, P2, P3, P4 Input Low Voltage P1, P2, P3, P4 Input Low Voltage RST [*3] IPWDN - IIN ILK IIN2 ILK1 -50 -10 -10 -60 -500 0 0 0 0 0 0 3.5 1.6 3.5 1.7 3.5 1.6 +10 +10 +0 +300 0.8 0.5 0.8 0.3 0.8 0.6 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 Input Low Voltage XTAL1 [*3] VIL3 VIH1 VIH2 VIH3 Input High Voltage P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1 [*4] - 19 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A DC Characteristics, continued PARAMETER SYM. MIN. SPECIFICATION MAX. UNIT TEST CONDITIONS Output Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN [*4] VOL1 VOL2 VOL3 ISK1 ISK2 ISK3 VOH1 VOH2 ISR1 ISR2 4 1.8 10 4.5 12 2.4 1.4 2.4 1.4 -120 -20 -10 -1.9 0.45 0.25 0.45 0.25 0.22 12 5.4 18 9 24 -250 -40 -14 -3.3 V V V V V mA mA mA mA mA V V V V μA μA mA mA VDD = 4.5V, IOL = +2 mA VDD = 2.4V, IOL = +1 mA VDD = 4.5V, IOL = +4 mA VDD = 2.4V, IOL = +2 mA VDD = 4.5V, IOL = +2 mA VDD = 4.5V, VOL = 0.45V VDD = 2.4V, VOL = 0.4V VDD = 4.5V, VOL = 0.45V VDD = 2.4V, VOL = 0.4V VDD = 4.5V, VOL = 0.45V VDD = 4.5V, VOH = -100 μA VDD = 2.4V, VOH = -20 μA VDD = 4.5V, IOH = -400 μA VDD = 2.4V, IOH = -200 μA VDD = 4.5V, VOH = 2.4V VDD = 2.4V, VOH = 1.4V VDD = 4.5V, VOH = 2.4V VDD = 2.4V, VOH = 1.4V Output Low Voltage P3[*6] Sink current P1, P2, P3[5], P4 Sink current P0, ALE, PSEN , P4.6 Sink current P3.4 to P3.7 in High-Drive mode Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN Source current P1, P2, P3, P4 Source current P0, ALE, PSEN , P4.6 Notes: [*4] *1. RST pin has an internal pull-down. *2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0. *3. RST is a Schmitt trigger input and XTAL1 is a CMOS input. *4. P0, P2, ALE and PSEN are tested in the external access mode. *5. P3.4 to P3.7 are in normal mode. *6. P3 (P3.4 − P3.7) is used LED driver port by set SFR. - 20 - W78LE812/W78L812A 9. AC CHARACTERISTICS The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers. 9.1 Clock Input Waveform XTAL1 TCH F OP, TCP T CL PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed Clock Period Clock High Clock Low FOP TCP TCH TCL 0 50 25 25 - 20 - MHz nS nS nS 1 2 3 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. - 21 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 9.2 Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low Address Hold from ALE Low ALE Low to PSEN Low TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW 1 TCP -Δ 1 TCP -Δ 1 TCP -Δ 0 0 2 TCP -Δ 3 TCP -Δ 2 TCP 3 TCP 2 TCP 1 TCP 1 TCP - nS nS nS nS nS nS nS nS 4 1, 4 4 2 3 PSEN Low to Data Valid Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width PSEN Pulse Width 4 4 Notes: 1. P0.0 − P0.7, P2.0 − P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "Δ" (due to buffer driving delay and wire loading) is 20 nS. 9.3 Data Read Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES ALE Low to RD Low RD Low to Data Valid TDAR TDDA TDDH TDDZ TDRD 3 TCP -Δ 0 0 6 TCP -Δ 6 TCP 3 TCP +Δ 4 TCP 2 TCP 2 TCP - nS nS nS nS nS 1, 2 1 Data Hold from RD High Data Float from RD High RD Pulse Width Notes: 2 1. Data memory access time is 8 TCP. 2. "Δ" (due to buffer driving delay and wire loading) is 20 nS. 9.4 Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low Data Valid to WR Low Data Hold from WR High WR Pulse Width TDAW TDAD TDWD TDWR 3 TCP -Δ 1 TCP -Δ 1 TCP -Δ 6 TCP -Δ 6 TCP 3 TCP +Δ - nS nS nS nS Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS. - 22 - W78LE812/W78L812A 9.5 Port Access Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE TPDS TPDH TPDA 1 TCP 0 1 TCP - - nS nS nS Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. 9.6 Program Operation PARAMETER SYMBOL MIN. TYP. MAX. UNIT VPP Setup Time Data Setup Time Data Hold Time Address Setup Time Address Hold Time TVPS TDS TDH TAS TAH TPWP TOCS TOCH TOES TDFP TOEV 2.0 2.0 2.0 2.0 0 290 2.0 2.0 2.0 0 - 300 - 310 130 150 μS μS μS μS μS μS μS μS μS nS nS CE Program Pulse Width for Program Operation OECTRL Setup Time OECTRL Hold Time OE Setup Time OE High to Output Float Data Valid from OE and the PSEN pin must pull in VIH status. Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, - 23 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 10. TIMING WAVEFORMS 10.1 Program Fetch Cycle S1 XTAL1 T ALW ALE T APL PSEN T PSW T AAS PORT 2 T AAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 T PDA T PDH, T PDZ S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 10.2 Data Read Cycle S4 XTAL1 ALE PSEN PORT 2 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 A8-A15 A0-A7 DATA T DAR T DDA PORT 0 T DDH, T DDZ RD T DRD - 24 - W78LE812/W78L812A 10.3 Data Write Cycle S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR A0-A7 A8-A15 DATA OUT S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 T DAD TDWD TDAW TDWR 10.4 Port Access Cycle S5 XTAL1 S6 S1 ALE TPDS PORT INPUT SAMPLE T PDH T PDA DATA OUT - 25 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 10.5 Program Operation Program P2, P1 (A15... A0) P3.6 (CE) P3.3 (OECTRL) P3.7 (OE) P0 (A7... A0) VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL Vcp Vpp VIH TVPS Data In TDS Program Verify Read Verify Address Stable TAS TPWP TAH TOCS TOCH TOES TDH D OUT TDFP Address Valid Data Out TOEV - 26 - W78LE812/W78L812A 11. TYPICAL APPLICATION CIRCUITS 11.1 Expanded External Program Memory and Crystal Figure A CRYSTAL C1 C2 R 16 MHz 20 MHz 30P 15P 30P 15P - Above table shows the reference values for crystal applications. Note: C1, C2, R components refer to Figure A. - 27 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A Typical Application Circuits, continued 11.2 Expanded External Data Memory and Oscillator VDD VDD 31 19 10 u EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD W R PSEN ALE TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 O C G 74373 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE O E W R 20256 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 O SCILLA R TO 18 8.2 K 9 12 13 14 15 1 2 3 4 5 6 7 8 GD 1 N 11 G D 20 N 22 27 W 78LE812/W 78L812A Figure B - 28 - W78LE812/W78L812A 12. PACKAGE DIMENSIONS 12.1 40-pin DIP Symbol Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.254 3.81 0.406 1.219 0.203 3.937 4.064 0.457 0.559 1.27 1.372 5.334 D 40 21 E1 A A1 A2 B B1 c D E E1 e1 L a 0.254 0.356 52.20 52.58 0.610 14.986 15.24 15.494 0.550 0.110 0.140 15 0.670 0.090 13.72 2.286 3.048 0 16.00 16.51 13.84 2.54 3.302 13.97 2.794 3.556 15 17.01 2.286 1 S 20 E c eA S Notes: A A2 A1 Base Plane Seating Plane L B B1 e1 a eA 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 12.2 44-pin PLCC HD D 6 1 44 40 Symbol Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 39 7 E HE GE 17 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Notes: 0.185 0.020 0.508 4.699 0.145 0.150 0.155 3.683 3.81 3.937 0.026 0.028 0.032 0.66 0.711 0.813 0.016 0.018 0.022 0.406 0.457 0.559 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 0.648 0.653 0.658 16.46 16.59 16.71 0.050 BSC 1.27 BSC 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.296 0.004 2.54 2.794 0.10 L A2 A θ e Seating Plane GD b b1 A1 y 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. - 29 - Publication Release Date: November 6, 2006 Revision A9 W78LE812/W78L812A 12.3 44-pin PQFP HD D Dimension in inch Dimension in mm Symbol 44 34 Min. Nom. Max. --0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7 Min. Nom. Max. --0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6 --0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08 0 7 1 33 E HE 11 12 e b 22 A A1 A2 b c D E e HD HE L L1 y θ Notes: c A2 A A1 y θ L L1 Detail F Seating Plane See Detail F 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. 12.4 48-pin LQFP HD D 36 25 Symbol Dimension in mm Min. Nom. --0.05 1.35 0.17 0.09 ----1.40 0.20 --7.00 7.00 0.50 9.00 9.00 0.45 0.60 1.00 --0 0.08 3.5 --7 0.75 Max. 1.60 0.15 1.45 0.27 0.20 37 24 E HE 48 13 1 e b 12 A A1 A2 b c D E e HD HE L L1 y 0 Notes: c A2 A Seating Plane See Detail F A1 y L L1 Detail F 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. - 30 - W78LE812/W78L812A 13. REVISION HISTORY VERSION DATE PAGE REASONS FOR CHANGE A5 A6 A7 A8 October 15, 2001 April 19, 2005 July 1, 2005 June 19, 2006 26 3 3,5 31 13,14 Add Important Notice Add lead free (RoHS) parts Add a part in 48-pin LQFP part Add package spec of 48-pin LQFP Correct the watchdog prescale table Remove block diagram 3 Remove all Leaded package parts A9 November 6, 2006 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 31 - Publication Release Date: November 6, 2006 Revision A9